feat(rdaspen/ras): add DT buffer and IRQ setup

Added node to map reserved memory for CPER.
Interrupt set from TF-A for RAS error notification.

Change-Id: Id7e296772275cdf76c81d8d62294b0bce94bbf57
S

feat(rdaspen/ras): add DT buffer and IRQ setup

Added node to map reserved memory for CPER.
Interrupt set from TF-A for RAS error notification.

Change-Id: Id7e296772275cdf76c81d8d62294b0bce94bbf57
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>

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Merge "fix(rdaspen): dts: make cache nodes DT spec compliant" into integration

fix(tc): configure mte addresses and sizes

- Use the carveout address specified by the MCN Top-level
design spec. The total size of the MTE carveout is 1/32 of
the available DRAM.
- MTE carveout

fix(tc): configure mte addresses and sizes

- Use the carveout address specified by the MCN Top-level
design spec. The total size of the MTE carveout is 1/32 of
the available DRAM.
- MTE carveout is not included when building FVP.
FVP's do not require a physical carveout to
emulate MTE, so we can save the memory.
- Add memory map diagrams to platform_def.h
- Tidy up existing memory map macros.

Change-Id: I4d31aa27e470344d4ed6469939331d0e2ced9d54
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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fix(rdaspen): dts: make cache nodes DT spec compliant

The Devicetree specification demands that L2 and L3 cache nodes using
the unified property names (cache-size instead of
i-cache-size/d-cache-siz

fix(rdaspen): dts: make cache nodes DT spec compliant

The Devicetree specification demands that L2 and L3 cache nodes using
the unified property names (cache-size instead of
i-cache-size/d-cache-size), are required to carry a "cache-unified"
boolean property. Also the node names must be just "l2-cache" or
"l3-cache", without any further numbering. Finally there should be no
specific compatible string for the L3 cache, just "cache" is enough.

Fix the cache description in the RDAspen devicetree to make it pass
the Linux kernel DTB checks.

Change-Id: If634c8e841ceb5c83079738d82fcdb9c13d327ad
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(fvp): fully remove FVP_Foundation

It was removed with patch 4f6c9397b61824b320f7b16b6267d9928dc88998 but
some bits remain. Remove them.

Change-Id: Ia40d97ca81983006e470b061d913d238cf73b6f9
Sign

fix(fvp): fully remove FVP_Foundation

It was removed with patch 4f6c9397b61824b320f7b16b6267d9928dc88998 but
some bits remain. Remove them.

Change-Id: Ia40d97ca81983006e470b061d913d238cf73b6f9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(morello): fix the incorrect order of gpu interrupts in dt

Declare the GPU DT interrupts in the same order as defined
in the DT schema for arm,mali-bifrost.

Signed-off-by: Chandni Cherukuri <cha

fix(morello): fix the incorrect order of gpu interrupts in dt

Declare the GPU DT interrupts in the same order as defined
in the DT schema for arm,mali-bifrost.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
Change-Id: If3e72d33dcba4143900a5032688cf9340c717259

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fix(stm32mp2-fdts): set SDMMC max frequency to 166 MHz on stm32mp25

Set SDMMC max frequency to 166 MHz on stm32mp25.

Change-Id: Ibc1eadcf7d942c9723bfe41d711a78371dfed99f
Signed-off-by: Christophe K

fix(stm32mp2-fdts): set SDMMC max frequency to 166 MHz on stm32mp25

Set SDMMC max frequency to 166 MHz on stm32mp25.

Change-Id: Ibc1eadcf7d942c9723bfe41d711a78371dfed99f
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>

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fix(stm32mp25-fdts): new swizzle configuration for STM32MP257F-EV1 board

Correction of the bank group management for x8 devices to remove
impacts on other cases.

While at it correct comment about d

fix(stm32mp25-fdts): new swizzle configuration for STM32MP257F-EV1 board

Correction of the bank group management for x8 devices to remove
impacts on other cases.

While at it correct comment about density only per device .

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: Iec46a35bd5e83f8de88a13fce29357b2b10c2a77

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feat(rdaspen): support configurable CPU topology in device tree

Adjust the platform's CPU topology in the device tree file based on
the passed build time topology. If no build time topology was
prov

feat(rdaspen): support configurable CPU topology in device tree

Adjust the platform's CPU topology in the device tree file based on
the passed build time topology. If no build time topology was
provided, default topology will be used.

Change-Id: Ied48f27f32d8f7a7df138a98075848c59f7435c0
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>

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fix(rdaspen): fix timer bus cells & fix ranges

The timer node is a child bus that should expose frames via a
translating address space per the timer-with-frames binding.
The #size-cells were updated

fix(rdaspen): fix timer bus cells & fix ranges

The timer node is a child bus that should expose frames via a
translating address space per the timer-with-frames binding.
The #size-cells were updated to <1> from <2>, due to a
validation warning when running dt_validate:

/home/root/fdt/fdt: timer@1a810000: #size-cells: 1 was expected

Updating the cell-size to 1 fixes it, and another fix is also
applied to avoid an empty range property.

This models the timer as a proper translating bus:
- Remove clock-frequency since it is already configured in firmware.
- Update #address-cells from <2> to <1>/
- Update #size-cells from <2> to <1>.
- Provide a non-empty ranges mapping the child space at
0x1a810000 over a 0x30000 window.
- Convert frame and reg values to offsets within the child space.

This removes the dtc warnings in dt_validate and aligns with the
dt-schema expectation for the timer-with-frames layout used by
ACS DT validation.

Change-Id: I6deb9ecc0946176b9f9992d80c95db4106eb5820
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(rdaspen): add DSU to the device tree

Update the device tree file to include the AP's DSU clusters'
L3 cache and PMU info.

Change-Id: I0923b1aed1c92f8460370de197a6197de183d7f5
Signed-off-by: Am

feat(rdaspen): add DSU to the device tree

Update the device tree file to include the AP's DSU clusters'
L3 cache and PMU info.

Change-Id: I0923b1aed1c92f8460370de197a6197de183d7f5
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(rdaspen): introduce Arm RD-Aspen platform

Create a new platform for the RD-Aspen automotive FVP.
Add the required source, header files and makefile,and
device tree

This platform contains:
* C

feat(rdaspen): introduce Arm RD-Aspen platform

Create a new platform for the RD-Aspen automotive FVP.
Add the required source, header files and makefile,and
device tree

This platform contains:
* Cortex-A720AE, Armv9.2-A application processor
* A GICv4-compatible GIC-720AE
* 128 MB of SRAM, of which 512 KB is reserved for TF-A
* 4GiB of DRAM in two partitions (extensible)

It also adds:
* FW_CONFIG and HW_CONFIG device trees

Change-Id: I4ba3e4bf1fed8f3640f7eda815607b0a5cab9500
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>

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refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dts

refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dtsi files.
This patch combines the two base TC dtsi files,
and removes tautological ifdefs in TC platform code.

Change-Id: I011b5fe1f645d6d53276007b11a17bd6cf952ecb
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/docu

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/documentation/107771/0102/
C1-Ultra TRM: https://developer.arm.com/documentation/108014/0100/
C1-Premium TRM: https://developer.arm.com/documentation/109416/0100/
C1-Nano TRM: https://developer.arm.com/documentation/107753/0001/

[1]:
https://www.arm.com/product-filter?families=c1%20cpus
https://www.arm.com/products/mobile/compute-subsystems/lumex

Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id4b487ef6a6fd1b00b75b09c5d06d81bce50a15d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(fvp): pass an `interrupt-names` property for the timer when using GICv5

The DT bindings expect the architectural timer's interrupts in the
following order:
interrupts:
minItems: 1
items:

fix(fvp): pass an `interrupt-names` property for the timer when using GICv5

The DT bindings expect the architectural timer's interrupts in the
following order:
interrupts:
minItems: 1
items:
- description: secure timer irq
- description: non-secure timer irq
- description: virtual timer irq
- description: hypervisor timer irq
- description: hypervisor virtual timer irq

However, in GICv5 the NS frame does not have access to a secure timer
and one is not passed. Override the interrupt names Instead of passing a
dummy value.

Change-Id: Ib33dd44ee17bfc63b4e21a44205c81ad4c81bfda
Reported-by: Andrew Turner <andrew.turner4@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sasc

feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Co-developed-by: Lorenzo Pieralisi <lorenzo.pieralisi2@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(fvp): factor out interrupt information from the dts

The FVP_Base models are all identical. Individual components can be
swapped out without affecting the rest of the system. In order to not

refactor(fvp): factor out interrupt information from the dts

The FVP_Base models are all identical. Individual components can be
swapped out without affecting the rest of the system. In order to not
diverge too much, factor as much common stuff out but leave out
interrupt information so that it can be swapped out.

Change-Id: I4ce5b627c7ca00d98f10eba888cc1bf4d61880a9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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chore(fvp): remove fvp-base-gicv3-psci-dynamiq-common.dtsi

It is never referenced and therefore redundant.

Change-Id: I25226bb5c78f8191aaf206c57ecbc003b7eb751a
Signed-off-by: Boyan Karatotev <boyan

chore(fvp): remove fvp-base-gicv3-psci-dynamiq-common.dtsi

It is never referenced and therefore redundant.

Change-Id: I25226bb5c78f8191aaf206c57ecbc003b7eb751a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topics "refactor_stmm", "stmm_crb_area", "stmm_with_xferlist" into integration

* changes:
feat(fvp): organize fvp_stmm_manifest.dts
feat(juno): add pseudo CRB area
feat(fvp)

Merge changes from topics "refactor_stmm", "stmm_crb_area", "stmm_with_xferlist" into integration

* changes:
feat(fvp): organize fvp_stmm_manifest.dts
feat(juno): add pseudo CRB area
feat(fvp): add pseudo CRB area
feat(arm): add pseudo CRB area
feat(juno): increase xtable for pseudo CRB
feat(fvp): increase xtable for pseudo CRB for SPMC_AT_EL3
feat(el3-spmc): deliver TPM event log via hob list
feat(el3-spmc): get sp_manifest via xferlist
feat(fvp): tos_fw_config with transfer list
feat(arm): load tos_fw_cfg using xferlist in SPMC_AT_EL3
feat(fvp): increase secure partition's table mapping count
feat(fvp): increase bl2 mmap tables for handoff

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Merge changes Ib220a866,I38e6af65,I1554efdb,Iae99985e,I96f96267, ... into integration

* changes:
feat(stm32mp25-fdts): enable rng nodes for ST boards
feat(stm32mp2): prepare DDR secure area encr

Merge changes Ib220a866,I38e6af65,I1554efdb,Iae99985e,I96f96267, ... into integration

* changes:
feat(stm32mp25-fdts): enable rng nodes for ST boards
feat(stm32mp2): prepare DDR secure area encryption
feat(stm32mp2): add some platform helpers
feat(st-drivers): add RISAF driver
feat(fdts): add RISAF nodes for STM32MP25
feat(stm32mp2-fdts): add memory firewall node
feat(stm32mp2-fdts): add firewall nodes in fw-config
feat(stm32mp2): add RIF dt-binding defines
feat(stm32mp1-fdts): add MCE support for STM32MP13 DK board
feat(stm32mp1): prepare DDR secure area encryption for STM32MP13
feat(stm32mp1): enable MCE driver for STM32MP13
feat(st-drivers): add Memory Cipher Engine driver
feat(dt-bindings): add MCE DT bindings for STM32MP13
fix(st-crypto): improve RNG health test configuration
feat(st): add RNG minor version
feat(st-crypto): add multi instance and error management in RNG driver
feat(stm32mp2): add HASH and RNG compilation
feat(stm32mp25-fdts): add RNG node

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feat(fvp): organize fvp_stmm_manifest.dts

To generalize manifest file for StandaloneMm for FVP,
organize this manifest file by separating:

* stmm_common.dtsi
- collection of macros to used by

feat(fvp): organize fvp_stmm_manifest.dts

To generalize manifest file for StandaloneMm for FVP,
organize this manifest file by separating:

* stmm_common.dtsi
- collection of macros to used by {plat_}stmm_*.dts(i) files.

* stmm_dev_region.dtsi
- device region template for StandaloneMm.
- If some environment don't required it, it can be excluded in
by not defining STMM_XXX macro.

* stmm_mem_region.dtsi
- memory region template for StandaloneMm.

* stmm_template.dts
- StandaloneMm manifest template defining common root node
information.

* fvp_stmm_{xxx}_manifest.dts
- Main StandaloneMm manifest file.
- According to environment, defines proper STMM_XXX value
to define device/memory region.
- device region can be excluded by not defining some STMM_XXX macro.

This is useful to define new StandaloneMm manifest
in different environments.

Change-Id: Ia9668c4994f589b178872d4d7a18a9f28075df74
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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fix(fdts): remove extra members in PCI interrupt-map

The FVP PCI interrupt-map DT entries are wrong and has extra members.
This patch removes the same.

Change-Id: I892cb2e2b8c6a57aec3007518d4f65014

fix(fdts): remove extra members in PCI interrupt-map

The FVP PCI interrupt-map DT entries are wrong and has extra members.
This patch removes the same.

Change-Id: I892cb2e2b8c6a57aec3007518d4f650146934283
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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feat(stm32mp25-fdts): enable rng nodes for ST boards

Enable RNG peripheral in device trees for ST boards STM32MP257F-DK and
STM32MP257F-EV1.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed

feat(stm32mp25-fdts): enable rng nodes for ST boards

Enable RNG peripheral in device trees for ST boards STM32MP257F-DK and
STM32MP257F-EV1.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Ib220a866e75d3383f43596c7bcfdcad590c541a4

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feat(fdts): add RISAF nodes for STM32MP25

Add RISAF2 and RISAF4 nodes in STM32MP25 SoC DT file.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.ba

feat(fdts): add RISAF nodes for STM32MP25

Add RISAF2 and RISAF4 nodes in STM32MP25 SoC DT file.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I96f96267292e7f7a498a87c60e35310e25b41d6d

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feat(stm32mp2-fdts): add memory firewall node

add RIF memory firewall node for STM32MP257F-DK board.

Change-Id: I1b6b094a3f6209f996a2ff5d590f081a68d9c7a9
Signed-off-by: Maxime Méré <maxime.mere@fos

feat(stm32mp2-fdts): add memory firewall node

add RIF memory firewall node for STM32MP257F-DK board.

Change-Id: I1b6b094a3f6209f996a2ff5d590f081a68d9c7a9
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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