1 /* 2 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef AGILEX5_IOSSM_MAILBOX_H 8 #define AGILEX5_IOSSM_MAILBOX_H 9 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <stdlib.h> 13 14 #include "lib/mmio.h" 15 #include "agilex5_ddr.h" 16 17 #define __bf_shf(x) (__builtin_ffsll(x) - 1U) 18 #define FIELD_GET(_mask, _reg) \ 19 ({ \ 20 (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ 21 }) 22 23 #define FIELD_PREP(_mask, _val) \ 24 ({ \ 25 ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ 26 }) 27 28 #define IOSSM_TIMEOUT_MS 120000U 29 #define TIMEOUT_5000MS 5000 30 #define TIMEOUT TIMEOUT_5000MS 31 #define IOSSM_STATUS_CAL_SUCCESS BIT(0) 32 #define IOSSM_STATUS_CAL_FAIL BIT(1) 33 #define IOSSM_STATUS_CAL_BUSY BIT(2) 34 #define IOSSM_STATUS_COMMAND_RESPONSE_READY 1 35 #define IOSSM_CMD_RESPONSE_STATUS_OFFSET 0x45C 36 #define IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x458 37 #define IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x454 38 #define IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x450 39 #define IOSSM_CMD_REQ_OFFSET 0x43C 40 #define IOSSM_CMD_PARAM_0_OFFSET 0x438 41 #define IOSSM_CMD_PARAM_1_OFFSET 0x434 42 #define IOSSM_CMD_PARAM_2_OFFSET 0x430 43 #define IOSSM_CMD_PARAM_3_OFFSET 0x42C 44 #define IOSSM_CMD_PARAM_4_OFFSET 0x428 45 #define IOSSM_CMD_PARAM_5_OFFSET 0x424 46 #define IOSSM_CMD_PARAM_6_OFFSET 0x420 47 #define IOSSM_STATUS_OFFSET 0x400 48 #define IOSSM_CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16) 49 #define IOSSM_CMD_RESPONSE_DATA_SHORT(data) (((data) & \ 50 IOSSM_CMD_RESPONSE_DATA_SHORT_MASK) >> 16) 51 #define MAX_IO96B_SUPPORTED 2 52 #define MAX_MEM_INTERFACES_SUPPORTED 2 53 #define SZ_8 0x00000008 54 #define GET_INLINE_ECC_HW_DDR_SIZE(size) (((size) * 7) / 8) 55 56 /* ECC error status related register offsets/commands. */ 57 #define IOSSM_ECC_ERR_STATUS_OFFSET 0x300 58 #define IOSSM_ECC_ERR_DATA_START_OFFSET 0x310 59 #define IOSSM_ECC_CLEAR_ERR_BUFFER 0x0110 60 61 /* Offset info of ECC_ERR_STATUS */ 62 #define ECC_ERR_COUNTER_MASK GENMASK(15, 0) 63 #define ECC_ERR_OVERFLOW_MASK GENMASK(31, 16) 64 65 /* Offset info of ECC_ERR_DATA */ 66 #define ECC_ERR_IP_TYPE_MASK GENMASK(24, 22) 67 #define ECC_ERR_INSTANCE_ID_MASK GENMASK(21, 17) 68 #define ECC_ERR_SOURCE_ID_MASK GENMASK(16, 10) 69 #define ECC_ERR_TYPE_MASK GENMASK(9, 6) 70 #define ECC_ERR_ADDR_UPPER_MASK GENMASK(5, 0) 71 #define ECC_ERR_ADDR_LOWER_MASK GENMASK(31, 0) 72 73 #define MAX_ECC_ERR_COUNT 16U 74 75 #define BIST_START_ADDR_SPACE_MASK GENMASK(5, 0) 76 #define BIST_START_ADDR_LOW_MASK GENMASK(31, 0) 77 #define BIST_START_ADDR_HIGH_MASK GENMASK(37, 32) 78 79 /* supported mailbox command type */ 80 enum iossm_mailbox_cmd_type { 81 CMD_NOP, 82 CMD_GET_SYS_INFO, 83 CMD_GET_MEM_INFO, 84 CMD_GET_MEM_CAL_INFO, 85 CMD_TRIG_CONTROLLER_OP, 86 CMD_TRIG_MEM_CAL_OP 87 }; 88 89 /* ECC error types */ 90 enum ecc_error_type { 91 SINGLE_BIT_ERROR = 0, /* 0b0000 */ 92 MULTIPLE_SINGLE_BIT_ERRORS = 1, /* 0b0001 */ 93 DOUBLE_BIT_ERROR = 2, /* 0b0010 */ 94 MULTIPLE_DOUBLE_BIT_ERRORS = 3, /* 0b0011 */ 95 SINGLE_BIT_ERROR_SCRUBBING = 8, /* 0b1000 */ 96 WRITE_LINK_SINGLE_BIT_ERROR = 9, /* 0b1001 */ 97 WRITE_LINK_DOUBLE_BIT_ERROR = 10, /* 0b1010 */ 98 READ_LINK_SINGLE_BIT_ERROR = 11, /* 0b1011 */ 99 READ_LINK_DOUBLE_BIT_ERROR = 12, /* 0b1100 */ 100 READ_MODIFY_WRITE_DOUBLE_BIT_ERROR = 13 /* 0b1101 */ 101 }; 102 103 /* supported mailbox command opcode */ 104 enum iossm_mailbox_cmd_opcode { 105 GET_MEM_INTF_INFO = 0x0001, 106 GET_MEM_TECHNOLOGY, 107 GET_MEMCLK_FREQ_KHZ, 108 GET_MEM_WIDTH_INFO, 109 ECC_ENABLE_SET = 0x0101, 110 ECC_ENABLE_STATUS, 111 ECC_INTERRUPT_STATUS, 112 ECC_INTERRUPT_ACK, 113 ECC_INTERRUPT_MASK, 114 ECC_WRITEBACK_ENABLE, 115 ECC_SCRUB_IN_PROGRESS_STATUS = 0x0201, 116 ECC_SCRUB_MODE_0_START, 117 ECC_SCRUB_MODE_1_START, 118 BIST_STANDARD_MODE_START = 0x0301, 119 BIST_RESULTS_STATUS, 120 BIST_MEM_INIT_START, 121 BIST_MEM_INIT_STATUS, 122 BIST_SET_DATA_PATTERN_UPPER, 123 BIST_SET_DATA_PATTERN_LOWER, 124 TRIG_MEM_CAL = 0x000a, 125 GET_MEM_CAL_STATUS 126 }; 127 128 /* 129 * IOSSM mailbox required information 130 * 131 * @num_mem_interface: Number of memory interfaces instantiated 132 * @ip_type: IP type implemented on the IO96B 133 * @ip_instance_id: IP identifier for every IP instance implemented on the IO96B 134 * @memory_size[2]: Memory size for every IP instance implemented on the IO96B 135 */ 136 struct io96b_mb_ctrl { 137 uint32_t num_mem_interface; 138 uint32_t ip_type[2]; 139 uint32_t ip_instance_id[2]; 140 phys_size_t memory_size[2]; 141 }; 142 143 /* 144 * IOSSM mailbox response outputs 145 * 146 * @cmd_resp_status: Command Interface status 147 * @cmd_resp_data_*: More spaces for command response 148 */ 149 struct io96b_mb_resp { 150 uint32_t cmd_resp_status; 151 uint32_t cmd_resp_data_0; 152 uint32_t cmd_resp_data_1; 153 uint32_t cmd_resp_data_2; 154 }; 155 156 /* 157 * IO96B instance specific information 158 * 159 * @io96b_csr_addr: IO96B instance CSR address 160 * @cal_status: IO96B instance calibration status 161 * @mb_ctrl: IOSSM mailbox required information 162 */ 163 struct io96b_instance { 164 phys_addr_t io96b_csr_addr; 165 bool cal_status; 166 struct io96b_mb_ctrl mb_ctrl; 167 }; 168 169 /* 170 * Overall IO96B instance(s) information 171 * 172 * @num_instance: Number of instance(s) assigned to HPS 173 * @overall_cal_status: Overall calibration status for all IO96B instance(s) 174 * @ddr_type: DDR memory type 175 * @ecc_status: ECC enable status (false = disabled, true = enabled) 176 * @overall_size: Total DDR memory size 177 * @io96b_0: IO96B 0 instance specific information 178 * @io96b_1: IO96B 1 instance specific information 179 */ 180 struct io96b_info { 181 uint8_t num_instance; 182 bool overall_cal_status; 183 const char *ddr_type; 184 bool ecc_status; 185 bool is_inline_ecc; 186 phys_size_t overall_size; 187 struct io96b_instance io96b_0; 188 struct io96b_instance io96b_1; 189 }; 190 191 int io96b_mb_req(phys_addr_t io96b_csr_addr, uint32_t ip_type, uint32_t instance_id, 192 uint32_t usr_cmd_type, uint32_t usr_cmd_opcode, uint32_t cmd_param_0, 193 uint32_t cmd_param_1, uint32_t cmd_param_2, uint32_t cmd_param_3, 194 uint32_t cmd_param_4, uint32_t cmd_param_5, uint32_t cmd_param_6, 195 uint32_t resp_data_len, struct io96b_mb_resp *resp); 196 197 /* Supported IOSSM mailbox function */ 198 void io96b_mb_init(struct io96b_info *io96b_ctrl); 199 int io96b_cal_status(phys_addr_t addr); 200 void init_mem_cal(struct io96b_info *io96b_ctrl); 201 int trig_mem_cal(struct io96b_info *io96b_ctrl); 202 int get_mem_technology(struct io96b_info *io96b_ctrl); 203 int get_mem_width_info(struct io96b_info *io96b_ctrl); 204 int ecc_enable_status(struct io96b_info *io96b_ctrl); 205 int bist_mem_init_start(struct io96b_info *io96b_ctrl); 206 bool get_ecc_dbe_status(struct io96b_info *io96b_ctrl); 207 208 #endif /* AGILEX5_IOSSM_MAILBOX_H */ 209