1 /* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef NEOVERSE_V2_H 8 #define NEOVERSE_V2_H 9 10 #define NEOVERSE_V2_MIDR U(0x410FD4F0) 11 12 /* Neoverse V2 loop count for CVE-2022-23960 mitigation */ 13 #define NEOVERSE_V2_BHB_LOOP_COUNT U(132) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions 17 ******************************************************************************/ 18 #define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4 19 #define NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 20 21 /******************************************************************************* 22 * CPU Power Control register specific definitions 23 ******************************************************************************/ 24 #define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 25 #define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 26 #define NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT U(4) 27 #define NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH U(3) 28 #define NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT U(7) 29 #define NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH U(3) 30 31 /******************************************************************************* 32 * CPU Extended Control register 2 specific definitions. 33 ******************************************************************************/ 34 #define NEOVERSE_V2_CPUECTLR2_EL1 S3_0_C15_C1_5 35 #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0) 36 #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB U(0) 37 #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH U(3) 38 39 /******************************************************************************* 40 * CPU Auxiliary Control register specific definitions. 41 ******************************************************************************/ 42 #define NEOVERSE_V2_CPUACTLR_EL1 S3_0_C15_C1_0 43 44 /******************************************************************************* 45 * CPU Auxiliary Control register 2 specific definitions. 46 ******************************************************************************/ 47 #define NEOVERSE_V2_CPUACTLR2_EL1 S3_0_C15_C1_1 48 #define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 49 50 /******************************************************************************* 51 * CPU Auxiliary Control register 3 specific definitions. 52 ******************************************************************************/ 53 #define NEOVERSE_V2_CPUACTLR3_EL1 S3_0_C15_C1_2 54 #define NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) 55 56 /******************************************************************************* 57 * CPU Auxiliary Control register 5 specific definitions. 58 ******************************************************************************/ 59 #define NEOVERSE_V2_CPUACTLR5_EL1 S3_0_C15_C8_0 60 #define NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) 61 #define NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) 62 63 /******************************************************************************* 64 * CPU Auxiliary control register 6 specific definitions 65 ******************************************************************************/ 66 #define NEOVERSE_V2_CPUACTLR6_EL1 S3_0_C15_C8_1 67 68 #ifndef __ASSEMBLER__ 69 long check_erratum_neoverse_v2_3701771(long cpu_rev); 70 #endif /* __ASSEMBLER__ */ 71 72 #endif /* NEOVERSE_V2_H */ 73