1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_HWREQ_H 8 #define MT_SPM_HWREQ_H 9 10 #include <drivers/spm/mt_spm_resource_req.h> 11 #include <mt_spm_common_v1.h> 12 13 /* ddren, apsrc and emi resource have become hw resource_req. 14 * So we don't need to use HW CG for request resource. 15 */ 16 #define SPM_HWCG_DDREN_PWR_MB (0) 17 #define SPM_HWCG_DDREN_PWR_MSB_MB (0) 18 #define SPM_HWCG_DDREN_MODULE_BUSY_MB (0) 19 20 /* VRF18 */ 21 #define SPM_HWCG_VRF18_PWR_MB \ 22 (BIT(HWCG_PWR_ISP_IMG1) | BIT(HWCG_PWR_ISP_IMG2) | \ 23 BIT(HWCG_PWR_ISP_IPE) | BIT(HWCG_PWR_VDE0) | BIT(HWCG_PWR_VEN0) | \ 24 BIT(HWCG_PWR_CAM_MAIN) | BIT(HWCG_PWR_CAM_SUBA) | \ 25 BIT(HWCG_PWR_CAM_SUBB) | BIT(HWCG_PWR_CAM_VCORE) | \ 26 BIT(HWCG_PWR_MDP0) | BIT(HWCG_PWR_MM_INFRA)) 27 28 #define SPM_HWCG_VRF18_PWR_MSB_MB \ 29 (BIT(HWCG_PWR_DP_TX) | BIT(HWCG_PWR_EMI0) | BIT(HWCG_PWR_CSI_RX) | \ 30 BIT(HWCG_PWR_SSRSYS) | BIT(HWCG_PWR_SSPM) | BIT(HWCG_PWR_EDP_TX) | \ 31 BIT(HWCG_PWR_PCIE) | BIT(HWCG_PWR_PCIE_PHY)) 32 33 #define SPM_HWCG_VRF18_MODULE_BUSY_MB (0) 34 35 /* INFRA */ 36 #define SPM_HWCG_INFRA_PWR_MB (SPM_HWCG_VRF18_PWR_MB) 37 #define SPM_HWCG_INFRA_PWR_MSB_MB (SPM_HWCG_VRF18_PWR_MSB_MB) 38 #define SPM_HWCG_INFRA_MODULE_BUSY_MB (0) 39 40 /* PMIC */ 41 #define SPM_HWCG_PMIC_PWR_MB (SPM_HWCG_INFRA_PWR_MB) 42 43 #define SPM_HWCG_PMIC_PWR_MSB_MB (SPM_HWCG_INFRA_PWR_MSB_MB) 44 #define SPM_HWCG_PMIC_MODULE_BUSY_MB (0) 45 46 /* F26M */ 47 #define SPM_HWCG_F26M_PWR_MB \ 48 ((SPM_HWCG_PMIC_PWR_MB) | BIT(HWCG_PWR_AUDIO)) 49 50 #define SPM_HWCG_F26M_PWR_MSB_MB (SPM_HWCG_PMIC_PWR_MSB_MB) 51 52 #define SPM_HWCG_F26M_MODULE_BUSY_MB \ 53 (BIT(HWCG_MODULE_MMPLL) | BIT(HWCG_MODULE_UFSPLL) | \ 54 BIT(HWCG_MODULE_MSDCPLL) | BIT(HWCG_MODULE_UNIVPLL)) 55 56 /* VCORE */ 57 #define SPM_HWCG_VCORE_PWR_MB \ 58 ((SPM_HWCG_F26M_PWR_MB) | BIT(HWCG_PWR_UFS0)) 59 60 #define SPM_HWCG_VCORE_PWR_MSB_MB (SPM_HWCG_F26M_PWR_MSB_MB) 61 #define SPM_HWCG_VCORE_MODULE_BUSY_MB (SPM_HWCG_F26M_MODULE_BUSY_MB) 62 63 #define INFRA_SW_CG_MB (0) 64 65 #define PERI_REQ_EN_MASK 0x3FFFF 66 67 /* Resource requirement which HW CG support */ 68 enum { 69 HWCG_DDREN = 0, 70 HWCG_VRF18, 71 HWCG_INFRA, 72 HWCG_F26M, 73 HWCG_PMIC, 74 HWCG_VCORE, 75 HWCG_MAX 76 }; 77 78 enum spm_pwr_status { 79 HWCG_PWR_MD1 = 0, 80 HWCG_PWR_CONN, 81 HWCG_PWR_IFR, 82 HWCG_PWR_PERI, 83 HWCG_PWR_UFS0, 84 HWCG_PWR_UFS0_PHY, 85 HWCG_PWR_AUDIO, 86 HWCG_PWR_ADSP_TOP, 87 HWCG_PWR_ADSP_INFRA = 8, 88 HWCG_PWR_ADSP_AO, 89 HWCG_PWR_ISP_IMG1, 90 HWCG_PWR_ISP_IMG2, 91 HWCG_PWR_ISP_IPE, 92 HWCG_PWR_ISP_VCORE, 93 HWCG_PWR_VDE0, 94 HWCG_PWR_VDE1, 95 HWCG_PWR_VEN0 = 16, 96 HWCG_PWR_VEN1, 97 HWCG_PWR_CAM_MAIN, 98 HWCG_PWR_CAM_MRAW, 99 HWCG_PWR_CAM_SUBA, 100 HWCG_PWR_CAM_SUBB, 101 HWCG_PWR_CAM_SUBC, 102 HWCG_PWR_CAM_VCORE, 103 HWCG_PWR_CAM_CCU = 24, 104 HWCG_PWR_CAM_CCU_AO, 105 HWCG_PWR_MDP0, 106 HWCG_PWR_MDP1, 107 HWCG_PWR_DIS0, 108 HWCG_PWR_DIS1, 109 HWCG_PWR_MM_INFRA, 110 HWCG_PWR_MM_PROC, 111 HWCG_PWR_MAX 112 }; 113 114 enum spm_pwr_msb_status { 115 HWCG_PWR_DP_TX = 0, 116 HWCG_PWR_SCP_CORE, 117 HWCG_PWR_SCP_PERI, 118 HWCG_PWR_DPM0, 119 HWCG_PWR_DPM1, 120 HWCG_PWR_EMI0, 121 HWCG_PWR_EMI1, 122 HWCG_PWR_CSI_RX, 123 HWCG_PWR_SSRSYS = 8, 124 HWCG_PWR_SSPM, 125 HWCG_PWR_SSUSB, 126 HWCG_PWR_SSUSB_PHY, 127 HWCG_PWR_EDP_TX, 128 HWCG_PWR_PCIE, 129 HWCG_PWR_PCIE_PHY, 130 HWCG_PWR_MSB_EMPTY_BIT15, 131 HWCG_PWR_MSB_EMPTY_BIT16 = 16, 132 HWCG_PWR_MSB_EMPTY_BIT17, 133 HWCG_PWR_MSB_EMPTY_BIT18, 134 HWCG_PWR_MSB_EMPTY_BIT19, 135 HWCG_PWR_MSB_EMPTY_BIT20, 136 HWCG_PWR_MSB_EMPTY_BIT21, 137 HWCG_PWR_MSB_EMPTY_BIT22, 138 HWCG_PWR_MSB_EMPTY_BIT23, 139 HWCG_PWR_MSB_EMPTY_BIT24 = 24, 140 HWCG_PWR_MSB_EMPTY_BIT25, 141 HWCG_PWR_MSB_EMPTY_BIT26, 142 HWCG_PWR_MSB_EMPTY_BIT27, 143 HWCG_PWR_MSB_EMPTY_BIT28, 144 HWCG_PWR_MSB_EMPTY_BIT29, 145 HWCG_PWR_MSB_EMPTY_BIT30, 146 HWCG_PWR_MSB_EMPTY_BIT31, 147 HWCG_PWR_MSB_MAX 148 }; 149 150 enum spm_hwcg_module_busy { 151 HWCG_MODULE_AUDIO = 0, 152 HWCG_MODULE_MMPLL, 153 HWCG_MODULE_UFSPLL, 154 HWCG_MODULE_MSDCPLL, 155 HWCG_MODULE_UNIVPLL, 156 HWCG_MODULE_MAX 157 }; 158 159 /* Resource requirement which PERI REQ support */ 160 enum spm_peri_req { 161 PERI_REQ_F26M = 0, 162 PERI_REQ_INFRA, 163 PERI_REQ_SYSPLL, 164 PERI_REQ_APSRC, 165 PERI_REQ_DDREN, 166 PERI_REQ_EMI, 167 PERI_REQ_PMIC, 168 PERI_REQ_MAX 169 }; 170 171 enum spm_peri_req_en { 172 PERI_REQ_EN_DMA = 1, 173 PERI_REQ_EN_UART0, 174 PERI_REQ_EN_UART1, 175 PERI_REQ_EN_UART2, 176 PERI_REQ_EN_UART3, 177 PERI_REQ_EN_PWM = 6, 178 PERI_REQ_EN_SPI0, 179 PERI_REQ_EN_SPI1, 180 PERI_REQ_EN_SPI2, 181 PERI_REQ_EN_SPI3 = 10, 182 PERI_REQ_EN_SPI4, 183 PERI_REQ_EN_SPI5, 184 PERI_REQ_EN_I2C, 185 PERI_REQ_EN_MSDC0, 186 PERI_REQ_EN_MSDC1 = 15, 187 PERI_REQ_EN_MSDC2, 188 PERI_REQ_EN_SSUSB0 = 17, 189 PERI_REQ_EN_SSUSB1, 190 PERI_REQ_EN_SSUSB2, 191 PERI_REQ_EN_SSUSB3, 192 PERI_REQ_EN_SSUSB4, 193 PERI_REQ_EN_PEXTP, 194 PERI_REQ_EN_AFE = 23, 195 PERI_REQ_EN_MAX 196 }; 197 198 #define INFRA_AO_OFFSET(offset) (INFRACFG_AO_BASE + offset) 199 #define INFRA_SW_CG_0_MASK INFRA_AO_OFFSET(0x060) 200 #define INFRA_SW_CG_1_MASK INFRA_AO_OFFSET(0x064) 201 #define INFRA_SW_CG_2_MASK INFRA_AO_OFFSET(0x068) 202 #define INFRA_SW_CG_3_MASK INFRA_AO_OFFSET(0x0CC) 203 #define INFRA_SW_CG_4_MASK INFRA_AO_OFFSET(0x0EC) 204 205 #define REG_PERI_REQ_EN(N) (PERICFG_AO_BASE + 0x050 + 0x4 * N) 206 #define REG_PERI_REQ_STA(N) (PERICFG_AO_BASE + 0x06C + 0x4 * N) 207 208 static inline uint32_t spm_hwcg_num(void) 209 { 210 return HWCG_MAX; 211 } 212 213 static inline uint32_t spm_peri_req_num(void) 214 { 215 return PERI_REQ_MAX; 216 } 217 218 #endif 219