1/* 2 * Copyright (c) 2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 model = "RD-Aspen"; 13 compatible = "arm,rdaspen"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { 19 stdout-path = &soc_serial0; 20 }; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 /* 4 clusters and 4 CPU cores in each cluster */ 27 cpu-map { 28 cluster0 { 29 core0 { 30 cpu = <&CPU0>; 31 }; 32 core1 { 33 cpu = <&CPU1>; 34 }; 35 core2 { 36 cpu = <&CPU2>; 37 }; 38 core3 { 39 cpu = <&CPU3>; 40 }; 41 CL0_L3: l3-cache0 { 42 compatible = "arm,dsu-l3-cache", "cache"; 43 cache-level = <0x03>; 44 /* 4MB */ 45 cache-size = <0x400000>; 46 /* 64B */ 47 cache-line-size = <0x40>; 48 /* 16-way set */ 49 cache-sets = <0x1000>; 50 }; 51 }; 52 cluster1 { 53 core0 { 54 cpu = <&CPU4>; 55 }; 56 core1 { 57 cpu = <&CPU5>; 58 }; 59 core2 { 60 cpu = <&CPU6>; 61 }; 62 core3 { 63 cpu = <&CPU7>; 64 }; 65 CL1_L3: l3-cache1 { 66 compatible = "arm,dsu-l3-cache", "cache"; 67 cache-level = <0x03>; 68 /* 4MB */ 69 cache-size = <0x400000>; 70 /* 64B */ 71 cache-line-size = <0x40>; 72 /* 16-way set */ 73 cache-sets = <0x1000>; 74 }; 75 }; 76 cluster2 { 77 core0 { 78 cpu = <&CPU8>; 79 }; 80 core1 { 81 cpu = <&CPU9>; 82 }; 83 core2 { 84 cpu = <&CPU10>; 85 }; 86 core3 { 87 cpu = <&CPU11>; 88 }; 89 CL2_L3: l3-cache2 { 90 compatible = "arm,dsu-l3-cache", "cache"; 91 cache-level = <0x03>; 92 /* 4MB */ 93 cache-size = <0x400000>; 94 /* 64B */ 95 cache-line-size = <0x40>; 96 /* 16-way set */ 97 cache-sets = <0x1000>; 98 }; 99 }; 100 cluster3 { 101 core0 { 102 cpu = <&CPU12>; 103 }; 104 core1 { 105 cpu = <&CPU13>; 106 }; 107 core2 { 108 cpu = <&CPU14>; 109 }; 110 core3 { 111 cpu = <&CPU15>; 112 }; 113 CL3_L3: l3-cache3 { 114 compatible = "arm,dsu-l3-cache", "cache"; 115 cache-level = <0x03>; 116 /* 4MB */ 117 cache-size = <0x400000>; 118 /* 64B */ 119 cache-line-size = <0x40>; 120 /* 16-way set */ 121 cache-sets = <0x1000>; 122 }; 123 }; 124 }; 125 126 CPU0: cpu@0 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a720ae"; 129 reg = <0x0 0x0>; 130 enable-method = "psci"; 131 i-cache-size = <0x10000>; 132 i-cache-line-size = <0x40>; 133 i-cache-sets = <0x100>; 134 d-cache-size = <0x10000>; 135 d-cache-line-size = <0x40>; 136 d-cache-sets = <0x100>; 137 next-level-cache = <&CL0_L2_0>; 138 CL0_L2_0: l2-cache0 { 139 compatible = "cache"; 140 cache-level = <0x02>; 141 /* 512KB */ 142 cache-size = <0x80000>; 143 /* 64B */ 144 cache-line-size = <0x40>; 145 /* 8-way set */ 146 cache-sets = <0x400>; 147 next-level-cache = <&CL0_L3>; 148 }; 149 }; 150 151 CPU1: cpu@100 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a720ae"; 154 reg = <0x0 0x100>; 155 enable-method = "psci"; 156 i-cache-size = <0x10000>; 157 i-cache-line-size = <0x40>; 158 i-cache-sets = <0x100>; 159 d-cache-size = <0x10000>; 160 d-cache-line-size = <0x40>; 161 d-cache-sets = <0x100>; 162 next-level-cache = <&CL0_L2_1>; 163 CL0_L2_1: l2-cache1 { 164 compatible = "cache"; 165 cache-level = <0x02>; 166 /* 512KB */ 167 cache-size = <0x80000>; 168 /* 64B */ 169 cache-line-size = <0x40>; 170 /* 8-way set */ 171 cache-sets = <0x400>; 172 next-level-cache = <&CL0_L3>; 173 }; 174 }; 175 176 CPU2: cpu@200 { 177 device_type = "cpu"; 178 compatible = "arm,cortex-a720ae"; 179 reg = <0x0 0x200>; 180 enable-method = "psci"; 181 i-cache-size = <0x10000>; 182 i-cache-line-size = <0x40>; 183 i-cache-sets = <0x100>; 184 d-cache-size = <0x10000>; 185 d-cache-line-size = <0x40>; 186 d-cache-sets = <0x100>; 187 next-level-cache = <&CL0_L2_2>; 188 CL0_L2_2: l2-cache2 { 189 compatible = "cache"; 190 cache-level = <0x02>; 191 /* 512KB */ 192 cache-size = <0x80000>; 193 /* 64B */ 194 cache-line-size = <0x40>; 195 /* 8-way set */ 196 cache-sets = <0x400>; 197 next-level-cache = <&CL0_L3>; 198 }; 199 }; 200 201 CPU3: cpu@300 { 202 device_type = "cpu"; 203 compatible = "arm,cortex-a720ae"; 204 reg = <0x0 0x300>; 205 enable-method = "psci"; 206 i-cache-size = <0x10000>; 207 i-cache-line-size = <0x40>; 208 i-cache-sets = <0x100>; 209 d-cache-size = <0x10000>; 210 d-cache-line-size = <0x40>; 211 d-cache-sets = <0x100>; 212 next-level-cache = <&CL0_L2_3>; 213 CL0_L2_3: l2-cache3 { 214 compatible = "cache"; 215 cache-level = <0x02>; 216 /* 512KB */ 217 cache-size = <0x80000>; 218 /* 64B */ 219 cache-line-size = <0x40>; 220 /* 8-way set */ 221 cache-sets = <0x400>; 222 next-level-cache = <&CL0_L3>; 223 }; 224 }; 225 226 CPU4: cpu@10000 { 227 device_type = "cpu"; 228 compatible = "arm,cortex-a720ae"; 229 reg = <0x0 0x10000>; 230 enable-method = "psci"; 231 i-cache-size = <0x10000>; 232 i-cache-line-size = <0x40>; 233 i-cache-sets = <0x100>; 234 d-cache-size = <0x10000>; 235 d-cache-line-size = <0x40>; 236 d-cache-sets = <0x100>; 237 next-level-cache = <&CL1_L2_0>; 238 CL1_L2_0: l2-cache4 { 239 compatible = "cache"; 240 cache-level = <0x02>; 241 /* 512KB */ 242 cache-size = <0x80000>; 243 /* 64B */ 244 cache-line-size = <0x40>; 245 /* 8-way set */ 246 cache-sets = <0x400>; 247 next-level-cache = <&CL1_L3>; 248 }; 249 }; 250 251 CPU5: cpu@10100 { 252 device_type = "cpu"; 253 compatible = "arm,cortex-a720ae"; 254 reg = <0x0 0x10100>; 255 enable-method = "psci"; 256 i-cache-size = <0x10000>; 257 i-cache-line-size = <0x40>; 258 i-cache-sets = <0x100>; 259 d-cache-size = <0x10000>; 260 d-cache-line-size = <0x40>; 261 d-cache-sets = <0x100>; 262 next-level-cache = <&CL1_L2_1>; 263 CL1_L2_1: l2-cache5 { 264 compatible = "cache"; 265 cache-level = <0x02>; 266 /* 512KB */ 267 cache-size = <0x80000>; 268 /* 64B */ 269 cache-line-size = <0x40>; 270 /* 8-way set */ 271 cache-sets = <0x400>; 272 next-level-cache = <&CL1_L3>; 273 }; 274 }; 275 276 CPU6: cpu@10200 { 277 device_type = "cpu"; 278 compatible = "arm,cortex-a720ae"; 279 reg = <0x0 0x10200>; 280 enable-method = "psci"; 281 i-cache-size = <0x10000>; 282 i-cache-line-size = <0x40>; 283 i-cache-sets = <0x100>; 284 d-cache-size = <0x10000>; 285 d-cache-line-size = <0x40>; 286 d-cache-sets = <0x100>; 287 next-level-cache = <&CL1_L2_2>; 288 CL1_L2_2: l2-cache6 { 289 compatible = "cache"; 290 cache-level = <0x02>; 291 /* 512KB */ 292 cache-size = <0x80000>; 293 /* 64B */ 294 cache-line-size = <0x40>; 295 /* 8-way set */ 296 cache-sets = <0x400>; 297 next-level-cache = <&CL1_L3>; 298 }; 299 }; 300 301 CPU7: cpu@10300 { 302 device_type = "cpu"; 303 compatible = "arm,cortex-a720ae"; 304 reg = <0x0 0x10300>; 305 enable-method = "psci"; 306 i-cache-size = <0x10000>; 307 i-cache-line-size = <0x40>; 308 i-cache-sets = <0x100>; 309 d-cache-size = <0x10000>; 310 d-cache-line-size = <0x40>; 311 d-cache-sets = <0x100>; 312 next-level-cache = <&CL1_L2_3>; 313 CL1_L2_3: l2-cache7 { 314 compatible = "cache"; 315 cache-level = <0x02>; 316 /* 512KB */ 317 cache-size = <0x80000>; 318 /* 64B */ 319 cache-line-size = <0x40>; 320 /* 8-way set */ 321 cache-sets = <0x400>; 322 next-level-cache = <&CL1_L3>; 323 }; 324 }; 325 326 CPU8: cpu@20000 { 327 device_type = "cpu"; 328 compatible = "arm,cortex-a720ae"; 329 reg = <0x0 0x20000>; 330 enable-method = "psci"; 331 i-cache-size = <0x10000>; 332 i-cache-line-size = <0x40>; 333 i-cache-sets = <0x100>; 334 d-cache-size = <0x10000>; 335 d-cache-line-size = <0x40>; 336 d-cache-sets = <0x100>; 337 next-level-cache = <&CL2_L2_0>; 338 CL2_L2_0: l2-cache8 { 339 compatible = "cache"; 340 cache-level = <0x02>; 341 /* 512KB */ 342 cache-size = <0x80000>; 343 /* 64B */ 344 cache-line-size = <0x40>; 345 /* 8-way set */ 346 cache-sets = <0x400>; 347 next-level-cache = <&CL2_L3>; 348 }; 349 }; 350 351 CPU9: cpu@20100 { 352 device_type = "cpu"; 353 compatible = "arm,cortex-a720ae"; 354 reg = <0x0 0x20100>; 355 enable-method = "psci"; 356 i-cache-size = <0x10000>; 357 i-cache-line-size = <0x40>; 358 i-cache-sets = <0x100>; 359 d-cache-size = <0x10000>; 360 d-cache-line-size = <0x40>; 361 d-cache-sets = <0x100>; 362 next-level-cache = <&CL2_L2_1>; 363 CL2_L2_1: l2-cache9 { 364 compatible = "cache"; 365 cache-level = <0x02>; 366 /* 512KB */ 367 cache-size = <0x80000>; 368 /* 64B */ 369 cache-line-size = <0x40>; 370 /* 8-way set */ 371 cache-sets = <0x400>; 372 next-level-cache = <&CL2_L3>; 373 }; 374 }; 375 376 CPU10: cpu@20200 { 377 device_type = "cpu"; 378 compatible = "arm,cortex-a720ae"; 379 reg = <0x0 0x20200>; 380 enable-method = "psci"; 381 i-cache-size = <0x10000>; 382 i-cache-line-size = <0x40>; 383 i-cache-sets = <0x100>; 384 d-cache-size = <0x10000>; 385 d-cache-line-size = <0x40>; 386 d-cache-sets = <0x100>; 387 next-level-cache = <&CL2_L2_2>; 388 CL2_L2_2: l2-cache10 { 389 compatible = "cache"; 390 cache-level = <0x02>; 391 /* 512KB */ 392 cache-size = <0x80000>; 393 /* 64B */ 394 cache-line-size = <0x40>; 395 /* 8-way set */ 396 cache-sets = <0x400>; 397 next-level-cache = <&CL2_L3>; 398 }; 399 }; 400 401 CPU11: cpu@20300 { 402 device_type = "cpu"; 403 compatible = "arm,cortex-a720ae"; 404 reg = <0x0 0x20300>; 405 enable-method = "psci"; 406 i-cache-size = <0x10000>; 407 i-cache-line-size = <0x40>; 408 i-cache-sets = <0x100>; 409 d-cache-size = <0x10000>; 410 d-cache-line-size = <0x40>; 411 d-cache-sets = <0x100>; 412 next-level-cache = <&CL2_L2_3>; 413 CL2_L2_3: l2-cache11 { 414 compatible = "cache"; 415 cache-level = <0x02>; 416 /* 512KB */ 417 cache-size = <0x80000>; 418 /* 64B */ 419 cache-line-size = <0x40>; 420 /* 8-way set */ 421 cache-sets = <0x400>; 422 next-level-cache = <&CL2_L3>; 423 }; 424 }; 425 426 CPU12: cpu@30000 { 427 device_type = "cpu"; 428 compatible = "arm,cortex-a720ae"; 429 reg = <0x0 0x30000>; 430 enable-method = "psci"; 431 i-cache-size = <0x10000>; 432 i-cache-line-size = <0x40>; 433 i-cache-sets = <0x100>; 434 d-cache-size = <0x10000>; 435 d-cache-line-size = <0x40>; 436 d-cache-sets = <0x100>; 437 next-level-cache = <&CL3_L2_0>; 438 CL3_L2_0: l2-cache12 { 439 compatible = "cache"; 440 cache-level = <0x02>; 441 /* 512KB */ 442 cache-size = <0x80000>; 443 /* 64B */ 444 cache-line-size = <0x40>; 445 /* 8-way set */ 446 cache-sets = <0x400>; 447 next-level-cache = <&CL3_L3>; 448 }; 449 }; 450 451 CPU13: cpu@30100 { 452 device_type = "cpu"; 453 compatible = "arm,cortex-a720ae"; 454 reg = <0x0 0x30100>; 455 enable-method = "psci"; 456 i-cache-size = <0x10000>; 457 i-cache-line-size = <0x40>; 458 i-cache-sets = <0x100>; 459 d-cache-size = <0x10000>; 460 d-cache-line-size = <0x40>; 461 d-cache-sets = <0x100>; 462 next-level-cache = <&CL3_L2_1>; 463 CL3_L2_1: l2-cache13 { 464 compatible = "cache"; 465 cache-level = <0x02>; 466 /* 512KB */ 467 cache-size = <0x80000>; 468 /* 64B */ 469 cache-line-size = <0x40>; 470 /* 8-way set */ 471 cache-sets = <0x400>; 472 next-level-cache = <&CL3_L3>; 473 }; 474 }; 475 476 CPU14: cpu@30200 { 477 device_type = "cpu"; 478 compatible = "arm,cortex-a720ae"; 479 reg = <0x0 0x30200>; 480 enable-method = "psci"; 481 i-cache-size = <0x10000>; 482 i-cache-line-size = <0x40>; 483 i-cache-sets = <0x100>; 484 d-cache-size = <0x10000>; 485 d-cache-line-size = <0x40>; 486 d-cache-sets = <0x100>; 487 next-level-cache = <&CL3_L2_2>; 488 CL3_L2_2: l2-cache14 { 489 compatible = "cache"; 490 cache-level = <0x02>; 491 /* 512KB */ 492 cache-size = <0x80000>; 493 /* 64B */ 494 cache-line-size = <0x40>; 495 /* 8-way set */ 496 cache-sets = <0x400>; 497 next-level-cache = <&CL3_L3>; 498 }; 499 }; 500 501 CPU15: cpu@30300 { 502 device_type = "cpu"; 503 compatible = "arm,cortex-a720ae"; 504 reg = <0x0 0x30300>; 505 enable-method = "psci"; 506 i-cache-size = <0x10000>; 507 i-cache-line-size = <0x40>; 508 i-cache-sets = <0x100>; 509 d-cache-size = <0x10000>; 510 d-cache-line-size = <0x40>; 511 d-cache-sets = <0x100>; 512 next-level-cache = <&CL3_L2_3>; 513 CL3_L2_3: l2-cache15 { 514 compatible = "cache"; 515 cache-level = <0x02>; 516 /* 512KB */ 517 cache-size = <0x80000>; 518 /* 64B */ 519 cache-line-size = <0x40>; 520 /* 8-way set */ 521 cache-sets = <0x400>; 522 next-level-cache = <&CL3_L3>; 523 }; 524 }; 525 }; 526 527 dsu-pmu-0 { 528 compatible = "arm,dsu-pmu"; 529 cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>; 530 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; 531 }; 532 533 dsu-pmu-1 { 534 compatible = "arm,dsu-pmu"; 535 cpus = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; 536 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 537 }; 538 539 dsu-pmu-2 { 540 compatible = "arm,dsu-pmu"; 541 cpus = <&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>; 542 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 543 }; 544 545 dsu-pmu-3 { 546 compatible = "arm,dsu-pmu"; 547 cpus = <&CPU12>, <&CPU13>, <&CPU14>, <&CPU15>; 548 interrupts = <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>; 549 }; 550 551 memory@80000000 { 552 device_type = "memory"; 553 554 /* Bank 0: start = 0x0000_0000_8000_0000, size = ~2 GiB (0x7F00_0000) */ 555 /* Bank 1: start = 0x0000_0200_0000_0000, size = 2 GiB (0x8000_0000) */ 556 reg = < 557 0x00000000 0x80000000 0x00000000 0x7F000000 558 0x00000200 0x00000000 0x00000000 0x80000000 559 >; 560 }; 561 562 timer { 563 compatible = "arm,armv8-timer"; 564 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 565 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 566 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 567 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 568 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 569 }; 570 571 soc_clk24mhz: clk24mhz { 572 compatible = "fixed-clock"; 573 #clock-cells = <0>; 574 clock-frequency = <24000000>; 575 clock-output-names = "refclk24mhz"; 576 }; 577 578 soc { 579 compatible = "simple-bus"; 580 #address-cells = <2>; 581 #size-cells = <2>; 582 ranges; 583 584 timer@1a810000 { 585 compatible = "arm,armv7-timer-mem"; 586 reg = <0x0 0x1a810000 0 0x10000>; 587 #address-cells = <1>; 588 #size-cells = <1>; 589 /* Map child space [0x0..0x30000) to parent @ 0x1a810000 */ 590 ranges = <0x0 0x0 0x1a810000 0x00030000>; 591 592 frame@20000 { 593 frame-number = <1>; 594 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 595 reg = <0x20000 0x10000>; 596 }; 597 }; 598 599 gic: interrupt-controller@20000000 { 600 compatible = "arm,gic-v3"; 601 reg = <0x0 0x20000000 0x0 0x10000>, /* GICD */ 602 <0x0 0x200c0000 0x0 0x400000>; /* 16 * GICR */ 603 #interrupt-cells = <3>; 604 #address-cells = <2>; 605 #size-cells = <2>; 606 ranges; 607 interrupt-controller; 608 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 609 610 its1: msi-controller@20040000 { 611 compatible = "arm,gic-v3-its"; 612 reg = <0x0 0x20040000 0x0 0x40000>; 613 msi-controller; 614 #msi-cells = <1>; 615 }; 616 its2: msi-controller@20080000 { 617 compatible = "arm,gic-v3-its"; 618 reg = <0x0 0x20080000 0x0 0x40000>; 619 msi-controller; 620 #msi-cells = <1>; 621 }; 622 }; 623 624 /* UART is fixed as 24MHz, both UARTCLK and PCLK */ 625 soc_serial0: serial@1a400000 { 626 compatible = "arm,pl011", "arm,primecell"; 627 reg = <0x0 0x1a400000 0x0 0x10000>; 628 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&soc_clk24mhz>, <&soc_clk24mhz>; 630 clock-names = "uartclk", "apb_pclk"; 631 }; 632 633 watchdog@1a420000 { 634 compatible = "arm,sbsa-gwdt"; 635 reg = <0x0 0x1a420000 0x0 0x10000>, 636 <0x0 0x1a430000 0x0 0x10000>; 637 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 638 }; 639 640 rtc@300d0000 { 641 compatible = "arm,pl031", "arm,primecell"; 642 reg = <0x0 0x300d0000 0x0 0x10000>; 643 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&soc_clk24mhz>; 645 clock-names = "apb_pclk"; 646 }; 647 648 virtio-net@30060000 { 649 compatible = "virtio,mmio"; 650 reg = <0x0 0x30060000 0x0 0x10000>; 651 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 652 }; 653 654 /* OS storage */ 655 virtio-block@30020000 { 656 compatible = "virtio,mmio"; 657 reg = <0x0 0x30020000 0x0 0x10000>; 658 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 659 }; 660 661 /* Distro installation media */ 662 virtio-block@30030000 { 663 compatible = "virtio,mmio"; 664 reg = <0x0 0x30030000 0x0 0x10000>; 665 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 666 }; 667 668 /* SystemReady ACS validation media */ 669 virtio-block@30040000 { 670 compatible = "virtio,mmio"; 671 reg = <0x0 0x30040000 0x0 0x10000>; 672 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 673 }; 674 675 /* User data media */ 676 virtio-block@30050000 { 677 compatible = "virtio,mmio"; 678 reg = <0x0 0x30050000 0x0 0x10000>; 679 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 680 }; 681 682 virtio-rng@30080000 { 683 compatible = "virtio,mmio"; 684 reg = <0x0 0x30080000 0x0 0x10000>; 685 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 686 }; 687 688 }; 689 690 psci { 691 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 692 method = "smc"; 693 cpu_suspend = <0xc4000001>; 694 cpu_off = <0x84000002>; 695 cpu_on = <0xc4000003>; 696 }; 697 698}; 699