1 /* 2 * Copyright (c) 2021-2025, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef FVP_PAS_DEF_H 7 #define FVP_PAS_DEF_H 8 9 #include <lib/gpt_rme/gpt_rme.h> 10 #include <platform_def.h> 11 12 /***************************************************************************** 13 * PAS regions used to initialize the Granule Protection Table (GPT) 14 ****************************************************************************/ 15 16 /* 17 * The PA space is initially mapped in the GPT as follows: 18 * 19 * ============================================================================ 20 * Base Addr | Size |L? GPT|PAS |Content |Comment 21 * ============================================================================ 22 * 0GB | 1GB |L0 GPT|ANY |TBROM (EL3 code) |Fixed mapping 23 * | | | |TSRAM (EL3 data) | 24 * 00000000 | 40000000 | | |IO (incl.UARTs & GIC) | 25 * ---------------------------------------------------------------------------- 26 * 1GB | 1GB |L0 GPT|ANY |IO |Fixed mapping 27 * 40000000 | 40000000 | | | | 28 * ---------------------------------------------------------------------------- 29 * 1GB+256MB | 256MB |L1 GPT|NS |PCI Memory Region 1 |Use T.Descrip 30 * 50000000 | 10000000 | | | | 31 * ---------------------------------------------------------------------------- 32 * 2GB | 2GB-64MB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip 33 * 80000000 | 7C000000 | | | | 34 * ---------------------------------------------------------------------------- 35 * 4GB-64MB |64MB-32MB-4MB|L1 GPT|SECURE|DRAM TZC |Use T.Descrip 36 * FC000000 | 1C00000 | | | | 37 * ---------------------------------------------------------------------------- 38 * 4GB-32MB | | | | | 39 * -3MB-1MB | 32MB |L1 GPT|REALM |RMM |Use T.Descrip 40 * FDC00000 | 2000000 | | | | 41 * ---------------------------------------------------------------------------- 42 * 4GB-3MB | | | | | 43 * -1MB | 4MB |L1 GPT|ROOT |EL3 DRAM data, L1 GPTs, |Use T.Descrip 44 * FFC00000 | 400000 | | |SCP TZC | 45 * ---------------------------------------------------------------------------- 46 * 34GB | 2GB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip 47 * 880000000 | 80000000 | | | | 48 * ---------------------------------------------------------------------------- 49 * 256GB | 3GB |L1 GPT|NS |PCI Memory Region 2 |Use T.Descrip 50 * 4000000000| C0000000 | | |(first 3GB only) | 51 * ============================================================================ 52 * 53 * - 4KB of L0 GPT reside in TSRAM, on top of the CONFIG section. 54 * - ~1MB of L1 GPTs reside at the top of DRAM1 (TZC area). 55 * - The first 1GB region has GPT_GPI_ANY and, therefore, is not protected by 56 * the GPT. 57 * - The DRAM TZC area is split into three regions: the L1 GPT region and 58 * 3MB of region below that are defined as GPT_GPI_ROOT, 32MB Realm region 59 * below that is defined as GPT_GPI_REALM and the rest of it is defined as 60 * GPT_GPI_SECURE. 61 */ 62 63 /* TODO: This might not be the best way to map the PAS */ 64 65 /* Device memory 0 to 2GB */ 66 #define ARM_PAS_1_BASE (U(0)) 67 #define ARM_PAS_1_SIZE (SZ_2G) /* 2GB */ 68 69 /* NS memory 2GB to (end - 64MB) */ 70 #define ARM_PAS_2_BASE (ARM_PAS_1_BASE + ARM_PAS_1_SIZE) 71 #define ARM_PAS_2_SIZE (ARM_NS_DRAM1_SIZE) 72 73 /* Shared area between EL3 and RMM */ 74 #define ARM_PAS_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) 75 #define ARM_PAS_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) 76 77 /* Secure TZC region */ 78 #define ARM_PAS_3_BASE (ARM_AP_TZC_DRAM1_BASE) 79 #define ARM_PAS_3_SIZE (ARM_AP_TZC_DRAM1_SIZE) 80 81 /* NS memory 2GB */ 82 #define ARM_PAS_4_BASE ARM_DRAM2_BASE 83 #define ARM_PAS_4_SIZE (SZ_2G) /* 2GB */ 84 85 #define ARM_PAS_KERNEL GPT_MAP_REGION_GRANULE(ARM_PAS_2_BASE, \ 86 ARM_PAS_2_SIZE, \ 87 GPT_GPI_NS) 88 89 #define ARM_PAS_SECURE GPT_MAP_REGION_GRANULE(ARM_PAS_3_BASE, \ 90 ARM_PAS_3_SIZE, \ 91 GPT_GPI_SECURE) 92 93 #define ARM_PAS_KERNEL_1 GPT_MAP_REGION_GRANULE(ARM_PAS_4_BASE, \ 94 ARM_PAS_4_SIZE, \ 95 GPT_GPI_NS) 96 97 #define ARM_PAS_PCI_MEM_1 GPT_MAP_REGION_GRANULE(PLAT_ARM_PCI_MEM_1_BASE, \ 98 PLAT_ARM_PCI_MEM_1_SIZE, \ 99 GPT_GPI_NS) 100 101 #define ARM_PAS_PCI_MEM_2 GPT_MAP_REGION_GRANULE(PLAT_ARM_PCI_MEM_2_BASE, \ 102 PLAT_ARM_PCI_MEM_2_SIZE, \ 103 GPT_GPI_NS) 104 /* 105 * REALM and Shared area share the same PAS, so consider them a single 106 * PAS region to configure in GPT. 107 */ 108 #define ARM_PAS_REALM GPT_MAP_REGION_GRANULE(ARM_REALM_BASE, \ 109 (ARM_PAS_SHARED_SIZE + \ 110 ARM_REALM_SIZE), \ 111 GPT_GPI_REALM) 112 /* Check if the EL3 TZC DRAM is contiguous with L1 GPT region. */ 113 #if (ARM_L1_GPT_BASE != (ARM_EL3_TZC_DRAM1_BASE + ARM_EL3_TZC_DRAM1_SIZE)) 114 #define ARM_PAS_EL3_DRAM GPT_MAP_REGION_GRANULE(ARM_EL3_TZC_DRAM1_BASE, \ 115 ARM_EL3_TZC_DRAM1_SIZE, \ 116 GPT_GPI_ROOT) 117 118 #define ARM_PAS_GPTS GPT_MAP_REGION_GRANULE(ARM_L1_GPT_BASE, \ 119 ARM_L1_GPT_SIZE, \ 120 GPT_GPI_ROOT) 121 #else 122 /* Contiguous ROOT region */ 123 #define ARM_PAS_EL3_DRAM GPT_MAP_REGION_GRANULE(ARM_EL3_TZC_DRAM1_BASE, \ 124 ARM_EL3_TZC_DRAM1_SIZE + \ 125 ARM_L1_GPT_SIZE, \ 126 GPT_GPI_ROOT) 127 #endif 128 129 /* GPT Configuration options */ 130 #define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS 131 132 #endif /* FVP_PAS_DEF_H */ 133