1/* 2 * Copyright (c) 2015-2025, Renesas Electronics Corporation. All rights reserved. 3 * Copyright (c) 2025, Arm Limited. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8#include <arch.h> 9#include <asm_macros.S> 10#include <console_macros.S> 11#include <drivers/renesas/rcar/console/console.h> 12#include <platform_def.h> 13 14#define SCIF_INTERNAL_CLK 0 15#define SCIF_EXTARNAL_CLK 1 16#define SCIF_CLK SCIF_INTERNAL_CLK 17 18#define PRR_PRODUCT_H3_VER_10 (0x00004F00) 19 20/* module stop */ 21#define CPG_BASE (0xE6150000) 22#define CPG_SMSTPCR2 (0x0138) 23#define CPG_SMSTPCR3 (0x013C) 24#define CPG_MSTPSR2 (0x0040) 25#define CPG_MSTPSR3 (0x0048) 26#define MSTP207 (1 << 7) 27#define MSTP310 (1 << 10) 28#define CPG_CPGWPR (0x0900) 29 30/* scif */ 31#define SCIF0_BASE (0xE6E60000) 32#define SCIF2_BASE (0xE6E88000) 33#define SCIF_SCSMR (0x00) 34#define SCIF_SCBRR (0x04) 35#define SCIF_SCSCR (0x08) 36#define SCIF_SCFTDR (0x0C) 37#define SCIF_SCFSR (0x10) 38#define SCIF_SCFRDR (0x14) 39#define SCIF_SCFCR (0x18) 40#define SCIF_SCFDR (0x1C) 41#define SCIF_SCSPTR (0x20) 42#define SCIF_SCLSR (0x24) 43#define SCIF_DL (0x30) 44#define SCIF_CKS (0x34) 45 46#if RCAR_LSI == RCAR_V3M 47#define SCIF_BASE SCIF0_BASE 48#define CPG_SMSTPCR CPG_SMSTPCR2 49#define CPG_MSTPSR CPG_MSTPSR2 50#define MSTP MSTP207 51#else 52#define SCIF_BASE SCIF2_BASE 53#define CPG_SMSTPCR CPG_SMSTPCR3 54#define CPG_MSTPSR CPG_MSTPSR3 55#define MSTP MSTP310 56#endif 57 58/* mode pin */ 59#define MODEMR_MD12 (0x00001000) 60 61#define SCSMR_CA_MASK (1 << 7) 62#define SCSMR_CA_ASYNC (0x0000) 63#define SCSMR_CHR_MASK (1 << 6) 64#define SCSMR_CHR_8 (0x0000) 65#define SCSMR_PE_MASK (1 << 5) 66#define SCSMR_PE_DIS (0x0000) 67#define SCSMR_STOP_MASK (1 << 3) 68#define SCSMR_STOP_1 (0x0000) 69#define SCSMR_CKS_MASK (3 << 0) 70#define SCSMR_CKS_DIV1 (0x0000) 71#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + \ 72 SCSMR_CHR_8 + \ 73 SCSMR_PE_DIS + \ 74 SCSMR_STOP_1 + \ 75 SCSMR_CKS_DIV1) 76#define SCBRR_115200BPS (17) 77#define SCBRR_115200BPS_D3_SSCG (16) 78#define SCBRR_115200BPS_E3_SSCG (15) 79#define SCBRR_230400BPS (8) 80 81#define SCSCR_TE_MASK (1 << 5) 82#define SCSCR_TE_DIS (0x0000) 83#define SCSCR_TE_EN (0x0020) 84#define SCSCR_RE_MASK (1 << 4) 85#define SCSCR_RE_DIS (0x0000) 86#define SCSCR_RE_EN (0x0010) 87#define SCSCR_CKE_MASK (3 << 0) 88#define SCSCR_CKE_INT (0x0000) 89#define SCSCR_CKE_BRG (0x0002) 90#if SCIF_CLK == SCIF_EXTARNAL_CLK 91#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG) 92#else 93#define SCFSR_TEND_MASK (1 << 6) 94#define SCFSR_TEND_TRANS_END (0x0040) 95#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT) 96#endif 97#define SCFSR_INIT_DATA (0x0000) 98#define SCFCR_TTRG_MASK (3 << 4) 99#define SCFCR_TTRG_8 (0x0000) 100#define SCFCR_TTRG_0 (0x0030) 101#define SCFCR_TFRST_MASK (1 << 2) 102#define SCFCR_TFRST_DIS (0x0000) 103#define SCFCR_TFRST_EN (0x0004) 104#define SCFCR_RFRS_MASK (1 << 1) 105#define SCFCR_RFRS_DIS (0x0000) 106#define SCFCR_RFRS_EN (0x0002) 107#define SCFCR_INIT_DATA (SCFCR_TTRG_8) 108#define SCFDR_T_MASK (0x1f << 8) 109#define DL_INIT_DATA (8) 110#define CKS_CKS_DIV_MASK (1 << 15) 111#define CKS_CKS_DIV_CLK (0x0000) 112#define CKS_XIN_MASK (1 << 14) 113#define CKS_XIN_SCIF_CLK (0x0000) 114#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK) 115 116 .globl console_rcar_init 117 .globl console_rcar_putc 118 .globl console_rcar_flush 119 120 /* 121 * int console_rcar_init(unsigned long base_addr, 122 * unsigned int uart_clk, unsigned int baud_rate) 123 * Function to initialize the console without a 124 * C Runtime to print debug information. This 125 * function will be accessed by console_rcar_register 126 * and crash reporting. 127 * In: x0 - console base address 128 * w1 - Uart clock in Hz 129 * w2 - Baud rate 130 * Out: return 1 on success 131 * Clobber list : x1, x2 132 */ 133func console_rcar_init 134 ldr x0, =CPG_BASE 135 ldr w1, [x0, #CPG_SMSTPCR] 136 and w1, w1, #~MSTP 137 mvn w2, w1 138 str w2, [x0, #CPG_CPGWPR] 139 str w1, [x0, #CPG_SMSTPCR] 1405: 141 ldr w1, [x0, #CPG_MSTPSR] 142 and w1, w1, #MSTP 143 cbnz w1, 5b 144 145 ldr x0, =SCIF_BASE 146 /* Clear bits TE and RE in SCSCR to 0 */ 147 mov w1, #(SCSCR_TE_DIS + SCSCR_RE_DIS) 148 strh w1, [x0, #SCIF_SCSCR] 149 /* Set bits TFRST and RFRST in SCFCR to 1 */ 150 ldrh w1, [x0, #SCIF_SCFCR] 151 orr w1, w1, #(SCFCR_TFRST_EN + SCFCR_RFRS_EN) 152 strh w1, [x0, #SCIF_SCFCR] 153 /* 154 * Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER 155 * in SCLSR, then clear them to 0 156 */ 157 mov w1, #SCFSR_INIT_DATA 158 strh w1, [x0, #SCIF_SCFSR] 159 mov w1, #0 160 strh w1, [x0, #SCIF_SCLSR] 161 /* Set bits CKE[1:0] in SCSCR */ 162 ldrh w1, [x0, #SCIF_SCSCR] 163 and w1, w1, #~SCSCR_CKE_MASK 164 mov w2, #SCSCR_CKE_INT_CLK 165 orr w1, w1, w2 166 strh w1, [x0, #SCIF_SCSCR] 167 /* Set data transfer format in SCSMR */ 168 mov w1, #SCSMR_INIT_DATA 169 strh w1, [x0, #SCIF_SCSMR] 170 /* Set value in SCBRR */ 171#if SCIF_CLK == SCIF_INTERNAL_CLK 172 ldr x1, =PRR 173 ldr w1, [x1] 174 and w1, w1, #(PRR_PRODUCT_MASK | PRR_CUT_MASK) 175 mov w2, #PRR_PRODUCT_H3_VER_10 176 cmp w1, w2 177 beq 3f 178 and w1, w1, #PRR_PRODUCT_MASK 179 mov w2, #PRR_PRODUCT_D3 180 cmp w1, w2 181 beq 5f 182 and w1, w1, #PRR_PRODUCT_MASK 183 mov w2, #PRR_PRODUCT_E3 184 cmp w1, w2 185 bne 4f 186 187 /* When SSCG(MD12) on (E3) */ 188 ldr x1, =RST_MODEMR 189 ldr w1, [x1] 190 and w1, w1, #MODEMR_MD12 191 mov w2, #MODEMR_MD12 192 cmp w1, w2 193 bne 4f 194 195 /* When SSCG(MD12) on (E3) */ 196 mov w1, #SCBRR_115200BPS_E3_SSCG 197 b 2f 1985: 199 /* In case of D3 */ 200 ldr x1, =RST_MODEMR 201 ldr w1, [x1] 202 and w1, w1, #MODEMR_MD12 203 mov w2, #MODEMR_MD12 204 cmp w1, w2 205 bne 4f 206 207 /* When SSCG(MD12) on (D3) */ 208 mov w1, #SCBRR_115200BPS_D3_SSCG 209 b 2f 2104: 211 /* In case of H3/M3/M3N or when SSCG(MD12) is off in E3/D3 */ 212 mov w1, #SCBRR_115200BPS 213 b 2f 2143: 215 mov w1, #SCBRR_230400BPS 2162: 217 strb w1, [x0, SCIF_SCBRR] 218#else 219 mov w1, #DL_INIT_DATA 220 strh w1, [x0, #SCIF_DL] 221 mov w1, #CKS_INIT_DATA 222 strh w1, [x0, #SCIF_CKS] 223#endif 224 /* 1-bit interval elapsed */ 225 mov w1, #100 2261: 227 subs w1, w1, #1 228 cbnz w1, 1b 229 /* 230 * Set bits RTRG[1:0], TTRG[1:0], and MCE in SCFCR 231 * Clear bits FRST and RFRST to 0 232 */ 233 mov w1, #SCFCR_INIT_DATA 234 strh w1, [x0, #SCIF_SCFCR] 235 /* Set bits TE and RE in SCSCR to 1 */ 236 ldrh w1, [x0, #SCIF_SCSCR] 237 orr w1, w1, #(SCSCR_TE_EN + SCSCR_RE_EN) 238 strh w1, [x0, #SCIF_SCSCR] 239 mov x0, #1 240 241 ret 242endfunc console_rcar_init 243 244 /* 245 * int console_rcar_putc(int c, unsigned int base_addr) 246 * Function to output a character over the console. It 247 * returns the character printed on success or -1 on error. 248 * In : w0 - character to be printed 249 * x1 - pointer to console_t structure 250 * Out : return -1 on error else return character. 251 * Clobber list : x2 252 */ 253func console_rcar_putc 254 ldr x1, =SCIF_BASE 255 cmp w0, #0xA 256 /* Prepend '\r' to '\n' */ 257 bne 2f 2581: 259 /* Check if the transmit FIFO is full */ 260 ldrh w2, [x1, #SCIF_SCFDR] 261 ubfx w2, w2, #8, #5 262 cmp w2, #16 263 bcs 1b 264 mov w2, #0x0D 265 strb w2, [x1, #SCIF_SCFTDR] 2662: 267 /* Check if the transmit FIFO is full */ 268 ldrh w2, [x1, #SCIF_SCFDR] 269 ubfx w2, w2, #8, #5 270 cmp w2, #16 271 bcs 2b 272 strb w0, [x1, #SCIF_SCFTDR] 273 274 /* Clear TEND flag */ 275 ldrh w2, [x1, #SCIF_SCFSR] 276 and w2, w2, #~SCFSR_TEND_MASK 277 strh w2, [x1, #SCIF_SCFSR] 278 279 ret 280endfunc console_rcar_putc 281 282 /* 283 * void console_rcar_flush(void) 284 * Function to force a write of all buffered 285 * data that hasn't been output. It returns void 286 * Clobber list : x0, x1 287 */ 288func console_rcar_flush 289 ldr x0, =SCIF_BASE 2901: 291 /* Check TEND flag */ 292 ldrh w1, [x0, #SCIF_SCFSR] 293 and w1, w1, #SCFSR_TEND_MASK 294 cmp w1, #SCFSR_TEND_TRANS_END 295 bne 1b 296 297 ldr x0, =SCIF_BASE 298 ldrh w1, [x0, #SCIF_SCSCR] 299 and w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN) 300 strh w1, [x0, #SCIF_SCSCR] 301 302 ret 303endfunc console_rcar_flush 304