1# 2# Copyright (c) 2016-2025, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Warning level to give to the compiler 14W := 0 15 16# Use T32 by default 17AARCH32_INSTRUCTION_SET := T32 18 19# The AArch32 Secure Payload to be built as BL32 image 20AARCH32_SP := none 21 22# The Target build architecture. Supported values are: aarch64, aarch32. 23ARCH := aarch64 24 25# ARM Architecture feature modifiers: none by default 26ARM_ARCH_FEATURE := none 27 28# ARM Architecture major and minor versions: 8.0 by default. 29ARM_ARCH_MAJOR := 8 30ARM_ARCH_MINOR := 0 31 32# Base commit to perform code check on 33BASE_COMMIT := origin/master 34 35# Execute BL2 at EL3 36RESET_TO_BL2 := 0 37 38# Only use SP packages if SP layout JSON is defined 39BL2_ENABLE_SP_LOAD := 0 40 41# BL2 image is stored in XIP memory, for now, this option is only supported 42# when RESET_TO_BL2 is 1. 43BL2_IN_XIP_MEM := 0 44 45# Do dcache invalidate upon BL2 entry at EL3 46BL2_INV_DCACHE := 1 47 48# Select the branch protection features to use. 49BRANCH_PROTECTION := 0 50 51# By default, consider that the platform may release several CPUs out of reset. 52# The platform Makefile is free to override this value. 53COLD_BOOT_SINGLE_CPU := 0 54 55# Flag to compile in coreboot support code. Exclude by default. The coreboot 56# Makefile system will set this when compiling TF as part of a coreboot image. 57COREBOOT := 0 58 59# For Chain of Trust 60CREATE_KEYS := 1 61 62# Build flag to include AArch32 registers in cpu context save and restore during 63# world switch. This flag must be set to 0 for AArch64-only platforms. 64CTX_INCLUDE_AARCH32_REGS := 1 65 66# Include FP registers in cpu context 67CTX_INCLUDE_FPREGS := 0 68 69# Include SVE registers in cpu context 70CTX_INCLUDE_SVE_REGS := 0 71 72# Debug build 73DEBUG := 0 74 75# By default disable authenticated decryption support. 76DECRYPTION_SUPPORT := none 77 78# Build platform 79DEFAULT_PLAT := fvp 80 81# Disable the generation of the binary image (ELF only). 82DISABLE_BIN_GENERATION := 0 83 84# Enable capability to disable authentication dynamically. Only meant for 85# development platforms. 86DYN_DISABLE_AUTH := 0 87 88# Enable the Maximum Power Mitigation Mechanism on supporting cores. 89ENABLE_MPMM := 0 90 91# Flag to Enable Position Independant support (PIE) 92ENABLE_PIE := 0 93 94# Flag to enable Performance Measurement Framework 95ENABLE_PMF := 0 96 97# Flag to enable PSCI STATs functionality 98ENABLE_PSCI_STAT := 0 99 100# Flag to enable runtime instrumentation using PMF 101ENABLE_RUNTIME_INSTRUMENTATION := 0 102 103# Flag to enable stack corruption protection 104ENABLE_STACK_PROTECTOR := 0 105 106# Flag to enable exception handling in EL3 107EL3_EXCEPTION_HANDLING := 0 108 109# Flag to include all errata for all CPUs TF-A implements workarounds for 110# Its supposed to be used only for testing. 111ENABLE_ERRATA_ALL := 0 112 113# By default BL31 encryption disabled 114ENCRYPT_BL31 := 0 115 116# By default BL32 encryption disabled 117ENCRYPT_BL32 := 0 118 119# Default dummy firmware encryption key 120ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 121 122# Default dummy nonce for firmware encryption 123ENC_NONCE := 1234567890abcdef12345678 124 125# Build flag to treat usage of deprecated platform and framework APIs as error. 126ERROR_DEPRECATED := 0 127 128# Fault injection support 129FAULT_INJECTION_SUPPORT := 0 130 131# Flag to enable architectural features detection mechanism 132FEATURE_DETECTION := 0 133 134# Byte alignment that each component in FIP is aligned to 135FIP_ALIGN := 0 136 137# Default FIP file name 138FIP_NAME := fip.bin 139 140# Default FWU_FIP file name 141FWU_FIP_NAME := fwu_fip.bin 142 143# By default firmware encryption with SSK 144FW_ENC_STATUS := 0 145 146# For Chain of Trust 147GENERATE_COT := 0 148 149# Default number of 512 blocks per bitlock 150RME_GPT_BITLOCK_BLOCK := 1 151 152# Default maximum size of GPT contiguous block 153RME_GPT_MAX_BLOCK := 512 154 155# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 156# default, they are for Secure EL1. 157GICV2_G0_FOR_EL3 := 0 158 159# Generic implementation of a GICvX driver 160USE_GIC_DRIVER := 0 161 162# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled 163# by lower ELs. 164HANDLE_EA_EL3_FIRST_NS := 0 165 166# Enable Handoff protocol using transfer lists 167TRANSFER_LIST := 0 168 169# Enable HOB list to generate boot information 170HOB_LIST := 0 171 172# Enables support for the gcc compiler option "-mharden-sls=all". 173# By default, disables all SLS hardening. 174HARDEN_SLS := 0 175 176# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 177# The default value is sha256. 178HASH_ALG := sha256 179 180# Whether system coherency is managed in hardware, without explicit software 181# operations. 182HW_ASSISTED_COHERENCY := 0 183 184# Flag to enable trapping of implementation defined sytem registers 185IMPDEF_SYSREG_TRAP := 0 186 187# Set the default algorithm for the generation of Trusted Board Boot keys 188KEY_ALG := rsa 189 190# Set the default key size in case KEY_ALG is rsa 191ifeq ($(KEY_ALG),rsa) 192KEY_SIZE := 2048 193endif 194 195# Option to build TF with Measured Boot support 196MEASURED_BOOT := 0 197 198# Option to build TF with Discrete TPM support 199DISCRETE_TPM := 0 200 201# Option to enable the DICE Protection Environmnet as a Measured Boot backend 202DICE_PROTECTION_ENVIRONMENT :=0 203 204# NS timer register save and restore 205NS_TIMER_SWITCH := 0 206 207# Include lib/libc in the final image 208OVERRIDE_LIBC := 0 209 210# Build PL011 UART driver in minimal generic UART mode 211PL011_GENERIC_UART := 0 212 213# By default, consider that the platform's reset address is not programmable. 214# The platform Makefile is free to override this value. 215PROGRAMMABLE_RESET_ADDRESS := 0 216 217# Flag used to choose the power state format: Extended State-ID or Original 218PSCI_EXTENDED_STATE_ID := 0 219 220# Enable PSCI OS-initiated mode support 221PSCI_OS_INIT_MODE := 0 222 223# SMCCC_ARCH_FEATURE_AVAILABILITY support 224ARCH_FEATURE_AVAILABILITY := 0 225 226# By default, BL1 acts as the reset handler, not BL31 227RESET_TO_BL31 := 0 228 229# For Chain of Trust 230SAVE_KEYS := 0 231 232# Software Delegated Exception support 233SDEI_SUPPORT := 0 234 235# True Random Number firmware Interface support 236TRNG_SUPPORT := 0 237 238# Check to see if Errata ABI is supported 239ERRATA_ABI_SUPPORT := 0 240 241# Check to enable Errata ABI for platforms with non-arm interconnect 242ERRATA_NON_ARM_INTERCONNECT := 0 243 244# SMCCC PCI support 245SMC_PCI_SUPPORT := 0 246 247# Whether code and read-only data should be put on separate memory pages. The 248# platform Makefile is free to override this value. 249SEPARATE_CODE_AND_RODATA := 0 250 251# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 252# separate memory region, which may be discontiguous from the rest of BL31. 253SEPARATE_NOBITS_REGION := 0 254 255# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory 256# region, platform Makefile is free to override this value. 257SEPARATE_BL2_NOLOAD_REGION := 0 258 259# Put RW DATA sections (.rwdata) in a separate memory region, which may be 260# discontiguous from the rest of BL31. 261SEPARATE_RWDATA_REGION := 0 262 263# Put SIMD context data structures in a separate memory region. Platforms 264# have the choice to put it outside of default BSS region of EL3 firmware. 265SEPARATE_SIMD_SECTION := 0 266 267# If the BL31 image initialisation code is recalimed after use for the secondary 268# cores stack 269RECLAIM_INIT_CODE := 0 270 271# SPD choice 272SPD := none 273 274# Enable the Management Mode (MM)-based Secure Partition Manager implementation 275SPM_MM := 0 276 277# Use the FF-A SPMC implementation in EL3. 278SPMC_AT_EL3 := 0 279 280# Enable SEL0 SP when SPMC is enabled at EL3 281SPMC_AT_EL3_SEL0_SP :=0 282 283# Use SPM at S-EL2 as a default config for SPMD 284SPMD_SPM_AT_SEL2 := 1 285 286# Flag to introduce an infinite loop in BL1 just before it exits into the next 287# image. This is meant to help debugging the post-BL2 phase. 288SPIN_ON_BL1_EXIT := 0 289 290# Flags to build TF with Trusted Boot support 291TRUSTED_BOARD_BOOT := 0 292 293# Build option to choose whether Trusted Firmware uses Coherent memory or not. 294USE_COHERENT_MEM := 1 295 296# Build option to add debugfs support 297USE_DEBUGFS := 0 298 299# Build option to enable passing the FDT in x0 to BL33, following the kernel 300# convention. 301USE_KERNEL_DT_CONVENTION := 0 302 303# Build option to fconf based io 304ARM_IO_IN_DTB := 0 305 306# Build option to support SDEI through fconf 307SDEI_IN_FCONF := 0 308 309# Build option to support Secure Interrupt descriptors through fconf 310SEC_INT_DESC_IN_FCONF := 0 311 312# Build option to choose whether Trusted Firmware uses library at ROM 313USE_ROMLIB := 0 314 315# Build option to choose whether the xlat tables of BL images can be read-only. 316# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 317# which is the per BL-image option that actually enables the read-only tables 318# API. The reason for having this additional option is to have a common high 319# level makefile where we can check for incompatible features/build options. 320ALLOW_RO_XLAT_TABLES := 0 321 322# Chain of trust. 323COT := tbbr 324 325# Use tbbr_oid.h instead of platform_oid.h 326USE_TBBR_DEFS := 1 327 328# Whether to enable D-Cache early during warm boot. This is usually 329# applicable for platforms wherein interconnect programming is not 330# required to enable cache coherency after warm reset (eg: single cluster 331# platforms). 332WARMBOOT_ENABLE_DCACHE_EARLY := 0 333 334# Default SVE vector length to maximum architected value 335SVE_VECTOR_LEN := 2048 336 337SANITIZE_UB := off 338 339# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 340# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 341# Default: disabled 342USE_SPINLOCK_CAS := 0 343 344# Enable Link Time Optimization 345ENABLE_LTO := 0 346 347# This option will include EL2 registers in cpu context save and restore during 348# EL2 firmware entry/exit. Internal flag not meant for direct setting. 349# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1 to enable 350# CTX_INCLUDE_EL2_REGS. 351CTX_INCLUDE_EL2_REGS := 0 352 353# Select workaround for AT speculative behaviour. 354ERRATA_SPECULATIVE_AT := 0 355 356# select workaround for SME aborting powerdown 357ERRATA_SME_POWER_DOWN := 0 358 359# Trap RAS error record access from Non secure 360RAS_TRAP_NS_ERR_REC_ACCESS := 0 361 362# Build option to create cot descriptors using fconf 363COT_DESC_IN_DTB := 0 364 365# Build option to provide OpenSSL directory path 366OPENSSL_DIR := /usr 367 368# Select the openssl binary provided in OPENSSL_DIR variable 369ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "") 370 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps 371else 372 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin 373endif 374 375# Build option to use the SP804 timer instead of the generic one 376USE_SP804_TIMER := 0 377 378# Build option to define number of firmware banks, used in firmware update 379# metadata structure. 380NR_OF_FW_BANKS := 2 381 382# Build option to define number of images in firmware bank, used in firmware 383# update metadata structure. 384NR_OF_IMAGES_IN_FW_BANK := 1 385 386# Disable Firmware update support by default 387PSA_FWU_SUPPORT := 0 388 389# Enable image description in FWU metadata by default when PSA_FWU_SUPPORT 390# is enabled. 391ifeq ($(PSA_FWU_SUPPORT),1) 392PSA_FWU_METADATA_FW_STORE_DESC := 1 393else 394PSA_FWU_METADATA_FW_STORE_DESC := 0 395endif 396 397# Dynamic Root of Trust for Measurement support 398DRTM_SUPPORT := 0 399 400# Check platform if cache management operations should be performed. 401# Disabled by default. 402CONDITIONAL_CMO := 0 403 404# By default, disable SPMD Logical partitions 405ENABLE_SPMD_LP := 0 406 407# By default, disable PSA crypto (use MbedTLS legacy crypto API). 408PSA_CRYPTO := 0 409 410# getc() support from the console(s). 411# Disabled by default because it constitutes an attack vector into TF-A. It 412# should only be enabled if there is a use case for it. 413ENABLE_CONSOLE_GETC := 0 414 415# Build option to disable EL2 when it is not used. 416# Most platforms switch from EL3 to NS-EL2 and hence the unused NS-EL2 417# functions must be enabled by platforms if they require it. 418# Disabled by default. 419INIT_UNUSED_NS_EL2 := 0 420 421# Disable including MPAM EL2 registers in context by default since currently 422# it's only enabled for NS world 423CTX_INCLUDE_MPAM_REGS := 0 424 425# Enable context memory usage reporting during BL31 setup. 426PLATFORM_REPORT_CTX_MEM_USE := 0 427 428# Enable early console 429EARLY_CONSOLE := 0 430 431# Allow platforms to save/restore DSU PMU registers over a power cycle. 432# Disabled by default and must be enabled by individual platforms. 433PRESERVE_DSU_PMU_REGS := 0 434 435# Enable RMMD to forward attestation requests from RMM to EL3. 436RMMD_ENABLE_EL3_TOKEN_SIGN := 0 437 438# Enable RMMD to program and manage IDE Keys at the PCIe Root Port(RP). 439# This flag is temporary and it is expected once the interface is 440# finalized, this flag will be removed. 441RMMD_ENABLE_IDE_KEY_PROG := 0 442 443# Live firmware activation support 444LFA_SUPPORT := 0 445 446# Enable support for arm DSU driver. 447USE_DSU_DRIVER := 0 448