xref: /rk3399_ARM-atf/plat/st/stm32mp2/stm32mp2_private.c (revision 7f690c3786224d000ff53f459f1bdb6ad05dc1d1) 
1 /*
2  * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <errno.h>
9 
10 #include <lib/xlat_tables/xlat_tables_v2.h>
11 
12 #include <platform_def.h>
13 
14 #define BKPR_FWU_INFO	48U
15 #define BKPR_BOOT_MODE	96U
16 
17 #if defined(IMAGE_BL31)
18 /* BL31 only uses the first half of the SYSRAM */
19 #define MAP_SYSRAM	MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
20 					STM32MP_SYSRAM_SIZE / 2U, \
21 					MT_MEMORY | \
22 					MT_RW | \
23 					MT_SECURE | \
24 					MT_EXECUTE_NEVER)
25 #else
26 #define MAP_SYSRAM	MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
27 					STM32MP_SYSRAM_SIZE, \
28 					MT_MEMORY | \
29 					MT_RW | \
30 					MT_SECURE | \
31 					MT_EXECUTE_NEVER)
32 #endif
33 
34 #if STM32MP_DDR_FIP_IO_STORAGE
35 #define MAP_SRAM1	MAP_REGION_FLAT(SRAM1_BASE, \
36 					SRAM1_SIZE_FOR_TFA, \
37 					MT_MEMORY | \
38 					MT_RW | \
39 					MT_SECURE | \
40 					MT_EXECUTE_NEVER)
41 #endif
42 
43 #define MAP_DEVICE	MAP_REGION_FLAT(STM32MP_DEVICE_BASE, \
44 					STM32MP_DEVICE_SIZE, \
45 					MT_DEVICE | \
46 					MT_RW | \
47 					MT_SECURE | \
48 					MT_EXECUTE_NEVER)
49 
50 #if defined(IMAGE_BL2)
51 static const mmap_region_t stm32mp2_mmap[] = {
52 	MAP_SYSRAM,
53 #if STM32MP_DDR_FIP_IO_STORAGE
54 	MAP_SRAM1,
55 #endif
56 	MAP_DEVICE,
57 	{0}
58 };
59 #endif
60 #if defined(IMAGE_BL31)
61 static const mmap_region_t stm32mp2_mmap[] = {
62 	MAP_SYSRAM,
63 	MAP_DEVICE,
64 	{0}
65 };
66 #endif
67 
68 void configure_mmu(void)
69 {
70 	mmap_add(stm32mp2_mmap);
71 	init_xlat_tables();
72 
73 	enable_mmu_el3(0);
74 }
75 
76 int stm32mp_map_retram(void)
77 {
78 	return  mmap_add_dynamic_region(RETRAM_BASE, RETRAM_BASE,
79 					RETRAM_SIZE,
80 					MT_RW | MT_SECURE);
81 }
82 
83 int stm32mp_unmap_retram(void)
84 {
85 	return  mmap_remove_dynamic_region(RETRAM_BASE,
86 					   RETRAM_SIZE);
87 }
88 
89 uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
90 {
91 	if (bank == GPIO_BANK_Z) {
92 		return GPIOZ_BASE;
93 	}
94 
95 	assert(bank <= GPIO_BANK_K);
96 
97 	return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
98 }
99 
100 uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
101 {
102 	if (bank == GPIO_BANK_Z) {
103 		return 0;
104 	}
105 
106 	assert(bank <= GPIO_BANK_K);
107 
108 	return bank * GPIO_BANK_OFFSET;
109 }
110 
111 unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
112 {
113 	if (bank == GPIO_BANK_Z) {
114 		return CK_BUS_GPIOZ;
115 	}
116 
117 	assert(bank <= GPIO_BANK_K);
118 
119 	return CK_BUS_GPIOA + (bank - GPIO_BANK_A);
120 }
121 
122 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
123 /*
124  * UART Management
125  */
126 static const uintptr_t stm32mp2_uart_addresses[STM32MP_NB_OF_UART] = {
127 	USART1_BASE,
128 	USART2_BASE,
129 	USART3_BASE,
130 	UART4_BASE,
131 	UART5_BASE,
132 	USART6_BASE,
133 	UART7_BASE,
134 	UART8_BASE,
135 	UART9_BASE,
136 };
137 
138 uintptr_t get_uart_address(uint32_t instance_nb)
139 {
140 	if ((instance_nb == 0U) ||
141 	    (instance_nb > STM32MP_NB_OF_UART)) {
142 		return 0U;
143 	}
144 
145 	return stm32mp2_uart_addresses[instance_nb - 1U];
146 }
147 #endif
148 
149 uint32_t stm32mp_get_chip_version(void)
150 {
151 	static uint32_t rev;
152 
153 	if (rev != 0U) {
154 		return rev;
155 	}
156 
157 	if (stm32_get_otp_value(REVISION_OTP, &rev) != 0) {
158 		panic();
159 	}
160 
161 	return rev;
162 }
163 
164 uint32_t stm32mp_get_chip_dev_id(void)
165 {
166 	return stm32mp_syscfg_get_chip_dev_id();
167 }
168 
169 static uint32_t get_part_number(void)
170 {
171 	static uint32_t part_number;
172 
173 	if (part_number != 0U) {
174 		return part_number;
175 	}
176 
177 	if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) {
178 		panic();
179 	}
180 
181 	return part_number;
182 }
183 
184 static uint32_t get_cpu_package(void)
185 {
186 	static uint32_t package = UINT32_MAX;
187 
188 	if (package == UINT32_MAX) {
189 		if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) {
190 			panic();
191 		}
192 	}
193 
194 	return (package & PACKAGE_OTP_PKG_MASK) >> PACKAGE_OTP_PKG_SHIFT;
195 }
196 
197 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE])
198 {
199 	char *cpu_s, *cpu_r, *pkg;
200 
201 	/* MPUs Part Numbers */
202 	switch (get_part_number()) {
203 	case STM32MP251A_PART_NB:
204 		cpu_s = "251A";
205 		break;
206 	case STM32MP251C_PART_NB:
207 		cpu_s = "251C";
208 		break;
209 	case STM32MP251D_PART_NB:
210 		cpu_s = "251D";
211 		break;
212 	case STM32MP251F_PART_NB:
213 		cpu_s = "251F";
214 		break;
215 	case STM32MP253A_PART_NB:
216 		cpu_s = "253A";
217 		break;
218 	case STM32MP253C_PART_NB:
219 		cpu_s = "253C";
220 		break;
221 	case STM32MP253D_PART_NB:
222 		cpu_s = "253D";
223 		break;
224 	case STM32MP253F_PART_NB:
225 		cpu_s = "253F";
226 		break;
227 	case STM32MP255A_PART_NB:
228 		cpu_s = "255A";
229 		break;
230 	case STM32MP255C_PART_NB:
231 		cpu_s = "255C";
232 		break;
233 	case STM32MP255D_PART_NB:
234 		cpu_s = "255D";
235 		break;
236 	case STM32MP255F_PART_NB:
237 		cpu_s = "255F";
238 		break;
239 	case STM32MP257A_PART_NB:
240 		cpu_s = "257A";
241 		break;
242 	case STM32MP257C_PART_NB:
243 		cpu_s = "257C";
244 		break;
245 	case STM32MP257D_PART_NB:
246 		cpu_s = "257D";
247 		break;
248 	case STM32MP257F_PART_NB:
249 		cpu_s = "257F";
250 		break;
251 	default:
252 		cpu_s = "????";
253 		break;
254 	}
255 
256 	/* Package */
257 	switch (get_cpu_package()) {
258 	case STM32MP25_PKG_CUSTOM:
259 		pkg = "XX";
260 		break;
261 	case STM32MP25_PKG_AL_VFBGA361:
262 		pkg = "AL";
263 		break;
264 	case STM32MP25_PKG_AK_VFBGA424:
265 		pkg = "AK";
266 		break;
267 	case STM32MP25_PKG_AI_TFBGA436:
268 		pkg = "AI";
269 		break;
270 	default:
271 		pkg = "??";
272 		break;
273 	}
274 
275 	/* REVISION */
276 	switch (stm32mp_get_chip_version()) {
277 	case STM32MP2_REV_A:
278 		cpu_r = "A";
279 		break;
280 	case STM32MP2_REV_B:
281 		cpu_r = "B";
282 		break;
283 	case STM32MP2_REV_X:
284 		cpu_r = "X";
285 		break;
286 	case STM32MP2_REV_Y:
287 		cpu_r = "Y";
288 		break;
289 	case STM32MP2_REV_Z:
290 		cpu_r = "Z";
291 		break;
292 	default:
293 		cpu_r = "?";
294 		break;
295 	}
296 
297 	snprintf(name, STM32_SOC_NAME_SIZE,
298 		 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
299 }
300 
301 void stm32mp_print_cpuinfo(void)
302 {
303 	char name[STM32_SOC_NAME_SIZE];
304 
305 	stm32mp_get_soc_name(name);
306 	NOTICE("CPU: %s\n", name);
307 }
308 
309 void stm32mp_print_boardinfo(void)
310 {
311 	uint32_t board_id = 0U;
312 
313 	if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) {
314 		return;
315 	}
316 
317 	if (board_id != 0U) {
318 		stm32_display_board_info(board_id);
319 	}
320 }
321 
322 /* Return true when SoC provides a single Cortex-A35 core, and false otherwise */
323 bool stm32mp_is_single_core(void)
324 {
325 	bool single_core = false;
326 
327 	switch (get_part_number()) {
328 	case STM32MP251A_PART_NB:
329 	case STM32MP251C_PART_NB:
330 	case STM32MP251D_PART_NB:
331 	case STM32MP251F_PART_NB:
332 		single_core = true;
333 		break;
334 	default:
335 		break;
336 	}
337 
338 	return single_core;
339 }
340 
341 /* Return true when device is in closed state */
342 uint32_t stm32mp_check_closed_device(void)
343 {
344 	return STM32MP_CHIP_SEC_OPEN;
345 }
346 
347 /* Return true when device supports secure boot */
348 bool stm32mp_is_auth_supported(void)
349 {
350 	bool supported = false;
351 
352 	switch (get_part_number()) {
353 	case STM32MP251C_PART_NB:
354 	case STM32MP251F_PART_NB:
355 	case STM32MP253C_PART_NB:
356 	case STM32MP253F_PART_NB:
357 	case STM32MP255C_PART_NB:
358 	case STM32MP255F_PART_NB:
359 	case STM32MP257C_PART_NB:
360 	case STM32MP257F_PART_NB:
361 		supported = true;
362 		break;
363 	default:
364 		break;
365 	}
366 
367 	return supported;
368 }
369 
370 bool stm32mp_is_wakeup_from_standby(void)
371 {
372 	/* TODO add source code to determine if platform is waking up from standby mode */
373 	return false;
374 }
375 
376 int stm32_risaf_get_instance(uintptr_t base)
377 {
378 	switch (base) {
379 	case RISAF2_BASE:
380 		return (int)RISAF2_INST;
381 	case RISAF4_BASE:
382 		return (int)RISAF4_INST;
383 	default:
384 		return -ENODEV;
385 	}
386 }
387 
388 uintptr_t stm32_risaf_get_base(int instance)
389 {
390 	switch (instance) {
391 	case RISAF2_INST:
392 		return (uintptr_t)RISAF2_BASE;
393 	case RISAF4_INST:
394 		return (uintptr_t)RISAF4_BASE;
395 	default:
396 		return 0U;
397 	}
398 }
399 
400 int stm32_risaf_get_max_region(int instance)
401 {
402 	switch (instance) {
403 	case RISAF2_INST:
404 		return (int)RISAF2_MAX_REGION;
405 	case RISAF4_INST:
406 		return (int)RISAF4_MAX_REGION;
407 	default:
408 		return 0;
409 	}
410 }
411 
412 uintptr_t stm32_risaf_get_memory_base(int instance)
413 {
414 	switch (instance) {
415 	case RISAF2_INST:
416 		return (uintptr_t)STM32MP_OSPI_MM_BASE;
417 	case RISAF4_INST:
418 		return (uintptr_t)STM32MP_DDR_BASE;
419 	default:
420 		return 0U;
421 	}
422 }
423 
424 size_t stm32_risaf_get_memory_size(int instance)
425 {
426 	switch (instance) {
427 	case RISAF2_INST:
428 		return STM32MP_OSPI_MM_SIZE;
429 	case RISAF4_INST:
430 		return dt_get_ddr_size();
431 	default:
432 		return 0U;
433 	}
434 }
435 
436 uintptr_t stm32_get_bkpr_boot_mode_addr(void)
437 {
438 	return tamp_bkpr(BKPR_BOOT_MODE);
439 }
440 
441 #if PSA_FWU_SUPPORT
442 uintptr_t stm32_get_bkpr_fwu_info_addr(void)
443 {
444 	return tamp_bkpr(BKPR_FWU_INFO);
445 }
446 #endif /* PSA_FWU_SUPPORT */
447 
448 uintptr_t stm32_ddrdbg_get_base(void)
449 {
450 	return DDRDBG_BASE;
451 }
452