1/* 2 * Copyright (c) 2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 model = "RD-Aspen"; 13 compatible = "arm,rdaspen"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { 19 stdout-path = &soc_serial0; 20 }; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 /* 4 clusters and 4 CPU cores in each cluster */ 27 CPU0: cpu@0 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a720ae"; 30 reg = <0x0 0x0>; 31 enable-method = "psci"; 32 i-cache-size = <0x10000>; 33 i-cache-line-size = <0x40>; 34 i-cache-sets = <0x100>; 35 d-cache-size = <0x10000>; 36 d-cache-line-size = <0x40>; 37 d-cache-sets = <0x100>; 38 }; 39 40 CPU1: cpu@100 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a720ae"; 43 reg = <0x0 0x100>; 44 enable-method = "psci"; 45 i-cache-size = <0x10000>; 46 i-cache-line-size = <0x40>; 47 i-cache-sets = <0x100>; 48 d-cache-size = <0x10000>; 49 d-cache-line-size = <0x40>; 50 d-cache-sets = <0x100>; 51 }; 52 53 CPU2: cpu@200 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a720ae"; 56 reg = <0x0 0x200>; 57 enable-method = "psci"; 58 i-cache-size = <0x10000>; 59 i-cache-line-size = <0x40>; 60 i-cache-sets = <0x100>; 61 d-cache-size = <0x10000>; 62 d-cache-line-size = <0x40>; 63 d-cache-sets = <0x100>; 64 }; 65 66 CPU3: cpu@300 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a720ae"; 69 reg = <0x0 0x300>; 70 enable-method = "psci"; 71 i-cache-size = <0x10000>; 72 i-cache-line-size = <0x40>; 73 i-cache-sets = <0x100>; 74 d-cache-size = <0x10000>; 75 d-cache-line-size = <0x40>; 76 d-cache-sets = <0x100>; 77 }; 78 79 CPU4: cpu@10000 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a720ae"; 82 reg = <0x0 0x10000>; 83 enable-method = "psci"; 84 i-cache-size = <0x10000>; 85 i-cache-line-size = <0x40>; 86 i-cache-sets = <0x100>; 87 d-cache-size = <0x10000>; 88 d-cache-line-size = <0x40>; 89 d-cache-sets = <0x100>; 90 }; 91 92 CPU5: cpu@10100 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a720ae"; 95 reg = <0x0 0x10100>; 96 enable-method = "psci"; 97 i-cache-size = <0x10000>; 98 i-cache-line-size = <0x40>; 99 i-cache-sets = <0x100>; 100 d-cache-size = <0x10000>; 101 d-cache-line-size = <0x40>; 102 d-cache-sets = <0x100>; 103 }; 104 105 CPU6: cpu@10200 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a720ae"; 108 reg = <0x0 0x10200>; 109 enable-method = "psci"; 110 i-cache-size = <0x10000>; 111 i-cache-line-size = <0x40>; 112 i-cache-sets = <0x100>; 113 d-cache-size = <0x10000>; 114 d-cache-line-size = <0x40>; 115 d-cache-sets = <0x100>; 116 }; 117 118 CPU7: cpu@10300 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a720ae"; 121 reg = <0x0 0x10300>; 122 enable-method = "psci"; 123 i-cache-size = <0x10000>; 124 i-cache-line-size = <0x40>; 125 i-cache-sets = <0x100>; 126 d-cache-size = <0x10000>; 127 d-cache-line-size = <0x40>; 128 d-cache-sets = <0x100>; 129 }; 130 131 CPU8: cpu@20000 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a720ae"; 134 reg = <0x0 0x20000>; 135 enable-method = "psci"; 136 i-cache-size = <0x10000>; 137 i-cache-line-size = <0x40>; 138 i-cache-sets = <0x100>; 139 d-cache-size = <0x10000>; 140 d-cache-line-size = <0x40>; 141 d-cache-sets = <0x100>; 142 }; 143 144 CPU9: cpu@20100 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-a720ae"; 147 reg = <0x0 0x20100>; 148 enable-method = "psci"; 149 i-cache-size = <0x10000>; 150 i-cache-line-size = <0x40>; 151 i-cache-sets = <0x100>; 152 d-cache-size = <0x10000>; 153 d-cache-line-size = <0x40>; 154 d-cache-sets = <0x100>; 155 }; 156 157 CPU10: cpu@20200 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a720ae"; 160 reg = <0x0 0x20200>; 161 enable-method = "psci"; 162 i-cache-size = <0x10000>; 163 i-cache-line-size = <0x40>; 164 i-cache-sets = <0x100>; 165 d-cache-size = <0x10000>; 166 d-cache-line-size = <0x40>; 167 d-cache-sets = <0x100>; 168 }; 169 170 CPU11: cpu@20300 { 171 device_type = "cpu"; 172 compatible = "arm,cortex-a720ae"; 173 reg = <0x0 0x20300>; 174 enable-method = "psci"; 175 i-cache-size = <0x10000>; 176 i-cache-line-size = <0x40>; 177 i-cache-sets = <0x100>; 178 d-cache-size = <0x10000>; 179 d-cache-line-size = <0x40>; 180 d-cache-sets = <0x100>; 181 }; 182 183 CPU12: cpu@30000 { 184 device_type = "cpu"; 185 compatible = "arm,cortex-a720ae"; 186 reg = <0x0 0x30000>; 187 enable-method = "psci"; 188 i-cache-size = <0x10000>; 189 i-cache-line-size = <0x40>; 190 i-cache-sets = <0x100>; 191 d-cache-size = <0x10000>; 192 d-cache-line-size = <0x40>; 193 d-cache-sets = <0x100>; 194 }; 195 196 CPU13: cpu@30100 { 197 device_type = "cpu"; 198 compatible = "arm,cortex-a720ae"; 199 reg = <0x0 0x30100>; 200 enable-method = "psci"; 201 i-cache-size = <0x10000>; 202 i-cache-line-size = <0x40>; 203 i-cache-sets = <0x100>; 204 d-cache-size = <0x10000>; 205 d-cache-line-size = <0x40>; 206 d-cache-sets = <0x100>; 207 }; 208 209 CPU14: cpu@30200 { 210 device_type = "cpu"; 211 compatible = "arm,cortex-a720ae"; 212 reg = <0x0 0x30200>; 213 enable-method = "psci"; 214 i-cache-size = <0x10000>; 215 i-cache-line-size = <0x40>; 216 i-cache-sets = <0x100>; 217 d-cache-size = <0x10000>; 218 d-cache-line-size = <0x40>; 219 d-cache-sets = <0x100>; 220 }; 221 222 CPU15: cpu@30300 { 223 device_type = "cpu"; 224 compatible = "arm,cortex-a720ae"; 225 reg = <0x0 0x30300>; 226 enable-method = "psci"; 227 i-cache-size = <0x10000>; 228 i-cache-line-size = <0x40>; 229 i-cache-sets = <0x100>; 230 d-cache-size = <0x10000>; 231 d-cache-line-size = <0x40>; 232 d-cache-sets = <0x100>; 233 }; 234 }; 235 236 memory@80000000 { 237 device_type = "memory"; 238 239 /* Bank 0: start = 0x0000_0000_8000_0000, size = ~2 GiB (0x7F00_0000) */ 240 /* Bank 1: start = 0x0000_0200_0000_0000, size = 2 GiB (0x8000_0000) */ 241 reg = < 242 0x00000000 0x80000000 0x00000000 0x7F000000 243 0x00000200 0x00000000 0x00000000 0x80000000 244 >; 245 }; 246 247 timer { 248 compatible = "arm,armv8-timer"; 249 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 250 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 251 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 252 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 253 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 254 }; 255 256 soc_clk24mhz: clk24mhz { 257 compatible = "fixed-clock"; 258 #clock-cells = <0>; 259 clock-frequency = <24000000>; 260 clock-output-names = "refclk24mhz"; 261 }; 262 263 soc { 264 compatible = "simple-bus"; 265 #address-cells = <2>; 266 #size-cells = <2>; 267 ranges; 268 269 timer@1a810000 { 270 compatible = "arm,armv7-timer-mem"; 271 reg = <0x0 0x1a810000 0 0x10000>; 272 #address-cells = <2>; 273 #size-cells = <2>; 274 clock-frequency = <125000000>; 275 ranges; 276 277 frame@1a830000 { 278 frame-number = <1>; 279 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 280 reg = <0x0 0x1a830000 0x0 0x10000>; 281 }; 282 }; 283 284 gic: interrupt-controller@20000000 { 285 compatible = "arm,gic-v3"; 286 reg = <0x0 0x20000000 0x0 0x10000>, /* GICD */ 287 <0x0 0x200c0000 0x0 0x400000>; /* 16 * GICR */ 288 #interrupt-cells = <3>; 289 #address-cells = <2>; 290 #size-cells = <2>; 291 ranges; 292 interrupt-controller; 293 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 294 295 its1: msi-controller@20040000 { 296 compatible = "arm,gic-v3-its"; 297 reg = <0x0 0x20040000 0x0 0x40000>; 298 msi-controller; 299 #msi-cells = <1>; 300 }; 301 its2: msi-controller@20080000 { 302 compatible = "arm,gic-v3-its"; 303 reg = <0x0 0x20080000 0x0 0x40000>; 304 msi-controller; 305 #msi-cells = <1>; 306 }; 307 }; 308 309 /* UART is fixed as 24MHz, both UARTCLK and PCLK */ 310 soc_serial0: serial@1a400000 { 311 compatible = "arm,pl011", "arm,primecell"; 312 reg = <0x0 0x1a400000 0x0 0x10000>; 313 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&soc_clk24mhz>, <&soc_clk24mhz>; 315 clock-names = "uartclk", "apb_pclk"; 316 }; 317 318 watchdog@1a420000 { 319 compatible = "arm,sbsa-gwdt"; 320 reg = <0x0 0x1a420000 0x0 0x10000>, 321 <0x0 0x1a430000 0x0 0x10000>; 322 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 323 }; 324 325 rtc@300d0000 { 326 compatible = "arm,pl031", "arm,primecell"; 327 reg = <0x0 0x300d0000 0x0 0x10000>; 328 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&soc_clk24mhz>; 330 clock-names = "apb_pclk"; 331 }; 332 333 virtio-net@30060000 { 334 compatible = "virtio,mmio"; 335 reg = <0x0 0x30060000 0x0 0x10000>; 336 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 337 }; 338 339 /* OS storage */ 340 virtio-block@30020000 { 341 compatible = "virtio,mmio"; 342 reg = <0x0 0x30020000 0x0 0x10000>; 343 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 344 }; 345 346 /* Distro installation media */ 347 virtio-block@30030000 { 348 compatible = "virtio,mmio"; 349 reg = <0x0 0x30030000 0x0 0x10000>; 350 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 351 }; 352 353 /* SystemReady ACS validation media */ 354 virtio-block@30040000 { 355 compatible = "virtio,mmio"; 356 reg = <0x0 0x30040000 0x0 0x10000>; 357 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 358 }; 359 360 /* User data media */ 361 virtio-block@30050000 { 362 compatible = "virtio,mmio"; 363 reg = <0x0 0x30050000 0x0 0x10000>; 364 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 365 }; 366 367 virtio-rng@30080000 { 368 compatible = "virtio,mmio"; 369 reg = <0x0 0x30080000 0x0 0x10000>; 370 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 371 }; 372 373 }; 374 375 psci { 376 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 377 method = "smc"; 378 cpu_suspend = <0xc4000001>; 379 cpu_off = <0x84000002>; 380 cpu_on = <0xc4000003>; 381 }; 382 383}; 384