1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_COND_H 8 #define MT_SPM_COND_H 9 10 #include <lpm_v2/mt_lp_rm.h> 11 12 #define SPM_RC_UPDATE_COND_ID_MASK 0xffff 13 #define SPM_RC_UPDATE_COND_RC_ID_MASK 0xffff 14 #define SPM_RC_UPDATE_COND_RC_ID_SHIFT (16) 15 16 #define SPM_RC_UPDATE_COND_RC_ID_GET(val) \ 17 ((val >> SPM_RC_UPDATE_COND_RC_ID_SHIFT) & \ 18 SPM_RC_UPDATE_COND_RC_ID_MASK) 19 20 #define SPM_RC_UPDATE_COND_ID_GET(val) (val & SPM_RC_UPDATE_COND_ID_MASK) 21 /* 22 * Definition about SPM_COND_CHECK_BLOCKED 23 * bit [00 ~ 15]: cg blocking index 24 * bit [16 ~ 29]: pll blocking index 25 * bit [62] : pll blocking information 26 * bit [63] : idle condition check fail 27 */ 28 #define SPM_COND_BLOCKED_CG_IDX (0) 29 #define SPM_COND_BLOCKED_PLL_IDX (16) 30 #define SPM_COND_CHECK_BLOCKED_PLL ((uint64_t)1 << 62L) 31 #define SPM_COND_CHECK_FAIL ((uint64_t)1 << 63L) 32 33 enum plat_spm_cond_pll { 34 PLAT_SPM_COND_PLL_UNIV = 0, 35 PLAT_SPM_COND_PLL_UNIV2, 36 PLAT_SPM_COND_PLL_MFG, 37 PLAT_SPM_COND_PLL_MFGSC, 38 PLAT_SPM_COND_PLL_SENSON, 39 PLAT_SPM_COND_PLL_MSDC, 40 PLAT_SPM_COND_PLL_UFS, 41 PLAT_SPM_COND_PLL_TVD, 42 PLAT_SPM_COND_PLL_MM, 43 PLAT_SPM_COND_PLL_MM2, 44 PLAT_SPM_COND_PLL_MAIN2, 45 PLAT_SPM_COND_PLL_IMG, 46 PLAT_SPM_COND_PLL_USB, 47 PLAT_SPM_COND_PLL_ADSP, 48 PLAT_SPM_COND_PLL_APLL1, 49 PLAT_SPM_COND_PLL_APLL2, 50 PLAT_SPM_COND_PLL_MAX 51 }; 52 53 #define PLL_BIT_MFG (1 << PLAT_SPM_COND_PLL_MFG) 54 #define PLL_BIT_MFGSC (1 << PLAT_SPM_COND_PLL_MFGSC) 55 #define PLL_BIT_SENSON (1 << PLAT_SPM_COND_PLL_SENSON) 56 #define PLL_BIT_MM (1 << PLAT_SPM_COND_PLL_MM) 57 #define PLL_BIT_MM2 (1 << PLAT_SPM_COND_PLL_MM2) 58 #define PLL_BIT_MAIN2 (1 << PLAT_SPM_COND_PLL_MAIN2) 59 #define PLL_BIT_UNIV (1 << PLAT_SPM_COND_PLL_UNIV) 60 #define PLL_BIT_UNIV2 (1 << PLAT_SPM_COND_PLL_UNIV2) 61 #define PLL_BIT_MSDC (1 << PLAT_SPM_COND_PLL_MSDC) 62 #define PLL_BIT_UFS (1 << PLAT_SPM_COND_PLL_UFS) 63 #define PLL_BIT_TVD (1 << PLAT_SPM_COND_PLL_TVD) 64 #define PLL_BIT_IMG (1 << PLAT_SPM_COND_PLL_IMG) 65 #define PLL_BIT_USB (1 << PLAT_SPM_COND_PLL_USB) 66 #define PLL_BIT_ADSP (1 << PLAT_SPM_COND_PLL_ADSP) 67 #define PLL_BIT_APLL1 (1 << PLAT_SPM_COND_PLL_APLL1) 68 #define PLL_BIT_APLL2 (1 << PLAT_SPM_COND_PLL_APLL2) 69 #define PLL_BIT_MAX (1 << PLAT_SPM_COND_PLL_MAX) 70 71 struct mt_spm_cond_tables { 72 unsigned int *table_cg; 73 uint64_t table_pll; 74 void *priv; 75 }; 76 77 struct plat_idle_cond_info { 78 /* check SPM_PWR_STATUS for bit definition */ 79 unsigned int pwr_status_mask; 80 /* cg address */ 81 uintptr_t cg_addr; 82 /* bitflip value from *addr ? */ 83 bool bBitflip; 84 /* check clkmux */ 85 uintptr_t clkmux_addr; 86 unsigned int clkmux_mask; 87 }; 88 89 struct plat_pll_cond_info { 90 uintptr_t pll_addr; 91 unsigned int pll_mask; 92 unsigned int pll_bit_set; 93 }; 94 95 struct plat_cond_info_t { 96 uintptr_t spm_pwr_status_addr; 97 uintptr_t spm_pwr_status_2nd_addr; 98 struct plat_idle_cond_info *idle_cond_table; 99 struct plat_pll_cond_info *pll_cond_table; 100 unsigned int idle_cond_num; 101 struct mt_spm_cond_tables cond_table_buf; 102 }; 103 104 uint64_t mt_spm_cond_check(const struct mt_spm_cond_tables *src, 105 const struct mt_spm_cond_tables *dest, 106 struct mt_spm_cond_tables *res); 107 uint64_t mt_spm_dump_all_pll(const struct mt_spm_cond_tables *src, 108 const struct mt_spm_cond_tables *dest, 109 struct mt_spm_cond_tables *res); 110 111 int mt_spm_cond_update(struct mt_resource_constraint **con, int num, 112 int stateid, void *priv); 113 int register_plat_cond_info(struct plat_cond_info_t *cond); 114 115 #endif 116