1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_HELPERS_H 8 #define ARCH_HELPERS_H 9 10 #include <cdefs.h> 11 #include <stdbool.h> 12 #include <stdint.h> 13 #include <string.h> 14 15 #include <arch.h> 16 #include <lib/extensions/sysreg128.h> 17 18 /********************************************************************** 19 * Macros which create inline functions to read or write CPU system 20 * registers 21 *********************************************************************/ 22 23 #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 24 static inline u_register_t read_ ## _name(void) \ 25 { \ 26 u_register_t v; \ 27 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ 28 return v; \ 29 } 30 31 #define _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) \ 32 static inline u_register_t read_ ## _name(void) \ 33 { \ 34 u_register_t v; \ 35 __asm__ ("mrs %0, " #_reg_name : "=r" (v)); \ 36 return v; \ 37 } 38 39 #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ 40 static inline void write_ ## _name(u_register_t v) \ 41 { \ 42 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ 43 } 44 45 #define SYSREG_WRITE_CONST(reg_name, v) \ 46 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v)) 47 48 /* Define read function for system register */ 49 #define DEFINE_SYSREG_READ_FUNC(_name) \ 50 _DEFINE_SYSREG_READ_FUNC(_name, _name) 51 52 /* Define read & write function for system register */ 53 #define DEFINE_SYSREG_RW_FUNCS(_name) \ 54 _DEFINE_SYSREG_READ_FUNC(_name, _name) \ 55 _DEFINE_SYSREG_WRITE_FUNC(_name, _name) 56 57 /* Define read & write function for renamed system register */ 58 #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ 59 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 60 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 61 62 /* Define read function for renamed system register */ 63 #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \ 64 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) 65 66 /* Define write function for renamed system register */ 67 #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ 68 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 69 70 /* Define read function for ID register (w/o volatile qualifier) */ 71 #define DEFINE_IDREG_READ_FUNC(_name) \ 72 _DEFINE_SYSREG_READ_FUNC_NV(_name, _name) 73 74 /* Define read function for renamed ID register (w/o volatile qualifier) */ 75 #define DEFINE_RENAME_IDREG_READ_FUNC(_name, _reg_name) \ 76 _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) 77 78 /********************************************************************** 79 * Macros to create inline functions for system instructions 80 *********************************************************************/ 81 82 /* Define function for simple system instruction */ 83 #define DEFINE_SYSOP_FUNC(_op) \ 84 static inline void _op(void) \ 85 { \ 86 __asm__ (#_op); \ 87 } 88 89 /* Define function for system instruction with register parameter */ 90 #define DEFINE_SYSOP_PARAM_FUNC(_op) \ 91 static inline void _op(uint64_t v) \ 92 { \ 93 __asm__ (#_op " %0" : : "r" (v)); \ 94 } 95 96 /* Define function for system instruction with type specifier */ 97 #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ 98 static inline void _op ## _type(void) \ 99 { \ 100 __asm__ (#_op " " #_type : : : "memory"); \ 101 } 102 103 /* Define function for system instruction with register parameter */ 104 #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ 105 static inline void _op ## _type(uint64_t v) \ 106 { \ 107 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ 108 } 109 110 /******************************************************************************* 111 * TLB maintenance accessor prototypes 112 ******************************************************************************/ 113 114 #if ERRATA_A57_813419 || ERRATA_A76_1286807 115 /* 116 * Define function for TLBI instruction with type specifier that implements 117 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of 118 * Cortex-A76. 119 */ 120 #define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\ 121 static inline void tlbi ## _type(void) \ 122 { \ 123 __asm__("tlbi " #_type "\n" \ 124 "dsb ish\n" \ 125 "tlbi " #_type); \ 126 } 127 128 /* 129 * Define function for TLBI instruction with register parameter that implements 130 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of 131 * Cortex-A76. 132 */ 133 #define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \ 134 static inline void tlbi ## _type(uint64_t v) \ 135 { \ 136 __asm__("tlbi " #_type ", %0\n" \ 137 "dsb ish\n" \ 138 "tlbi " #_type ", %0" : : "r" (v)); \ 139 } 140 #endif /* ERRATA_A57_813419 */ 141 142 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 143 /* 144 * Define function for DC instruction with register parameter that enables 145 * the workaround for errata 819472, 824069 and 827319 of Cortex-A53. 146 */ 147 #define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \ 148 static inline void dc ## _name(uint64_t v) \ 149 { \ 150 __asm__("dc " #_type ", %0" : : "r" (v)); \ 151 } 152 #endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */ 153 154 #if ERRATA_A57_813419 155 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 156 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 157 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 158 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 159 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3) 160 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is) 161 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 162 #elif ERRATA_A76_1286807 163 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1) 164 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is) 165 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2) 166 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is) 167 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3) 168 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is) 169 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1) 170 #else 171 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 172 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 173 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 174 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 175 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) 176 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) 177 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 178 #endif 179 180 #if ERRATA_A57_813419 181 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 182 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 183 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 184 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 185 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is) 186 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is) 187 #elif ERRATA_A76_1286807 188 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is) 189 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is) 190 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is) 191 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is) 192 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is) 193 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is) 194 #else 195 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 196 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 197 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 198 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 199 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is) 200 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is) 201 #endif 202 203 /******************************************************************************* 204 * Cache maintenance accessor prototypes 205 ******************************************************************************/ 206 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) 207 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) 208 #if ERRATA_A53_827319 209 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw) 210 #else 211 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) 212 #endif 213 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 214 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac) 215 #else 216 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) 217 #endif 218 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) 219 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) 220 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 221 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac) 222 #else 223 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) 224 #endif 225 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) 226 227 /******************************************************************************* 228 * Address translation accessor prototypes 229 ******************************************************************************/ 230 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r) 231 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w) 232 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r) 233 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w) 234 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r) 235 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r) 236 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r) 237 238 /******************************************************************************* 239 * Strip Pointer Authentication Code 240 ******************************************************************************/ 241 static inline u_register_t xpaci(u_register_t arg) 242 { 243 __asm__ (".arch armv8.3-a\n" 244 "xpaci %0\n" 245 : "+r" (arg)); 246 247 return arg; 248 } 249 250 void flush_dcache_range(uintptr_t addr, size_t size); 251 void flush_dcache_to_popa_range(uintptr_t addr, size_t size); 252 void flush_dcache_to_popa_range_mte2(uintptr_t addr, size_t size); 253 void clean_dcache_range(uintptr_t addr, size_t size); 254 void inv_dcache_range(uintptr_t addr, size_t size); 255 bool is_dcache_enabled(void); 256 257 void dcsw_op_louis(u_register_t op_type); 258 void dcsw_op_all(u_register_t op_type); 259 260 void disable_mmu_el1(void); 261 void disable_mmu_el3(void); 262 void disable_mpu_el2(void); 263 void disable_mmu_icache_el1(void); 264 void disable_mmu_icache_el3(void); 265 void disable_mpu_icache_el2(void); 266 267 /******************************************************************************* 268 * Misc. accessor prototypes 269 ******************************************************************************/ 270 271 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val) 272 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) 273 274 275 #if ENABLE_FEAT_D128 && !defined(SPD_tspd) 276 /* Don't use mrrs/msrr read/write implementation with tspd, 277 * While using SPD=tspd, tspd compiles with current arch_helpers 278 * thus trying to use mrrs/msrr read/write from Secure-world. 279 * SCR_EL3.D128en is set only for Non-Secure world, which may cause 280 * panic while using mrrs/msrr from tspd secure world. 281 */ 282 DECLARE_SYSREG128_RW_FUNCS(par_el1) 283 284 DECLARE_SYSREG128_RW_FUNCS(ttbr0_el1) 285 DECLARE_SYSREG128_RW_FUNCS(ttbr1_el1) 286 287 DECLARE_SYSREG128_RW_FUNCS(ttbr0_el2) 288 DECLARE_SYSREG128_RW_FUNCS(ttbr1_el2) 289 DECLARE_SYSREG128_RW_FUNCS(vttbr_el2) 290 291 /* FEAT_THE Registers */ 292 DECLARE_SYSREG128_RW_FUNCS(rcwmask_el1) 293 DECLARE_SYSREG128_RW_FUNCS(rcwsmask_el1) 294 #else 295 DEFINE_SYSREG_RW_FUNCS(par_el1) 296 297 DEFINE_SYSREG_RW_FUNCS(ttbr0_el1) 298 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) 299 300 DEFINE_SYSREG_RW_FUNCS(ttbr0_el2) 301 DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2) 302 DEFINE_SYSREG_RW_FUNCS(vttbr_el2) 303 304 /* FEAT_THE Registers */ 305 DEFINE_RENAME_SYSREG_RW_FUNCS(rcwmask_el1, RCWMASK_EL1) 306 DEFINE_RENAME_SYSREG_RW_FUNCS(rcwsmask_el1, RCWSMASK_EL1) 307 308 #endif /* ENABLE_FEAT_D128 && !defined(SPD_tspd) */ 309 310 DEFINE_IDREG_READ_FUNC(id_pfr1_el1) 311 DEFINE_IDREG_READ_FUNC(id_aa64isar0_el1) 312 DEFINE_IDREG_READ_FUNC(id_aa64isar1_el1) 313 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1) 314 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64isar3_el1, ID_AA64ISAR3_EL1) 315 DEFINE_IDREG_READ_FUNC(id_aa64pfr0_el1) 316 DEFINE_IDREG_READ_FUNC(id_aa64pfr1_el1) 317 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64pfr2_el1, ID_AA64PFR2_EL1) 318 DEFINE_IDREG_READ_FUNC(id_aa64dfr0_el1) 319 DEFINE_IDREG_READ_FUNC(id_aa64dfr1_el1) 320 DEFINE_IDREG_READ_FUNC(id_afr0_el1) 321 DEFINE_SYSREG_READ_FUNC(CurrentEl) 322 DEFINE_SYSREG_READ_FUNC(ctr_el0) 323 DEFINE_SYSREG_RW_FUNCS(daif) 324 DEFINE_SYSREG_RW_FUNCS(spsr_el1) 325 DEFINE_SYSREG_RW_FUNCS(spsr_el2) 326 DEFINE_SYSREG_RW_FUNCS(spsr_el3) 327 DEFINE_SYSREG_RW_FUNCS(elr_el1) 328 DEFINE_SYSREG_RW_FUNCS(elr_el2) 329 DEFINE_SYSREG_RW_FUNCS(elr_el3) 330 DEFINE_SYSREG_RW_FUNCS(mdccsr_el0) 331 DEFINE_SYSREG_RW_FUNCS(mdccint_el1) 332 DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0) 333 DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0) 334 DEFINE_SYSREG_RW_FUNCS(sp_el1) 335 DEFINE_SYSREG_RW_FUNCS(sp_el2) 336 DEFINE_SYSREG_RW_FUNCS(dbgprcr_el1) 337 338 DEFINE_SYSOP_FUNC(wfi) 339 DEFINE_SYSOP_FUNC(wfe) 340 DEFINE_SYSOP_FUNC(sev) 341 DEFINE_SYSOP_TYPE_FUNC(dsb, sy) 342 DEFINE_SYSOP_TYPE_FUNC(dmb, sy) 343 DEFINE_SYSOP_TYPE_FUNC(dmb, st) 344 DEFINE_SYSOP_TYPE_FUNC(dmb, ld) 345 DEFINE_SYSOP_TYPE_FUNC(dsb, ish) 346 DEFINE_SYSOP_TYPE_FUNC(dsb, osh) 347 DEFINE_SYSOP_TYPE_FUNC(dsb, nsh) 348 DEFINE_SYSOP_TYPE_FUNC(dsb, ishst) 349 DEFINE_SYSOP_TYPE_FUNC(dsb, oshst) 350 DEFINE_SYSOP_TYPE_FUNC(dmb, oshld) 351 DEFINE_SYSOP_TYPE_FUNC(dmb, oshst) 352 DEFINE_SYSOP_TYPE_FUNC(dmb, osh) 353 DEFINE_SYSOP_TYPE_FUNC(dmb, nshld) 354 DEFINE_SYSOP_TYPE_FUNC(dmb, nshst) 355 DEFINE_SYSOP_TYPE_FUNC(dmb, nsh) 356 DEFINE_SYSOP_TYPE_FUNC(dmb, ishld) 357 DEFINE_SYSOP_TYPE_FUNC(dmb, ishst) 358 DEFINE_SYSOP_TYPE_FUNC(dmb, ish) 359 DEFINE_SYSOP_FUNC(isb) 360 361 static inline void enable_irq(void) 362 { 363 /* 364 * The compiler memory barrier will prevent the compiler from 365 * scheduling non-volatile memory access after the write to the 366 * register. 367 * 368 * This could happen if some initialization code issues non-volatile 369 * accesses to an area used by an interrupt handler, in the assumption 370 * that it is safe as the interrupts are disabled at the time it does 371 * that (according to program order). However, non-volatile accesses 372 * are not necessarily in program order relatively with volatile inline 373 * assembly statements (and volatile accesses). 374 */ 375 COMPILER_BARRIER(); 376 write_daifclr(DAIF_IRQ_BIT); 377 isb(); 378 } 379 380 static inline void enable_fiq(void) 381 { 382 COMPILER_BARRIER(); 383 write_daifclr(DAIF_FIQ_BIT); 384 isb(); 385 } 386 387 static inline void enable_serror(void) 388 { 389 COMPILER_BARRIER(); 390 write_daifclr(DAIF_ABT_BIT); 391 isb(); 392 } 393 394 static inline void enable_debug_exceptions(void) 395 { 396 COMPILER_BARRIER(); 397 write_daifclr(DAIF_DBG_BIT); 398 isb(); 399 } 400 401 static inline void disable_irq(void) 402 { 403 COMPILER_BARRIER(); 404 write_daifset(DAIF_IRQ_BIT); 405 isb(); 406 } 407 408 static inline void disable_fiq(void) 409 { 410 COMPILER_BARRIER(); 411 write_daifset(DAIF_FIQ_BIT); 412 isb(); 413 } 414 415 static inline void disable_serror(void) 416 { 417 COMPILER_BARRIER(); 418 write_daifset(DAIF_ABT_BIT); 419 isb(); 420 } 421 422 static inline void disable_debug_exceptions(void) 423 { 424 COMPILER_BARRIER(); 425 write_daifset(DAIF_DBG_BIT); 426 isb(); 427 } 428 429 void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, 430 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); 431 432 /******************************************************************************* 433 * System register accessor prototypes 434 ******************************************************************************/ 435 DEFINE_IDREG_READ_FUNC(midr_el1) 436 DEFINE_SYSREG_READ_FUNC(mpidr_el1) 437 DEFINE_IDREG_READ_FUNC(id_aa64mmfr0_el1) 438 DEFINE_IDREG_READ_FUNC(id_aa64mmfr1_el1) 439 440 DEFINE_SYSREG_RW_FUNCS(scr_el3) 441 DEFINE_SYSREG_RW_FUNCS(hcr_el2) 442 443 DEFINE_SYSREG_RW_FUNCS(vbar_el1) 444 DEFINE_SYSREG_RW_FUNCS(vbar_el2) 445 DEFINE_SYSREG_RW_FUNCS(vbar_el3) 446 447 DEFINE_SYSREG_RW_FUNCS(sctlr_el1) 448 DEFINE_SYSREG_RW_FUNCS(sctlr_el2) 449 DEFINE_SYSREG_RW_FUNCS(sctlr_el3) 450 451 DEFINE_SYSREG_RW_FUNCS(actlr_el1) 452 DEFINE_SYSREG_RW_FUNCS(actlr_el2) 453 DEFINE_SYSREG_RW_FUNCS(actlr_el3) 454 455 DEFINE_SYSREG_RW_FUNCS(esr_el1) 456 DEFINE_SYSREG_RW_FUNCS(esr_el2) 457 DEFINE_SYSREG_RW_FUNCS(esr_el3) 458 459 DEFINE_SYSREG_RW_FUNCS(afsr0_el1) 460 DEFINE_SYSREG_RW_FUNCS(afsr0_el2) 461 DEFINE_SYSREG_RW_FUNCS(afsr0_el3) 462 463 DEFINE_SYSREG_RW_FUNCS(afsr1_el1) 464 DEFINE_SYSREG_RW_FUNCS(afsr1_el2) 465 DEFINE_SYSREG_RW_FUNCS(afsr1_el3) 466 467 DEFINE_SYSREG_RW_FUNCS(far_el1) 468 DEFINE_SYSREG_RW_FUNCS(far_el2) 469 DEFINE_SYSREG_RW_FUNCS(far_el3) 470 471 DEFINE_SYSREG_RW_FUNCS(mair_el1) 472 DEFINE_SYSREG_RW_FUNCS(mair_el2) 473 DEFINE_SYSREG_RW_FUNCS(mair_el3) 474 475 DEFINE_SYSREG_RW_FUNCS(amair_el1) 476 DEFINE_SYSREG_RW_FUNCS(amair_el2) 477 DEFINE_SYSREG_RW_FUNCS(amair_el3) 478 479 DEFINE_SYSREG_READ_FUNC(rvbar_el1) 480 DEFINE_SYSREG_READ_FUNC(rvbar_el2) 481 DEFINE_SYSREG_READ_FUNC(rvbar_el3) 482 483 DEFINE_SYSREG_RW_FUNCS(rmr_el1) 484 DEFINE_SYSREG_RW_FUNCS(rmr_el2) 485 DEFINE_SYSREG_RW_FUNCS(rmr_el3) 486 487 DEFINE_SYSREG_RW_FUNCS(tcr_el1) 488 DEFINE_SYSREG_RW_FUNCS(tcr_el2) 489 DEFINE_SYSREG_RW_FUNCS(tcr_el3) 490 491 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) 492 493 DEFINE_SYSREG_RW_FUNCS(cptr_el2) 494 DEFINE_SYSREG_RW_FUNCS(cptr_el3) 495 496 DEFINE_SYSREG_RW_FUNCS(cpacr_el1) 497 DEFINE_SYSREG_RW_FUNCS(cntfrq_el0) 498 DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2) 499 DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2) 500 DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2) 501 DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1) 502 DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1) 503 DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1) 504 DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0) 505 DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0) 506 DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0) 507 DEFINE_SYSREG_READ_FUNC(cntpct_el0) 508 DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) 509 DEFINE_SYSREG_RW_FUNCS(cntv_ctl_el0) 510 DEFINE_SYSREG_RW_FUNCS(cntv_cval_el0) 511 DEFINE_SYSREG_RW_FUNCS(cntkctl_el1) 512 513 DEFINE_SYSREG_RW_FUNCS(vtcr_el2) 514 515 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ 516 CNTP_CTL_ENABLE_MASK) 517 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ 518 CNTP_CTL_IMASK_MASK) 519 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ 520 CNTP_CTL_ISTATUS_MASK) 521 522 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT)) 523 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT)) 524 525 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) 526 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) 527 528 DEFINE_SYSREG_RW_FUNCS(tpidr_el0) 529 DEFINE_SYSREG_RW_FUNCS(tpidr_el1) 530 DEFINE_SYSREG_RW_FUNCS(tpidr_el2) 531 DEFINE_SYSREG_RW_FUNCS(tpidr_el3) 532 533 DEFINE_SYSREG_RW_FUNCS(cntvoff_el2) 534 535 DEFINE_SYSREG_RW_FUNCS(vpidr_el2) 536 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) 537 538 DEFINE_SYSREG_RW_FUNCS(hacr_el2) 539 DEFINE_SYSREG_RW_FUNCS(hpfar_el2) 540 541 DEFINE_SYSREG_RW_FUNCS(dbgvcr32_el2) 542 DEFINE_RENAME_SYSREG_RW_FUNCS(ich_hcr_el2, ICH_HCR_EL2) 543 DEFINE_RENAME_SYSREG_RW_FUNCS(ich_vmcr_el2, ICH_VMCR_EL2) 544 545 DEFINE_SYSREG_READ_FUNC(isr_el1) 546 547 DEFINE_SYSREG_RW_FUNCS(mdscr_el1) 548 DEFINE_SYSREG_RW_FUNCS(mdcr_el2) 549 DEFINE_SYSREG_RW_FUNCS(mdcr_el3) 550 DEFINE_SYSREG_RW_FUNCS(hstr_el2) 551 DEFINE_SYSREG_RW_FUNCS(pmcr_el0) 552 553 DEFINE_SYSREG_RW_FUNCS(csselr_el1) 554 DEFINE_SYSREG_RW_FUNCS(tpidrro_el0) 555 DEFINE_SYSREG_RW_FUNCS(contextidr_el1) 556 DEFINE_SYSREG_RW_FUNCS(spsr_abt) 557 DEFINE_SYSREG_RW_FUNCS(spsr_und) 558 DEFINE_SYSREG_RW_FUNCS(spsr_irq) 559 DEFINE_SYSREG_RW_FUNCS(spsr_fiq) 560 DEFINE_SYSREG_RW_FUNCS(dacr32_el2) 561 DEFINE_SYSREG_RW_FUNCS(ifsr32_el2) 562 563 /* GICv5 System Registers */ 564 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr0_el3, ICC_PPI_DOMAINR0_EL3) 565 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr1_el3, ICC_PPI_DOMAINR1_EL3) 566 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr2_el3, ICC_PPI_DOMAINR2_EL3) 567 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr3_el3, ICC_PPI_DOMAINR3_EL3) 568 569 /* GICv3 System Registers */ 570 571 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) 572 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) 573 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) 574 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) 575 DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1) 576 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3) 577 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1) 578 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1) 579 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1) 580 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1) 581 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1) 582 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1) 583 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) 584 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) 585 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1) 586 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) 587 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r, ICC_ASGI1R) 588 589 DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0) 590 DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0) 591 DEFINE_RENAME_SYSREG_READ_FUNC(amcg1idr_el0, AMCG1IDR_EL0) 592 DEFINE_RENAME_SYSREG_RW_FUNCS(amcr_el0, AMCR_EL0) 593 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0) 594 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0) 595 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0) 596 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0) 597 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr00_el0, AMEVCNTR00_EL0); 598 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr01_el0, AMEVCNTR01_EL0); 599 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr02_el0, AMEVCNTR02_EL0); 600 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr03_el0, AMEVCNTR03_EL0); 601 602 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr10_el0, AMEVCNTR10_EL0); 603 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr11_el0, AMEVCNTR11_EL0); 604 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr12_el0, AMEVCNTR12_EL0); 605 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr13_el0, AMEVCNTR13_EL0); 606 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr14_el0, AMEVCNTR14_EL0); 607 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr15_el0, AMEVCNTR15_EL0); 608 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr16_el0, AMEVCNTR16_EL0); 609 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr17_el0, AMEVCNTR17_EL0); 610 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr18_el0, AMEVCNTR18_EL0); 611 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr19_el0, AMEVCNTR19_EL0); 612 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr1a_el0, AMEVCNTR1A_EL0); 613 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr1b_el0, AMEVCNTR1B_EL0); 614 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr1c_el0, AMEVCNTR1C_EL0); 615 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr1d_el0, AMEVCNTR1D_EL0); 616 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr1e_el0, AMEVCNTR1E_EL0); 617 DEFINE_RENAME_SYSREG_RW_FUNCS(amevcntr1f_el0, AMEVCNTR1F_EL0); 618 619 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1) 620 621 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3) 622 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2) 623 624 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1) 625 DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el3, SMCR_EL3) 626 DEFINE_RENAME_SYSREG_RW_FUNCS(svcr, SVCR) 627 628 DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1) 629 DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1) 630 631 DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1) 632 DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1) 633 DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1) 634 DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1) 635 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1) 636 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1) 637 638 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el2, SCXTNUM_EL2) 639 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el1, SCXTNUM_EL1) 640 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el0, SCXTNUM_EL0) 641 642 /* Armv8.1 VHE Registers */ 643 DEFINE_RENAME_SYSREG_RW_FUNCS(contextidr_el2, CONTEXTIDR_EL2) 644 645 /* Armv8.2 ID Registers */ 646 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) 647 648 /* Armv8.2 RAS Registers */ 649 DEFINE_RENAME_SYSREG_RW_FUNCS(disr_el1, DISR_EL1) 650 DEFINE_RENAME_SYSREG_RW_FUNCS(vdisr_el2, VDISR_EL2) 651 DEFINE_RENAME_SYSREG_RW_FUNCS(vsesr_el2, VSESR_EL2) 652 653 /* Armv8.2 MPAM Registers */ 654 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1) 655 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3) 656 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2) 657 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2) 658 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm0_el2, MPAMVPM0_EL2) 659 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm1_el2, MPAMVPM1_EL2) 660 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm2_el2, MPAMVPM2_EL2) 661 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm3_el2, MPAMVPM3_EL2) 662 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm4_el2, MPAMVPM4_EL2) 663 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm5_el2, MPAMVPM5_EL2) 664 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm6_el2, MPAMVPM6_EL2) 665 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm7_el2, MPAMVPM7_EL2) 666 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpmv_el2, MPAMVPMV_EL2) 667 668 /* Armv8.3 Pointer Authentication Registers */ 669 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1) 670 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1) 671 672 /* Armv8.4 Data Independent Timing Register */ 673 DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT) 674 675 /* Armv8.4 FEAT_TRF Register */ 676 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2) 677 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el1, TRFCR_EL1) 678 DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2) 679 680 /* Armv8.5 MTE Registers */ 681 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1) 682 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1) 683 DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1) 684 DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1) 685 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el2, TFSR_EL2) 686 687 /* Armv8.5 FEAT_RNG Registers */ 688 DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR) 689 DEFINE_RENAME_SYSREG_READ_FUNC(rndrrs, RNDRRS) 690 691 /* Armv8.6 FEAT_FGT Registers */ 692 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2) 693 DEFINE_RENAME_SYSREG_RW_FUNCS(hafgrtr_el2, HAFGRTR_EL2) 694 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2) 695 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2) 696 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2) 697 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2) 698 699 /* ARMv8.6 FEAT_ECV Register */ 700 DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2) 701 702 /* FEAT_HCX Register */ 703 DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2) 704 705 /* Armv8.9 system registers */ 706 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3_EL1) 707 708 /* Armv8.9 FEAT_FGT2 Registers */ 709 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr2_el2, HDFGRTR2_EL2) 710 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr2_el2, HDFGWTR2_EL2) 711 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr2_el2, HFGITR2_EL2) 712 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr2_el2, HFGRTR2_EL2) 713 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr2_el2, HFGWTR2_EL2) 714 715 /* FEAT_TCR2 Register */ 716 DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el1, TCR2_EL1) 717 DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el2, TCR2_EL2) 718 719 /* FEAT_SxPIE Registers */ 720 DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el1, PIRE0_EL1) 721 DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el2, PIRE0_EL2) 722 DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el1, PIR_EL1) 723 DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el2, PIR_EL2) 724 DEFINE_RENAME_SYSREG_RW_FUNCS(s2pir_el2, S2PIR_EL2) 725 726 /* FEAT_SxPOE Registers */ 727 DEFINE_RENAME_SYSREG_RW_FUNCS(por_el1, POR_EL1) 728 DEFINE_RENAME_SYSREG_RW_FUNCS(por_el2, POR_EL2) 729 DEFINE_RENAME_SYSREG_RW_FUNCS(s2por_el1, S2POR_EL1) 730 731 /* FEAT_GCS Registers */ 732 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2) 733 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2) 734 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el1, GCSCR_EL1) 735 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscre0_el1, GCSCRE0_EL1) 736 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el1, GCSPR_EL1) 737 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el0, GCSPR_EL0) 738 739 /* FEAT_SCTLR2 Registers */ 740 DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el1, SCTLR2_EL1) 741 DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el2, SCTLR2_EL2) 742 DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el3, SCTLR2_EL3) 743 744 /* FEAT_LS64_ACCDATA Registers */ 745 DEFINE_RENAME_SYSREG_RW_FUNCS(accdata_el1, ACCDATA_EL1) 746 747 /* DynamIQ Control registers */ 748 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1) 749 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmcr_el1, CLUSTERPMCR_EL1) 750 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmcntenset_el1, CLUSTERPMCNTENSET_EL1) 751 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmccntr_el1, CLUSTERPMCCNTR_EL1) 752 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmovsset_el1, CLUSTERPMOVSSET_EL1) 753 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmovsclr_el1, CLUSTERPMOVSCLR_EL1) 754 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmselr_el1, CLUSTERPMSELR_EL1) 755 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmxevcntr_el1, CLUSTERPMXEVCNTR_EL1) 756 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmxevtyper_el1, CLUSTERPMXEVTYPER_EL1) 757 758 /* CPU Power/Performance Management registers */ 759 DEFINE_RENAME_SYSREG_RW_FUNCS(cpuppmcr_el3, CPUPPMCR_EL3) 760 DEFINE_RENAME_SYSREG_RW_FUNCS(cpumpmmcr_el3, CPUMPMMCR_EL3) 761 762 /* Armv9.1 FEAT_BRBE Registers */ 763 DEFINE_RENAME_SYSREG_RW_FUNCS(brbcr_el2, BRBCR_EL2) 764 765 /* Armv9.2 RME Registers */ 766 DEFINE_RENAME_SYSREG_RW_FUNCS(gptbr_el3, GPTBR_EL3) 767 DEFINE_RENAME_SYSREG_RW_FUNCS(gpccr_el3, GPCCR_EL3) 768 769 DEFINE_RENAME_SYSREG_RW_FUNCS(fpmr, FPMR) 770 771 /* FEAT_MEC Registers */ 772 DEFINE_RENAME_SYSREG_READ_FUNC(mecidr_el2, MECIDR_EL2) 773 774 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr4_el1, ID_AA64MMFR4_EL1) 775 776 /* FEAT_FGWTE3 Registers */ 777 DEFINE_RENAME_SYSREG_RW_FUNCS(fgwte3_el3, FGWTE3_EL3) 778 779 /* Armv9.3 MPAM_PE_BW_CTRL Registers */ 780 DEFINE_RENAME_SYSREG_RW_FUNCS(mpambw2_el2, MPAMBW2_EL2) 781 DEFINE_RENAME_SYSREG_RW_FUNCS(mpambw3_el3, MPAMBW3_EL3) 782 783 #define IS_IN_EL(x) \ 784 (GET_EL(read_CurrentEl()) == MODE_EL##x) 785 786 #define IS_IN_EL1() IS_IN_EL(1) 787 #define IS_IN_EL2() IS_IN_EL(2) 788 #define IS_IN_EL3() IS_IN_EL(3) 789 790 static inline unsigned int get_current_el(void) 791 { 792 return GET_EL(read_CurrentEl()); 793 } 794 795 static inline unsigned int get_current_el_maybe_constant(void) 796 { 797 #if defined(IMAGE_AT_EL1) 798 return 1; 799 #elif defined(IMAGE_AT_EL2) 800 return 2; /* no use-case in TF-A */ 801 #elif defined(IMAGE_AT_EL3) 802 return 3; 803 #else 804 /* 805 * If we do not know which exception level this is being built for 806 * (e.g. built for library), fall back to run-time detection. 807 */ 808 return get_current_el(); 809 #endif 810 } 811 812 /* 813 * Check if an EL is implemented from AA64PFR0 register fields. 814 */ 815 static inline uint64_t el_implemented(unsigned int el) 816 { 817 if (el > 3U) { 818 return EL_IMPL_NONE; 819 } else { 820 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el; 821 822 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK; 823 } 824 } 825 826 /* 827 * TLBI PAALLOS instruction 828 * (TLB Invalidate GPT Information by PA, All Entries, Outer Shareable) 829 */ 830 static inline void tlbipaallos(void) 831 { 832 __asm__("sys #6, c8, c1, #4"); 833 } 834 835 /* 836 * TLBI RPALOS instructions 837 * (TLB Range Invalidate GPT Information by PA, Last level, Outer Shareable) 838 * 839 * command SIZE, bits [47:44] field: 840 * 0b0000 4KB 841 * 0b0001 16KB 842 * 0b0010 64KB 843 * 0b0011 2MB 844 * 0b0100 32MB 845 * 0b0101 512MB 846 * 0b0110 1GB 847 * 0b0111 16GB 848 * 0b1000 64GB 849 * 0b1001 512GB 850 */ 851 #define TLBI_SZ_4K 0UL 852 #define TLBI_SZ_16K 1UL 853 #define TLBI_SZ_64K 2UL 854 #define TLBI_SZ_2M 3UL 855 #define TLBI_SZ_32M 4UL 856 #define TLBI_SZ_512M 5UL 857 #define TLBI_SZ_1G 6UL 858 #define TLBI_SZ_16G 7UL 859 #define TLBI_SZ_64G 8UL 860 #define TLBI_SZ_512G 9UL 861 862 #define TLBI_ADDR_SHIFT U(12) 863 #define TLBI_SIZE_SHIFT U(44) 864 865 #define TLBIRPALOS(_addr, _size) \ 866 { \ 867 u_register_t arg = ((_addr) >> TLBI_ADDR_SHIFT) | \ 868 ((_size) << TLBI_SIZE_SHIFT); \ 869 __asm__("sys #6, c8, c4, #7, %0" : : "r" (arg)); \ 870 } 871 872 /* Note: addr must be aligned to 4KB */ 873 static inline void tlbirpalos_4k(uintptr_t addr) 874 { 875 TLBIRPALOS(addr, TLBI_SZ_4K); 876 } 877 878 /* Note: addr must be aligned to 16KB */ 879 static inline void tlbirpalos_16k(uintptr_t addr) 880 { 881 TLBIRPALOS(addr, TLBI_SZ_16K); 882 } 883 884 /* Note: addr must be aligned to 64KB */ 885 static inline void tlbirpalos_64k(uintptr_t addr) 886 { 887 TLBIRPALOS(addr, TLBI_SZ_64K); 888 } 889 890 /* Note: addr must be aligned to 2MB */ 891 static inline void tlbirpalos_2m(uintptr_t addr) 892 { 893 TLBIRPALOS(addr, TLBI_SZ_2M); 894 } 895 896 /* Note: addr must be aligned to 32MB */ 897 static inline void tlbirpalos_32m(uintptr_t addr) 898 { 899 TLBIRPALOS(addr, TLBI_SZ_32M); 900 } 901 902 /* Note: addr must be aligned to 512MB */ 903 static inline void tlbirpalos_512m(uintptr_t addr) 904 { 905 TLBIRPALOS(addr, TLBI_SZ_512M); 906 } 907 908 /* Previously defined accessor functions with incomplete register names */ 909 910 #define read_current_el() read_CurrentEl() 911 912 #define dsb() dsbsy() 913 914 #define read_midr() read_midr_el1() 915 916 #define read_mpidr() read_mpidr_el1() 917 918 #define read_scr() read_scr_el3() 919 #define write_scr(_v) write_scr_el3(_v) 920 921 #define read_hcr() read_hcr_el2() 922 #define write_hcr(_v) write_hcr_el2(_v) 923 924 #define read_cpacr() read_cpacr_el1() 925 #define write_cpacr(_v) write_cpacr_el1(_v) 926 927 #define read_clusterpwrdn() read_clusterpwrdn_el1() 928 #define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v) 929 930 #define read_clusterpmcr() read_clusterpmcr_el1() 931 #define write_clusterpmcr(_v) write_clusterpmcr_el1(_v) 932 933 #define read_clusterpmcntenset() read_clusterpmcntenset_el1() 934 #define write_clusterpmcntenset(_v) write_clusterpmcntenset_el1(_v) 935 936 #define read_clusterpmccntr() read_clusterpmccntr_el1() 937 #define write_clusterpmccntr(_v) write_clusterpmccntr_el1(_v) 938 939 #define read_clusterpmovsset() read_clusterpmovsset_el1() 940 #define write_clusterpmovsset(_v) write_clusterpmovsset_el1(_v) 941 942 #define read_clusterpmovsclr() read_clusterpmovsclr_el1() 943 #define write_clusterpmovsclr(_v) write_clusterpmovsclr_el1(_v) 944 945 #define read_clusterpmselr() read_clusterpmselr_el1() 946 #define write_clusterpmselr(_v) write_clusterpmselr_el1(_v) 947 948 #define read_clusterpmxevcntr() read_clusterpmxevcntr_el1() 949 #define write_clusterpmxevcntr(_v) write_clusterpmxevcntr_el1(_v) 950 951 #define read_clusterpmxevtyper() read_clusterpmxevtyper_el1() 952 #define write_clusterpmxevtyper(_v) write_clusterpmxevtyper_el1(_v) 953 954 #if ERRATA_SPECULATIVE_AT 955 /* 956 * Assuming SCTLR.M bit is already enabled 957 * 1. Enable page table walk by clearing TCR_EL1.EPDx bits 958 * 2. Execute AT instruction for lower EL1/0 959 * 3. Disable page table walk by setting TCR_EL1.EPDx bits 960 */ 961 #define AT(_at_inst, _va) \ 962 { \ 963 assert((read_sctlr_el1() & SCTLR_M_BIT) != 0ULL); \ 964 write_tcr_el1(read_tcr_el1() & ~(TCR_EPD0_BIT | TCR_EPD1_BIT)); \ 965 isb(); \ 966 _at_inst(_va); \ 967 write_tcr_el1(read_tcr_el1() | (TCR_EPD0_BIT | TCR_EPD1_BIT)); \ 968 isb(); \ 969 } 970 #else 971 #define AT(_at_inst, _va) _at_inst(_va) 972 #endif 973 974 #endif /* ARCH_HELPERS_H */ 975