1 /* 2 * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. 3 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef POWERMANAGER_H 9 #define POWERMANAGER_H 10 11 #include "socfpga_handoff.h" 12 13 #define AGX5_PWRMGR_BASE 0x10d14000 14 15 /* DSU */ 16 #define AGX5_PWRMGR_DSU_FWENCTL 0x0 17 #define AGX5_PWRMGR_DSU_PGENCTL 0x4 18 #define AGX5_PWRMGR_DSU_PGSTAT 0x8 19 #define AGX5_PWRMGR_DSU_PWRCTLR 0xc 20 #define AGX5_PWRMGR_DSU_PWRSTAT0 0x10 21 #define AGX5_PWRMGR_DSU_PWRSTAT1 0x14 22 23 /* DSU Macros*/ 24 #define AGX5_PWRMGR_DSU_FWEN(x) ((x) & 0xf) 25 #define AGX5_PWRMGR_DSU_PGEN(x) ((x) & 0xf) 26 #define AGX5_PWRMGR_DSU_PGEN_OUT(x) ((x) & 0xf) 27 #define AGX5_PWRMGR_DSU_SINGLE_PACCEPT(x) ((x) & 0x1) 28 #define AGX5_PWRMGR_DSU_SINGLE_PDENY(x) (((x) & 0x1) << 1) 29 #define AGX5_PWRMGR_DSU_SINGLE_FSM_STATE(x) (((x) & 0xff) << 8) 30 #define AGX5_PWRMGR_DSU_SINGLE_PCH_DONE(x) (((x) & 0x1) << 31) 31 #define AGX5_PWRMGR_DSU_MULTI_PACTIVE_IN(x) ((x) & 0xff) 32 #define AGX5_PWRMGR_DSU_MULTI_PACCEPT(x) (((x) & 0xff) << 8) 33 #define AGX5_PWRMGR_DSU_MULTI_PDENY(x) (((x) & 0xff) << 16) 34 #define AGX5_PWRMGR_DSU_MULTI_PCH_DONE(x) (((x) & 0x1) << 31) 35 36 /* CPU */ 37 #define AGX5_PWRMGR_CPU_PWRCTLR0 0x18 38 #define AGX5_PWRMGR_CPU_PWRCTLR1 0x20 39 #define AGX5_PWRMGR_CPU_PWRCTLR2 0x28 40 #define AGX5_PWRMGR_CPU_PWRCTLR3 0x30 41 #define AGX5_PWRMGR_CPU_PWRSTAT0 0x1c 42 #define AGX5_PWRMGR_CPU_PWRSTAT1 0x24 43 #define AGX5_PWRMGR_CPU_PWRSTAT2 0x2c 44 #define AGX5_PWRMGR_CPU_PWRSTAT3 0x34 45 #define AGX5_PWRMGR_CPU_RUN_PCH(x) ((x) & 0x1) 46 #define AGX5_PWRMGR_CPU_POLL_COUNT 10 47 #define AGX5_PWRMGR_CPU_DELAY_10_US 10 48 49 /* CPU_SINGLE_FSM_STATE located at bit 9:2, 50 * masking with 0x3fc to get the field 51 */ 52 #define AGX5_PWRMGR_CPU_SINGLE_FSM_STATE(x) (((x) & 0x3fc) >> 2) 53 #define AGX5_PWRMGR_CPU_PROG_CPU_ON_STATE 0x10 54 55 /* APS */ 56 #define AGX5_PWRMGR_APS_FWENCTL 0x38 57 #define AGX5_PWRMGR_APS_PGENCTL 0x3C 58 #define AGX5_PWRMGR_APS_PGSTAT 0x40 59 60 /* PSS */ 61 #define AGX5_PWRMGR_PSS_FWENCTL 0x44 62 #define AGX5_PWRMGR_PSS_PGENCTL 0x48 63 #define AGX5_PWRMGR_PSS_PGSTAT 0x4c 64 65 /* PSS Macros*/ 66 #define AGX5_PWRMGR_PSS_FWEN(x) ((x) & 0xff) 67 #define AGX5_PWRMGR_PSS_PGEN(x) ((x) & 0xff) 68 #define AGX5_PWRMGR_PSS_PGEN_OUT(x) ((x) & 0xff) 69 70 /* MPU */ 71 #define AGX5_PWRMGR_MPU_PCHCTLR 0x50 72 #define AGX5_PWRMGR_MPU_PCHSTAT 0x54 73 #define AGX5_PWRMGR_MPU_BOOTCONFIG 0x58 74 #define AGX5_PWRMGR_CPU_POWER_STATE_MASK 0x1E 75 76 /* MPU Macros*/ 77 #define AGX5_PWRMGR_MPU_TRIGGER_PCH_DSU(x) ((x) & 0x1) 78 #define AGX5_PWRMGR_MPU_TRIGGER_PCH_CPU(x) (((x) & 0xf) << 1) 79 #define AGX5_PWRMGR_MPU_STATUS_PCH_CPU(x) (((x) & 0xf) << 1) 80 81 /* Shared Macros */ 82 #define AGX5_PWRMGR(_reg) (AGX5_PWRMGR_BASE + \ 83 (AGX5_PWRMGR_##_reg)) 84 85 /* POWER MANAGER ERROR CODE */ 86 #define AGX5_PWRMGR_HANDOFF_PERIPHERAL -1 87 #define AGX5_PWRMGR_PSS_STAT_BUSY_E_BUSY 0x0 88 #define AGX5_PWRMGR_PSS_STAT_BUSY(x) (((x) & 0x000000FF) >> 0) 89 90 void config_pwrmgr_handoff(handoff *hoff_ptr); 91 #endif 92