1 /* 2 * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* Runtime C routines for errata workarounds and common routines */ 8 9 #include <assert.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <cortex_a75.h> 14 #include <cortex_a510.h> 15 #include <cortex_a520.h> 16 #include <cortex_a710.h> 17 #include <cortex_a715.h> 18 #include <cortex_a720.h> 19 #include <cortex_a720_ae.h> 20 #include <cortex_a725.h> 21 #include <cortex_x2.h> 22 #include <cortex_x3.h> 23 #include <cortex_x4.h> 24 #include <cortex_x925.h> 25 #include <lib/cpus/cpu_ops.h> 26 #include <lib/cpus/errata.h> 27 #include <neoverse_n2.h> 28 #include <neoverse_n3.h> 29 #include <neoverse_v2.h> 30 #include <neoverse_v3.h> 31 32 struct erratum_entry *find_erratum_entry(uint32_t errata_id) 33 { 34 struct cpu_ops *cpu_ops; 35 struct erratum_entry *entry, *end; 36 37 cpu_ops = get_cpu_ops_ptr(); 38 assert(cpu_ops != NULL); 39 40 entry = cpu_ops->errata_list_start; 41 assert(entry != NULL); 42 43 end = cpu_ops->errata_list_end; 44 assert(end != NULL); 45 46 end--; /* point to the last erratum entry of the queried cpu */ 47 48 while ((entry <= end)) { 49 if (entry->id == errata_id) { 50 return entry; 51 } 52 entry += 1; 53 } 54 return NULL; 55 } 56 57 bool check_if_trbe_disable_affected_core(void) 58 { 59 switch (EXTRACT_PARTNUM(read_midr())) { 60 #if ERRATA_A520_2938996 61 case EXTRACT_PARTNUM(CORTEX_A520_MIDR): 62 return check_erratum_cortex_a520_2938996(cpu_get_rev_var()) == ERRATA_APPLIES; 63 #endif 64 #if ERRATA_X4_2726228 65 case EXTRACT_PARTNUM(CORTEX_X4_MIDR): 66 return check_erratum_cortex_x4_2726228(cpu_get_rev_var()) == ERRATA_APPLIES; 67 #endif 68 #if ERRATA_A510_2971420 69 case EXTRACT_PARTNUM(CORTEX_A510_MIDR): 70 return check_erratum_cortex_a510_2971420(cpu_get_rev_var()) == ERRATA_APPLIES; 71 #endif 72 default: 73 break; 74 } 75 return false; 76 } 77 78 #if ERRATA_A75_764081 79 bool errata_a75_764081_applies(void) 80 { 81 long rev_var = cpu_get_rev_var(); 82 if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) { 83 return true; 84 } 85 return false; 86 } 87 #endif /* ERRATA_A75_764081 */ 88 89 bool errata_ich_vmcr_el2_applies(void) 90 { 91 switch (EXTRACT_PARTNUM(read_midr())) { 92 #if ERRATA_A710_3701772 93 case EXTRACT_PARTNUM(CORTEX_A710_MIDR): 94 if (check_erratum_cortex_a710_3701772(cpu_get_rev_var()) == ERRATA_APPLIES) 95 return true; 96 break; 97 #endif /* ERRATA_A710_3701772 */ 98 99 #if ERRATA_A715_3699560 100 case EXTRACT_PARTNUM(CORTEX_A715_MIDR): 101 if (check_erratum_cortex_a715_3699560(cpu_get_rev_var()) == ERRATA_APPLIES) 102 return true; 103 break; 104 #endif /* ERRATA_A715_3699560 */ 105 106 #if ERRATA_A720_3699561 107 case EXTRACT_PARTNUM(CORTEX_A720_MIDR): 108 if (check_erratum_cortex_a720_3699561(cpu_get_rev_var()) == ERRATA_APPLIES) 109 return true;; 110 break; 111 #endif /* ERRATA_A720_3699561 */ 112 113 #if ERRATA_A720_AE_3699562 114 case EXTRACT_PARTNUM(CORTEX_A720_AE_MIDR): 115 if (check_erratum_cortex_a720_ae_3699562(cpu_get_rev_var()) == ERRATA_APPLIES) 116 return true; 117 break; 118 #endif /* ERRATA_A720_AE_3699562 */ 119 120 #if ERRATA_A725_3699564 121 case EXTRACT_PARTNUM(CORTEX_A725_MIDR): 122 if (check_erratum_cortex_a725_3699564(cpu_get_rev_var()) == ERRATA_APPLIES) 123 return true; 124 break; 125 #endif /* ERRATA_A725_3699564 */ 126 127 #if ERRATA_X2_3701772 128 case EXTRACT_PARTNUM(CORTEX_X2_MIDR): 129 if (check_erratum_cortex_x2_3701772(cpu_get_rev_var()) == ERRATA_APPLIES) 130 return true; 131 break; 132 #endif /* ERRATA_X2_3701772 */ 133 134 #if ERRATA_X3_3701769 135 case EXTRACT_PARTNUM(CORTEX_X3_MIDR): 136 if (check_erratum_cortex_x3_3701769(cpu_get_rev_var()) == ERRATA_APPLIES) 137 return true; 138 break; 139 #endif /* ERRATA_X3_3701769 */ 140 141 #if ERRATA_X4_3701758 142 case EXTRACT_PARTNUM(CORTEX_X4_MIDR): 143 if (check_erratum_cortex_x4_3701758(cpu_get_rev_var()) == ERRATA_APPLIES) 144 return true; 145 break; 146 #endif /* ERRATA_X4_3701758 */ 147 148 #if ERRATA_X925_3701747 149 case EXTRACT_PARTNUM(CORTEX_X925_MIDR): 150 if (check_erratum_cortex_x925_3701747(cpu_get_rev_var()) == ERRATA_APPLIES) 151 return true; 152 break; 153 #endif /* ERRATA_X925_3701747 */ 154 155 #if ERRATA_N2_3701773 156 case EXTRACT_PARTNUM(NEOVERSE_N2_MIDR): 157 if (check_erratum_neoverse_n2_3701773(cpu_get_rev_var()) == ERRATA_APPLIES) 158 return true; 159 break; 160 #endif /* ERRATA_N2_3701773 */ 161 162 #if ERRATA_N3_3699563 163 case EXTRACT_PARTNUM(NEOVERSE_N3_MIDR): 164 if (check_erratum_neoverse_n3_3699563(cpu_get_rev_var()) == ERRATA_APPLIES) 165 return true; 166 break; 167 #endif /* ERRATA_N3_3699563 */ 168 169 #if ERRATA_V2_3701771 170 case EXTRACT_PARTNUM(NEOVERSE_V2_MIDR): 171 if (check_erratum_neoverse_v2_3701771(cpu_get_rev_var()) == ERRATA_APPLIES) 172 return true; 173 break; 174 #endif /* ERRATA_V2_3701771 */ 175 176 #if ERRATA_V3_3701767 177 case EXTRACT_PARTNUM(NEOVERSE_V3_MIDR): 178 if (check_erratum_neoverse_v3_3701767(cpu_get_rev_var()) == ERRATA_APPLIES) 179 return true; 180 break; 181 #endif /* ERRATA_V3_3701767 */ 182 183 default: 184 break; 185 } 186 187 return false; 188 } 189 190 int check_erratum_applies(uint32_t cve, int errata_id) 191 { 192 struct erratum_entry *entry; 193 long rev_var; 194 195 rev_var = cpu_get_rev_var(); 196 197 entry = find_erratum_entry(errata_id); 198 199 if (entry == NULL) { 200 return ERRATA_NOT_APPLIES; 201 } 202 203 assert(entry->cve == cve); 204 205 return entry->check_func(rev_var); 206 } 207