1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLAT_ARM_H 7 #define PLAT_ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 12 #include <common/desc_image_load.h> 13 #include <drivers/arm/gic.h> 14 #include <drivers/arm/tzc_common.h> 15 #include <lib/bakery_lock.h> 16 #include <lib/cassert.h> 17 #include <lib/el3_runtime/cpu_data.h> 18 #include <lib/gpt_rme/gpt_rme.h> 19 #include <lib/spinlock.h> 20 #include <lib/utils_def.h> 21 #include <lib/xlat_tables/xlat_tables_compat.h> 22 #if TRANSFER_LIST 23 #include <transfer_list.h> 24 #endif 25 26 /******************************************************************************* 27 * Forward declarations 28 ******************************************************************************/ 29 struct meminfo; 30 struct image_info; 31 struct bl_params; 32 33 typedef struct arm_tzc_regions_info { 34 unsigned long long base; 35 unsigned long long end; 36 unsigned int sec_attr; 37 unsigned int nsaid_permissions; 38 } arm_tzc_regions_info_t; 39 40 typedef struct arm_gpt_info { 41 pas_region_t *pas_region_base; 42 unsigned int pas_region_count; 43 uintptr_t l0_base; 44 uintptr_t l1_base; 45 size_t l0_size; 46 size_t l1_size; 47 gpccr_pps_e pps; 48 gpccr_pgs_e pgs; 49 } arm_gpt_info_t; 50 51 /******************************************************************************* 52 * Default mapping definition of the TrustZone Controller for ARM standard 53 * platforms. 54 * Configure: 55 * - Region 0 with no access; 56 * - Region 1 with secure access only; 57 * - the remaining DRAM regions access from the given Non-Secure masters. 58 ******************************************************************************/ 59 60 #if ENABLE_RME 61 #define ARM_TZC_RME_REGIONS_DEF \ 62 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ 63 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ 64 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 65 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 66 /* Realm and Shared area share the same PAS */ \ 67 {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 68 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 69 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 70 PLAT_ARM_TZC_NS_DEV_ACCESS} 71 #endif 72 73 #if ENABLE_RME 74 #if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 75 MEASURED_BOOT 76 #define ARM_TZC_REGIONS_DEF \ 77 ARM_TZC_RME_REGIONS_DEF, \ 78 {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \ 79 TZC_REGION_S_RDWR, 0} 80 #else 81 #define ARM_TZC_REGIONS_DEF \ 82 ARM_TZC_RME_REGIONS_DEF 83 #endif 84 85 #else 86 #define ARM_TZC_REGIONS_DEF \ 87 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 88 TZC_REGION_S_RDWR, 0}, \ 89 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 90 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 91 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 92 PLAT_ARM_TZC_NS_DEV_ACCESS} 93 #endif 94 95 #define ARM_CASSERT_MMAP \ 96 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 97 assert_plat_arm_mmap_mismatch); \ 98 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 99 <= MAX_MMAP_REGIONS, \ 100 assert_max_mmap_regions); 101 102 void arm_setup_romlib(void); 103 104 #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) 105 /* 106 * Use this macro to instantiate lock before it is used in below 107 * arm_lock_xxx() macros 108 */ 109 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 110 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 111 112 #if !HW_ASSISTED_COHERENCY 113 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 114 #else 115 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 116 #endif 117 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 118 119 /* 120 * These are wrapper macros to the Coherent Memory Bakery Lock API. 121 */ 122 #define arm_lock_init() bakery_lock_init(&arm_lock) 123 #define arm_lock_get() bakery_lock_get(&arm_lock) 124 #define arm_lock_release() bakery_lock_release(&arm_lock) 125 126 #else 127 128 /* 129 * Empty macros for all other BL stages other than BL31 and BL32 130 */ 131 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 132 #define ARM_LOCK_GET_INSTANCE 0 133 #define arm_lock_init() 134 #define arm_lock_get() 135 #define arm_lock_release() 136 137 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ 138 139 #ifdef __aarch64__ 140 #define TL_TAG_EXEC_EP_INFO TL_TAG_EXEC_EP_INFO64 141 #define TL_TAG_SRAM_LAYOUT TL_TAG_SRAM_LAYOUT64 142 #else 143 #define TL_TAG_EXEC_EP_INFO TL_TAG_EXEC_EP_INFO32 144 #define TL_TAG_SRAM_LAYOUT TL_TAG_SRAM_LAYOUT32 145 #endif 146 147 #if ARM_RECOM_STATE_ID_ENC 148 /* 149 * Macros used to parse state information from State-ID if it is using the 150 * recommended encoding for State-ID. 151 */ 152 #define ARM_LOCAL_PSTATE_WIDTH 4 153 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 154 155 /* Last in Level for the OS-initiated */ 156 #define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \ 157 (ARM_LOCAL_PSTATE_WIDTH * \ 158 (PLAT_MAX_PWR_LVL + 1))) 159 160 /* Macros to construct the composite power state */ 161 162 /* Make composite power state parameter till power level 0 */ 163 #if PSCI_EXTENDED_STATE_ID 164 165 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 166 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 167 #else 168 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 169 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 170 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 171 ((type) << PSTATE_TYPE_SHIFT)) 172 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 173 174 /* Make composite power state parameter till power level 1 */ 175 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 176 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 177 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 178 179 /* Make composite power state parameter till power level 2 */ 180 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 181 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 182 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 183 184 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 185 186 /* ARM State switch error codes */ 187 #define STATE_SW_E_PARAM (-2) 188 #define STATE_SW_E_DENIED (-3) 189 190 /* plat_get_rotpk_info() flags */ 191 #define ARM_ROTPK_REGS_ID 1 192 #define ARM_ROTPK_DEVEL_RSA_ID 2 193 #define ARM_ROTPK_DEVEL_ECDSA_ID 3 194 #define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4 195 #define ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID 5 196 197 #define ARM_USE_DEVEL_ROTPK \ 198 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ 199 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ 200 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \ 201 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID) 202 203 /* IO storage utility functions */ 204 int arm_io_setup(void); 205 206 /* Set image specification in IO block policy */ 207 int arm_set_image_source(unsigned int image_id, const char *part_name, 208 uintptr_t *dev_handle, uintptr_t *image_spec); 209 void arm_set_fip_addr(uint32_t active_fw_bank_idx); 210 211 /* Security utility functions */ 212 void arm_tzc400_setup(uintptr_t tzc_base, 213 const arm_tzc_regions_info_t *tzc_regions); 214 struct tzc_dmc500_driver_data; 215 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 216 const arm_tzc_regions_info_t *tzc_regions); 217 218 /* Console utility functions */ 219 void arm_console_boot_init(void); 220 void arm_console_boot_end(void); 221 void arm_console_runtime_init(void); 222 void arm_console_runtime_end(void); 223 224 /* Systimer utility function */ 225 void arm_configure_sys_timer(void); 226 227 /* PM utility functions */ 228 int arm_validate_power_state(unsigned int power_state, 229 psci_power_state_t *req_state); 230 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 231 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 232 void arm_system_pwr_domain_save(void); 233 void arm_system_pwr_domain_resume(void); 234 int arm_psci_read_mem_protect(int *enabled); 235 int arm_nor_psci_write_mem_protect(int val); 236 void arm_nor_psci_do_static_mem_protect(void); 237 void arm_nor_psci_do_dyn_mem_protect(void); 238 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 239 240 /* Topology utility function */ 241 int arm_check_mpidr(u_register_t mpidr); 242 243 /* BL1 utility functions */ 244 void arm_bl1_early_platform_setup(void); 245 void arm_bl1_platform_setup(void); 246 void arm_bl1_plat_arch_setup(void); 247 248 /* BL2 utility functions */ 249 void arm_bl2_early_platform_setup(u_register_t arg0, u_register_t arg1, 250 u_register_t arg2, u_register_t arg3); 251 void arm_bl2_platform_setup(void); 252 void arm_bl2_plat_arch_setup(void); 253 uint32_t arm_get_spsr(unsigned int image_id); 254 int arm_bl2_plat_handle_post_image_load(unsigned int image_id); 255 int arm_bl2_handle_post_image_load(unsigned int image_id); 256 struct bl_params *arm_get_next_bl_params(void); 257 void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node); 258 259 /* BL2 at EL3 functions */ 260 void arm_bl2_el3_early_platform_setup(void); 261 void arm_bl2_el3_plat_arch_setup(void); 262 #if ARM_FW_CONFIG_LOAD_ENABLE 263 void arm_bl2_el3_plat_config_load(void); 264 #endif /* ARM_FW_CONFIG_LOAD_ENABLE */ 265 266 /* BL2U utility functions */ 267 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 268 void *plat_info); 269 void arm_bl2u_platform_setup(void); 270 void arm_bl2u_plat_arch_setup(void); 271 272 /* BL31 utility functions */ 273 void arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1, 274 u_register_t arg2, u_register_t arg3); 275 void arm_bl31_platform_setup(void); 276 void arm_bl31_plat_runtime_setup(void); 277 void arm_bl31_plat_arch_setup(void); 278 279 /* Firmware Handoff utility functions */ 280 #if TRANSFER_LIST 281 void arm_transfer_list_dyn_cfg_init(struct transfer_list_header *secure_tl); 282 void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node, 283 struct transfer_list_header *secure_tl); 284 void arm_transfer_list_copy_hw_config(struct transfer_list_header *secure_tl, 285 struct transfer_list_header *ns_tl); 286 struct transfer_list_entry * 287 arm_transfer_list_set_heap_info(struct transfer_list_header *tl); 288 void arm_transfer_list_get_heap_info(void **heap_addr, size_t *heap_size); 289 #endif 290 291 /* TSP utility functions */ 292 void arm_tsp_early_platform_setup(u_register_t arg0, u_register_t arg1, 293 u_register_t arg2, u_register_t arg3); 294 295 /* SP_MIN utility functions */ 296 void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 297 u_register_t arg2, u_register_t arg3); 298 void arm_sp_min_plat_runtime_setup(void); 299 void arm_sp_min_plat_arch_setup(void); 300 301 /* FIP TOC validity check */ 302 bool arm_io_is_toc_valid(void); 303 304 /* Utility functions for Dynamic Config */ 305 306 void arm_bl1_set_mbedtls_heap(void); 307 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 308 309 #if IMAGE_BL2 310 void arm_bl2_dyn_cfg_init(void); 311 #endif /* IMAGE_BL2 */ 312 313 #if MEASURED_BOOT 314 #if DICE_PROTECTION_ENVIRONMENT 315 int arm_set_nt_fw_info(int *ctx_handle); 316 int arm_set_tb_fw_info(int *ctx_handle); 317 int arm_get_tb_fw_info(int *ctx_handle); 318 #else 319 /* Specific to event log backend */ 320 int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); 321 int arm_set_nt_fw_info( 322 /* 323 * Currently OP-TEE does not support reading DTBs from Secure memory 324 * and this option should be removed when feature is supported. 325 */ 326 #ifdef SPD_opteed 327 uintptr_t log_addr, 328 #endif 329 size_t log_size, uintptr_t *ns_log_addr); 330 int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size, 331 size_t log_max_size); 332 int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size, 333 size_t *log_max_size); 334 #endif /* DICE_PROTECTION_ENVIRONMENT */ 335 #endif /* MEASURED_BOOT */ 336 337 /* 338 * Free the memory storing initialization code only used during an images boot 339 * time so it can be reclaimed for runtime data 340 */ 341 void arm_free_init_memory(void); 342 343 /* 344 * Make the higher level translation tables read-only 345 */ 346 void arm_xlat_make_tables_readonly(void); 347 348 /* 349 * Mandatory functions required in ARM standard platforms 350 */ 351 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 352 353 /* should not be used, but keep for compatibility */ 354 #if USE_GIC_DRIVER == 0 355 void plat_arm_gic_driver_init(void); 356 void plat_arm_gic_init(void); 357 void plat_arm_gic_cpuif_enable(void); 358 void plat_arm_gic_cpuif_disable(void); 359 void plat_arm_gic_redistif_on(void); 360 void plat_arm_gic_redistif_off(void); 361 void plat_arm_gic_pcpu_init(void); 362 void plat_arm_gic_save(void); 363 void plat_arm_gic_resume(void); 364 #elif USE_GIC_DRIVER == 3 365 extern uintptr_t arm_gicr_base_addrs[]; 366 #endif 367 void plat_arm_security_setup(void); 368 void plat_arm_pwrc_setup(void); 369 #if !HW_ASSISTED_COHERENCY 370 void plat_arm_interconnect_init(void); 371 void plat_arm_interconnect_enter_coherency(void); 372 void plat_arm_interconnect_exit_coherency(void); 373 #endif /* HW_ASSISTED_COHERENCY */ 374 void plat_arm_program_trusted_mailbox(uintptr_t address); 375 bool plat_arm_bl1_fwu_needed(void); 376 int plat_arm_ni_setup(uintptr_t global_cfg); 377 __dead2 void plat_arm_error_handler(int err); 378 379 /* 380 * Optional functions in ARM standard platforms 381 */ 382 void gic_set_gicr_frames(const uintptr_t *plat_gicr_frames); 383 int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, 384 unsigned int *flags); 385 int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, 386 unsigned int *flags); 387 int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, 388 unsigned int *flags); 389 int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, 390 unsigned int *flags); 391 392 #if ARM_PLAT_MT 393 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 394 #endif 395 396 unsigned int plat_cluster_id_by_mpidr(u_register_t mpidr); 397 398 /* 399 * This function is called after loading SCP_BL2 image and it is used to perform 400 * any platform-specific actions required to handle the SCP firmware. 401 */ 402 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 403 404 /* 405 * Optional functions required in ARM standard platforms 406 */ 407 void plat_arm_io_setup(void); 408 int plat_arm_get_alt_image_source( 409 unsigned int image_id, 410 uintptr_t *dev_handle, 411 uintptr_t *image_spec); 412 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 413 const mmap_region_t *plat_arm_get_mmap(void); 414 415 const arm_gpt_info_t *plat_arm_get_gpt_info(void); 416 void arm_gpt_setup(void); 417 418 /* Allow platform to override psci_pm_ops during runtime */ 419 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 420 421 /* Execution state switch in ARM platforms */ 422 int arm_execution_state_switch(unsigned int smc_fid, 423 uint32_t pc_hi, 424 uint32_t pc_lo, 425 uint32_t cookie_hi, 426 uint32_t cookie_lo, 427 void *handle); 428 429 /* Optional functions for SP_MIN */ 430 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 431 u_register_t arg2, u_register_t arg3); 432 433 /* global variables */ 434 extern plat_psci_ops_t plat_arm_psci_pm_ops; 435 extern const mmap_region_t plat_arm_mmap[]; 436 extern const unsigned int arm_pm_idle_states[]; 437 extern struct transfer_list_header *secure_tl; 438 439 /* secure watchdog */ 440 void plat_arm_secure_wdt_start(void); 441 void plat_arm_secure_wdt_stop(void); 442 void plat_arm_secure_wdt_refresh(void); 443 444 /* Get SOC-ID of ARM platform */ 445 uint32_t plat_arm_get_soc_id(void); 446 447 #endif /* PLAT_ARM_H */ 448