1/* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <assert_macros.S> 10#include <context.h> 11#include <el3_common_macros.S> 12#include <platform_def.h> 13 14#if CTX_INCLUDE_FPREGS 15 .global fpregs_context_save 16 .global fpregs_context_restore 17#endif /* CTX_INCLUDE_FPREGS */ 18 19#if CTX_INCLUDE_SVE_REGS 20 .global sve_context_save 21 .global sve_context_restore 22#endif /* CTX_INCLUDE_SVE_REGS */ 23 24#if ERRATA_SPECULATIVE_AT 25 .global save_and_update_ptw_el1_sys_regs 26#endif /* ERRATA_SPECULATIVE_AT */ 27 28 .global prepare_el3_entry 29 .global restore_gp_pmcr_pauth_regs 30 .global el3_exit 31 32/* Following macros will be used if any of CTX_INCLUDE_FPREGS or CTX_INCLUDE_SVE_REGS is enabled */ 33#if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 34.macro fpregs_state_save base:req hold:req 35 mrs \hold, fpsr 36 str \hold, [\base, #CTX_SIMD_FPSR] 37 38 mrs \hold, fpcr 39 str \hold, [\base, #CTX_SIMD_FPCR] 40 41#if CTX_INCLUDE_AARCH32_REGS && CTX_INCLUDE_FPREGS 42 mrs \hold, fpexc32_el2 43 str \hold, [\base, #CTX_SIMD_FPEXC32] 44#endif 45.endm 46 47.macro fpregs_state_restore base:req hold:req 48 ldr \hold, [\base, #CTX_SIMD_FPSR] 49 msr fpsr, \hold 50 51 ldr \hold, [\base, #CTX_SIMD_FPCR] 52 msr fpcr, \hold 53 54#if CTX_INCLUDE_AARCH32_REGS && CTX_INCLUDE_FPREGS 55 ldr \hold, [\base, #CTX_SIMD_FPEXC32] 56 msr fpexc32_el2, \hold 57#endif 58.endm 59 60#endif /* CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS */ 61 62/* ------------------------------------------------------------------ 63 * The following function follows the aapcs_64 strictly to use 64 * x9-x17 (temporary caller-saved registers according to AArch64 PCS) 65 * to save floating point register context. It assumes that 'x0' is 66 * pointing to a 'fp_regs' structure where the register context will 67 * be saved. 68 * 69 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 70 * However currently we don't use VFP registers nor set traps in 71 * Trusted Firmware, and assume it's cleared. 72 * 73 * TODO: Revisit when VFP is used in secure world 74 * ------------------------------------------------------------------ 75 */ 76#if CTX_INCLUDE_FPREGS 77func fpregs_context_save 78.arch_extension fp 79 /* Temporarily enable floating point */ 80 81 /* Save x0 and pass its original value to fpregs_state_save */ 82 mov x1, x0 83 84 stp q0, q1, [x0], #32 85 stp q2, q3, [x0], #32 86 stp q4, q5, [x0], #32 87 stp q6, q7, [x0], #32 88 stp q8, q9, [x0], #32 89 stp q10, q11, [x0], #32 90 stp q12, q13, [x0], #32 91 stp q14, q15, [x0], #32 92 stp q16, q17, [x0], #32 93 stp q18, q19, [x0], #32 94 stp q20, q21, [x0], #32 95 stp q22, q23, [x0], #32 96 stp q24, q25, [x0], #32 97 stp q26, q27, [x0], #32 98 stp q28, q29, [x0], #32 99 stp q30, q31, [x0], #32 100 101 fpregs_state_save x1, x9 102 103.arch_extension nofp 104 ret 105endfunc fpregs_context_save 106 107/* ------------------------------------------------------------------ 108 * The following function follows the aapcs_64 strictly to use x9-x17 109 * (temporary caller-saved registers according to AArch64 PCS) to 110 * restore floating point register context. It assumes that 'x0' is 111 * pointing to a 'fp_regs' structure from where the register context 112 * will be restored. 113 * 114 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 115 * However currently we don't use VFP registers nor set traps in 116 * Trusted Firmware, and assume it's cleared. 117 * 118 * TODO: Revisit when VFP is used in secure world 119 * ------------------------------------------------------------------ 120 */ 121func fpregs_context_restore 122.arch_extension fp 123 /* Temporarily enable floating point */ 124 125 /* Save x0 and pass its original value to fpregs_state_restore */ 126 mov x1, x0 127 128 ldp q0, q1, [x0], #32 129 ldp q2, q3, [x0], #32 130 ldp q4, q5, [x0], #32 131 ldp q6, q7, [x0], #32 132 ldp q8, q9, [x0], #32 133 ldp q10, q11, [x0], #32 134 ldp q12, q13, [x0], #32 135 ldp q14, q15, [x0], #32 136 ldp q16, q17, [x0], #32 137 ldp q18, q19, [x0], #32 138 ldp q20, q21, [x0], #32 139 ldp q22, q23, [x0], #32 140 ldp q24, q25, [x0], #32 141 ldp q26, q27, [x0], #32 142 ldp q28, q29, [x0], #32 143 ldp q30, q31, [x0], #32 144 145 fpregs_state_restore x1, x9 146 147.arch_extension nofp 148 ret 149endfunc fpregs_context_restore 150#endif /* CTX_INCLUDE_FPREGS */ 151 152#if CTX_INCLUDE_SVE_REGS 153/* 154 * Helper macros for SVE predicates save/restore operations. 155 */ 156.macro sve_predicate_op op:req reg:req 157 \op p0, [\reg, #0, MUL VL] 158 \op p1, [\reg, #1, MUL VL] 159 \op p2, [\reg, #2, MUL VL] 160 \op p3, [\reg, #3, MUL VL] 161 \op p4, [\reg, #4, MUL VL] 162 \op p5, [\reg, #5, MUL VL] 163 \op p6, [\reg, #6, MUL VL] 164 \op p7, [\reg, #7, MUL VL] 165 \op p8, [\reg, #8, MUL VL] 166 \op p9, [\reg, #9, MUL VL] 167 \op p10, [\reg, #10, MUL VL] 168 \op p11, [\reg, #11, MUL VL] 169 \op p12, [\reg, #12, MUL VL] 170 \op p13, [\reg, #13, MUL VL] 171 \op p14, [\reg, #14, MUL VL] 172 \op p15, [\reg, #15, MUL VL] 173.endm 174 175.macro sve_vectors_op op:req reg:req 176 \op z0, [\reg, #0, MUL VL] 177 \op z1, [\reg, #1, MUL VL] 178 \op z2, [\reg, #2, MUL VL] 179 \op z3, [\reg, #3, MUL VL] 180 \op z4, [\reg, #4, MUL VL] 181 \op z5, [\reg, #5, MUL VL] 182 \op z6, [\reg, #6, MUL VL] 183 \op z7, [\reg, #7, MUL VL] 184 \op z8, [\reg, #8, MUL VL] 185 \op z9, [\reg, #9, MUL VL] 186 \op z10, [\reg, #10, MUL VL] 187 \op z11, [\reg, #11, MUL VL] 188 \op z12, [\reg, #12, MUL VL] 189 \op z13, [\reg, #13, MUL VL] 190 \op z14, [\reg, #14, MUL VL] 191 \op z15, [\reg, #15, MUL VL] 192 \op z16, [\reg, #16, MUL VL] 193 \op z17, [\reg, #17, MUL VL] 194 \op z18, [\reg, #18, MUL VL] 195 \op z19, [\reg, #19, MUL VL] 196 \op z20, [\reg, #20, MUL VL] 197 \op z21, [\reg, #21, MUL VL] 198 \op z22, [\reg, #22, MUL VL] 199 \op z23, [\reg, #23, MUL VL] 200 \op z24, [\reg, #24, MUL VL] 201 \op z25, [\reg, #25, MUL VL] 202 \op z26, [\reg, #26, MUL VL] 203 \op z27, [\reg, #27, MUL VL] 204 \op z28, [\reg, #28, MUL VL] 205 \op z29, [\reg, #29, MUL VL] 206 \op z30, [\reg, #30, MUL VL] 207 \op z31, [\reg, #31, MUL VL] 208.endm 209 210/* ------------------------------------------------------------------ 211 * The following function follows the aapcs_64 strictly to use x9-x17 212 * (temporary caller-saved registers according to AArch64 PCS) to 213 * restore SVE register context. It assumes that 'x0' is 214 * pointing to a 'sve_regs_t' structure to which the register context 215 * will be saved. 216 * ------------------------------------------------------------------ 217 */ 218func sve_context_save 219.arch_extension sve 220 /* Predicate registers */ 221 mov x13, #CTX_SIMD_PREDICATES 222 add x9, x0, x13 223 sve_predicate_op str, x9 224 225 /* Save FFR after predicates */ 226 mov x13, #CTX_SIMD_FFR 227 add x9, x0, x13 228 rdffr p0.b 229 str p0, [x9] 230 231 /* Save vector registers */ 232 mov x13, #CTX_SIMD_VECTORS 233 add x9, x0, x13 234 sve_vectors_op str, x9 235.arch_extension nosve 236 237 /* Save FPSR, FPCR and FPEXC32 */ 238 fpregs_state_save x0, x9 239 240 ret 241endfunc sve_context_save 242 243/* ------------------------------------------------------------------ 244 * The following function follows the aapcs_64 strictly to use x9-x17 245 * (temporary caller-saved registers according to AArch64 PCS) to 246 * restore SVE register context. It assumes that 'x0' is pointing to 247 * a 'sve_regs_t' structure from where the register context will be 248 * restored. 249 * ------------------------------------------------------------------ 250 */ 251func sve_context_restore 252.arch_extension sve 253 /* Restore FFR register before predicates */ 254 mov x13, #CTX_SIMD_FFR 255 add x9, x0, x13 256 ldr p0, [x9] 257 wrffr p0.b 258 259 /* Restore predicate registers */ 260 mov x13, #CTX_SIMD_PREDICATES 261 add x9, x0, x13 262 sve_predicate_op ldr, x9 263 264 /* Restore vector registers */ 265 mov x13, #CTX_SIMD_VECTORS 266 add x9, x0, x13 267 sve_vectors_op ldr, x9 268.arch_extension nosve 269 270 /* Restore FPSR, FPCR and FPEXC32 */ 271 fpregs_state_restore x0, x9 272 ret 273endfunc sve_context_restore 274#endif /* CTX_INCLUDE_SVE_REGS */ 275 276 /* 277 * Set the PSTATE bits not set when the exception was taken as 278 * described in the AArch64.TakeException() pseudocode function 279 * in ARM DDI 0487F.c page J1-7635 to a default value. 280 */ 281 .macro set_unset_pstate_bits 282 /* 283 * If Data Independent Timing (DIT) functionality is implemented, 284 * always enable DIT in EL3 285 */ 286#if ENABLE_FEAT_DIT 287#if ENABLE_FEAT_DIT >= 2 288 mrs x8, id_aa64pfr0_el1 289 and x8, x8, #(ID_AA64PFR0_DIT_MASK << ID_AA64PFR0_DIT_SHIFT) 290 cbz x8, 1f 291#endif 292 mov x8, #DIT_BIT 293 msr DIT, x8 2941: 295#endif /* ENABLE_FEAT_DIT */ 296 .endm /* set_unset_pstate_bits */ 297 298/*------------------------------------------------------------------------- 299 * This macro checks the ENABLE_FEAT_MPAM state, performs ID register 300 * check to see if the platform supports MPAM extension and restores MPAM3 301 * register value if it is FEAT_STATE_ENABLED/FEAT_STATE_CHECKED. 302 * 303 * This is particularly more complicated because we can't check 304 * if the platform supports MPAM by looking for status of a particular bit 305 * in the MDCR_EL3 or CPTR_EL3 register like other extensions. 306 * ------------------------------------------------------------------------ 307 */ 308 309 .macro restore_mpam3_el3 310#if ENABLE_FEAT_MPAM 311#if ENABLE_FEAT_MPAM >= 2 312 mrs x8, id_aa64pfr0_el1 313 lsr x8, x8, #(ID_AA64PFR0_MPAM_SHIFT) 314 and x8, x8, #(ID_AA64PFR0_MPAM_MASK) 315 mrs x7, id_aa64pfr1_el1 316 lsr x7, x7, #(ID_AA64PFR1_MPAM_FRAC_SHIFT) 317 and x7, x7, #(ID_AA64PFR1_MPAM_FRAC_MASK) 318 orr x7, x7, x8 319 cbz x7, no_mpam 320#endif 321 /* ----------------------------------------------------------- 322 * Restore MPAM3_EL3 register as per context state 323 * Currently we only enable MPAM for NS world and trap to EL3 324 * for MPAM access in lower ELs of Secure and Realm world 325 * x9 holds address of the per_world context 326 * ----------------------------------------------------------- 327 */ 328 329 ldr x17, [x9, #CTX_MPAM3_EL3] 330 msr S3_6_C10_C5_0, x17 /* mpam3_el3 */ 331 332no_mpam: 333#endif 334 .endm /* restore_mpam3_el3 */ 335 336/* ------------------------------------------------------------------ 337 * The following macro is used to save all the general purpose 338 * registers and swap the FEAT_PAUTH keys with BL31's keys in 339 * cpu_data. It also checks if the Secure Cycle Counter (PMCCNTR_EL0) 340 * is disabled in EL3/Secure (ARMv8.5-PMU), wherein PMCCNTR_EL0 needs 341 * not to be saved/restored during world switch. 342 * 343 * Ideally we would only save and restore the callee saved registers 344 * when a world switch occurs but that type of implementation is more 345 * complex. So currently we will always save and restore these 346 * registers on entry and exit of EL3. 347 * clobbers: x18 348 * ------------------------------------------------------------------ 349 */ 350 .macro save_gp_pmcr_pauth_regs 351 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 352 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 353 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 354 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 355 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 356 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 357 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 358 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 359 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 360 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 361 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 362 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 363 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 364 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 365 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 366 mrs x18, sp_el0 367 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 368 369 /* PMUv3 is presumed to be always present */ 370 mrs x9, pmcr_el0 371 str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 372#if CTX_INCLUDE_PAUTH_REGS 373#if CTX_INCLUDE_PAUTH_REGS == 2 374 /* Skip if not present in hardware */ 375 is_feat_pauth_present_asm x9, x10 376 beq no_pauth_\@ 377#endif 378 /* ---------------------------------------------------------- 379 * Save the ARMv8.3-PAuth keys as they are not banked 380 * by exception level 381 * ---------------------------------------------------------- 382 */ 383 add x19, sp, #CTX_PAUTH_REGS_OFFSET 384 385 mrs x20, APIAKeyLo_EL1 /* x21:x20 = APIAKey */ 386 mrs x21, APIAKeyHi_EL1 387 mrs x22, APIBKeyLo_EL1 /* x23:x22 = APIBKey */ 388 mrs x23, APIBKeyHi_EL1 389 mrs x24, APDAKeyLo_EL1 /* x25:x24 = APDAKey */ 390 mrs x25, APDAKeyHi_EL1 391 mrs x26, APDBKeyLo_EL1 /* x27:x26 = APDBKey */ 392 mrs x27, APDBKeyHi_EL1 393 mrs x28, APGAKeyLo_EL1 /* x29:x28 = APGAKey */ 394 mrs x29, APGAKeyHi_EL1 395 396 stp x20, x21, [x19, #CTX_PACIAKEY_LO] 397 stp x22, x23, [x19, #CTX_PACIBKEY_LO] 398 stp x24, x25, [x19, #CTX_PACDAKEY_LO] 399 stp x26, x27, [x19, #CTX_PACDBKEY_LO] 400 stp x28, x29, [x19, #CTX_PACGAKEY_LO] 401#if ENABLE_PAUTH 402#if IMAGE_BL31 403 /* tpidr_el3 contains the address of the cpu_data structure */ 404 mrs x9, tpidr_el3 405 /* Load APIAKey from cpu_data */ 406 ldp x10, x11, [x9, #CPU_DATA_APIAKEY] 407#endif /* IMAGE_BL31 */ 408 409#if IMAGE_BL1 410 /* BL1 does not use cpu_data and has dedicated storage */ 411 adr_l x9, bl1_apiakey 412 ldp x10, x11, [x9] 413#endif /* IMAGE_BL1 */ 414 415 /* Program instruction key A */ 416 msr APIAKeyLo_EL1, x10 417 msr APIAKeyHi_EL1, x11 418no_pauth_\@: 419#endif /* ENABLE_PAUTH */ 420#endif /* CTX_INCLUDE_PAUTH_REGS */ 421 .endm /* save_gp_pmcr_pauth_regs */ 422 423/* ----------------------------------------------------------------- 424 * This function saves the context and sets the PSTATE to a known 425 * state, preparing entry to el3. 426 * Save all the general purpose and ARMv8.3-PAuth (if enabled) 427 * registers. 428 * Then set any of the PSTATE bits that are not set by hardware 429 * according to the Aarch64.TakeException pseudocode in the Arm 430 * Architecture Reference Manual to a default value for EL3. 431 * clobbers: x17 432 * ----------------------------------------------------------------- 433 */ 434func prepare_el3_entry 435 /* 436 * context is about to mutate, so make sure we don't affect any still 437 * in-flight profiling operations. We don't care that they actually 438 * finish, that can still be later. NOP if not present 439 */ 440#if ENABLE_SPE_FOR_NS 441 psb_csync 442#endif 443#if ENABLE_TRBE_FOR_NS 444 tsb_csync 445#endif 446 isb 447 save_gp_pmcr_pauth_regs 448 setup_el3_execution_context 449 ret 450endfunc prepare_el3_entry 451 452/* ------------------------------------------------------------------ 453 * This function restores ARMv8.3-PAuth (if enabled) and all general 454 * purpose registers except x30 from the CPU context. 455 * x30 register must be explicitly restored by the caller. 456 * ------------------------------------------------------------------ 457 */ 458func restore_gp_pmcr_pauth_regs 459#if CTX_INCLUDE_PAUTH_REGS 460#if CTX_INCLUDE_PAUTH_REGS == 2 461 /* Skip if not present in hardware */ 462 is_feat_pauth_present_asm x0, x1 463 beq no_pauth 464#endif 465 /* Restore the ARMv8.3 PAuth keys */ 466 add x10, sp, #CTX_PAUTH_REGS_OFFSET 467 468 ldp x0, x1, [x10, #CTX_PACIAKEY_LO] /* x1:x0 = APIAKey */ 469 ldp x2, x3, [x10, #CTX_PACIBKEY_LO] /* x3:x2 = APIBKey */ 470 ldp x4, x5, [x10, #CTX_PACDAKEY_LO] /* x5:x4 = APDAKey */ 471 ldp x6, x7, [x10, #CTX_PACDBKEY_LO] /* x7:x6 = APDBKey */ 472 ldp x8, x9, [x10, #CTX_PACGAKEY_LO] /* x9:x8 = APGAKey */ 473 474 msr APIAKeyLo_EL1, x0 475 msr APIAKeyHi_EL1, x1 476 msr APIBKeyLo_EL1, x2 477 msr APIBKeyHi_EL1, x3 478 msr APDAKeyLo_EL1, x4 479 msr APDAKeyHi_EL1, x5 480 msr APDBKeyLo_EL1, x6 481 msr APDBKeyHi_EL1, x7 482 msr APGAKeyLo_EL1, x8 483 msr APGAKeyHi_EL1, x9 484no_pauth: 485#endif /* CTX_INCLUDE_PAUTH_REGS */ 486 487 /* PMUv3 is presumed to be always present */ 488 ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 489 msr pmcr_el0, x0 490 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 491 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 492 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 493 ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 494 ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 495 ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 496 ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 497 ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 498 ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 499 ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 500 ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 501 ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 502 ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 503 ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 504 ldr x28, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 505 msr sp_el0, x28 506 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 507 ret 508endfunc restore_gp_pmcr_pauth_regs 509 510#if ERRATA_SPECULATIVE_AT 511/* -------------------------------------------------------------------- 512 * In case of ERRATA_SPECULATIVE_AT, save SCTLR_EL1 and TCR_EL1 513 * registers and update EL1 registers to disable stage1 and stage2 514 * page table walk. 515 * -------------------------------------------------------------------- 516 */ 517func save_and_update_ptw_el1_sys_regs 518 /* ---------------------------------------------------------- 519 * Save only sctlr_el1 and tcr_el1 registers 520 * ---------------------------------------------------------- 521 */ 522 mrs x29, sctlr_el1 523 str x29, [sp, #(CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1)] 524 mrs x29, tcr_el1 525 str x29, [sp, #(CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_TCR_EL1)] 526 527 /* ------------------------------------------------------------ 528 * Must follow below order in order to disable page table 529 * walk for lower ELs (EL1 and EL0). First step ensures that 530 * page table walk is disabled for stage1 and second step 531 * ensures that page table walker should use TCR_EL1.EPDx 532 * bits to perform address translation. ISB ensures that CPU 533 * does these 2 steps in order. 534 * 535 * 1. Update TCR_EL1.EPDx bits to disable page table walk by 536 * stage1. 537 * 2. Enable MMU bit to avoid identity mapping via stage2 538 * and force TCR_EL1.EPDx to be used by the page table 539 * walker. 540 * ------------------------------------------------------------ 541 */ 542 orr x29, x29, #(TCR_EPD0_BIT) 543 orr x29, x29, #(TCR_EPD1_BIT) 544 msr tcr_el1, x29 545 isb 546 mrs x29, sctlr_el1 547 orr x29, x29, #SCTLR_M_BIT 548 msr sctlr_el1, x29 549 isb 550 ret 551endfunc save_and_update_ptw_el1_sys_regs 552 553#endif /* ERRATA_SPECULATIVE_AT */ 554 555/* ----------------------------------------------------------------- 556* The below macro returns the address of the per_world context for 557* the security state, retrieved through "get_security_state" macro. 558* The per_world context address is returned in the register argument. 559* Clobbers: x9, x10 560* ------------------------------------------------------------------ 561*/ 562 563.macro get_per_world_context _reg:req 564 ldr x10, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 565 get_security_state x9, x10 566 mov_imm x10, (CTX_PERWORLD_EL3STATE_END - CTX_CPTR_EL3) 567 mul x9, x9, x10 568 adrp x10, per_world_context 569 add x10, x10, :lo12:per_world_context 570 add x9, x9, x10 571 mov \_reg, x9 572.endm 573 574/* ------------------------------------------------------------------ 575 * This routine assumes that the SP_EL3 is pointing to a valid 576 * context structure from where the gp regs and other special 577 * registers can be retrieved. 578 * ------------------------------------------------------------------ 579 */ 580func el3_exit 581#if ENABLE_ASSERTIONS 582 /* el3_exit assumes SP_EL0 on entry */ 583 mrs x17, spsel 584 cmp x17, #MODE_SP_EL0 585 ASM_ASSERT(eq) 586#endif /* ENABLE_ASSERTIONS */ 587 588 /* ---------------------------------------------------------- 589 * Save the current SP_EL0 i.e. the EL3 runtime stack which 590 * will be used for handling the next SMC. 591 * Then switch to SP_EL3. 592 * ---------------------------------------------------------- 593 */ 594 mov x17, sp 595 msr spsel, #MODE_SP_ELX 596 str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 597 598 /* ---------------------------------------------------------- 599 * Restore CPTR_EL3. 600 * ---------------------------------------------------------- */ 601 602 /* The address of the per_world context is stored in x9 */ 603 get_per_world_context x9 604 605 ldp x19, x20, [x9, #CTX_CPTR_EL3] 606 msr cptr_el3, x19 607 608#if IMAGE_BL31 609 restore_mpam3_el3 610 611#endif /* IMAGE_BL31 */ 612 613#if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 614 /* ---------------------------------------------------------- 615 * Restore mitigation state as it was on entry to EL3 616 * ---------------------------------------------------------- 617 */ 618 ldr x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE] 619 cbz x17, 1f 620 blr x17 6211: 622#endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */ 623 624#if IMAGE_BL31 625 synchronize_errors 626#endif /* IMAGE_BL31 */ 627 628 /* -------------------------------------------------------------- 629 * Restore MDCR_EL3, SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET 630 * -------------------------------------------------------------- 631 */ 632 ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 633 ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 634 ldr x19, [sp, #CTX_EL3STATE_OFFSET + CTX_MDCR_EL3] 635 msr spsr_el3, x16 636 msr elr_el3, x17 637 msr scr_el3, x18 638 msr mdcr_el3, x19 639 640 restore_ptw_el1_sys_regs 641 642 /* ---------------------------------------------------------- 643 * Restore general purpose (including x30), PMCR_EL0 and 644 * ARMv8.3-PAuth registers. 645 * Exit EL3 via ERET to a lower exception level. 646 * ---------------------------------------------------------- 647 */ 648 bl restore_gp_pmcr_pauth_regs 649 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 650 651#ifdef IMAGE_BL31 652 /* Clear the EL3 flag as we are exiting el3 */ 653 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] 654#endif /* IMAGE_BL31 */ 655 656 exception_return 657 658endfunc el3_exit 659