1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /**************************************************************** 8 * Auto generated by DE, please DO NOT modify this file directly. 9 ****************************************************************/ 10 11 #ifndef MT_SPM_REG_H 12 #define MT_SPM_REG_H 13 14 #include <pcm_def.h> 15 #include <sleep_def.h> 16 17 /************************************** 18 * Define and Declare 19 **************************************/ 20 21 #define POWERON_CONFIG_EN (SPM_BASE + 0x000) 22 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) 23 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) 24 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x00C) 25 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x010) 26 #define PCM_PWR_IO_EN (SPM_BASE + 0x014) 27 #define PCM_CON0 (SPM_BASE + 0x018) 28 #define PCM_CON1 (SPM_BASE + 0x01C) 29 #define SPM_SRAM_SLEEP_CTRL (SPM_BASE + 0x020) 30 #define SPM_CLK_CON (SPM_BASE + 0x024) 31 #define SPM_CLK_SETTLE (SPM_BASE + 0x028) 32 #define SPM_CLK_CON_1 (SPM_BASE + 0x02C) 33 #define SPM_SW_RST_CON (SPM_BASE + 0x040) 34 #define SPM_SW_RST_CON_SET (SPM_BASE + 0x044) 35 #define SPM_SW_RST_CON_CLR (SPM_BASE + 0x048) 36 #define R_SEC_READ_MASK (SPM_BASE + 0x050) 37 #define R_ONE_TIME_LOCK_L (SPM_BASE + 0x054) 38 #define R_ONE_TIME_LOCK_M (SPM_BASE + 0x058) 39 #define R_ONE_TIME_LOCK_H (SPM_BASE + 0x05C) 40 #define SSPM_CLK_CON (SPM_BASE + 0x084) 41 #define SCP_CLK_CON (SPM_BASE + 0x088) 42 #define SPM_SWINT (SPM_BASE + 0x090) 43 #define SPM_SWINT_SET (SPM_BASE + 0x094) 44 #define SPM_SWINT_CLR (SPM_BASE + 0x098) 45 #define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0) 46 #define SPM_IRQ_MASK (SPM_BASE + 0x0B4) 47 #define MD32PCM_SCU_CTRL0 (SPM_BASE + 0x100) 48 #define MD32PCM_SCU_CTRL1 (SPM_BASE + 0x104) 49 #define MD32PCM_SCU_CTRL2 (SPM_BASE + 0x108) 50 #define MD32PCM_SCU_CTRL3 (SPM_BASE + 0x10C) 51 #define MD32PCM_SCU_STA0 (SPM_BASE + 0x110) 52 #define SPM_IRQ_STA (SPM_BASE + 0x128) 53 #define MD32PCM_WAKEUP_STA (SPM_BASE + 0x130) 54 #define MD32PCM_EVENT_STA (SPM_BASE + 0x134) 55 #define SPM_WAKEUP_MISC (SPM_BASE + 0x140) 56 #define SPM_CK_STA (SPM_BASE + 0x164) 57 #define MD32PCM_STA (SPM_BASE + 0x190) 58 #define MD32PCM_PC (SPM_BASE + 0x194) 59 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x200) 60 #define CPU_WFI_EN (SPM_BASE + 0x204) 61 #define CPU_WFI_EN_SET (SPM_BASE + 0x208) 62 #define CPU_WFI_EN_CLR (SPM_BASE + 0x20C) 63 #define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x210) 64 #define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x214) 65 #define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x218) 66 #define MCUSYS_IDLE_STA (SPM_BASE + 0x21C) 67 #define CPU_PWR_STATUS (SPM_BASE + 0x220) 68 #define SW2SPM_WAKEUP (SPM_BASE + 0x224) 69 #define SW2SPM_WAKEUP_SET (SPM_BASE + 0x228) 70 #define SW2SPM_WAKEUP_CLR (SPM_BASE + 0x22C) 71 #define SW2SPM_MAILBOX_0 (SPM_BASE + 0x230) 72 #define SW2SPM_MAILBOX_1 (SPM_BASE + 0x234) 73 #define SW2SPM_MAILBOX_2 (SPM_BASE + 0x238) 74 #define SW2SPM_MAILBOX_3 (SPM_BASE + 0x23C) 75 #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x240) 76 #define SPM2SW_MAILBOX_1 (SPM_BASE + 0x244) 77 #define SPM2SW_MAILBOX_2 (SPM_BASE + 0x248) 78 #define SPM2SW_MAILBOX_3 (SPM_BASE + 0x24C) 79 #define SPM2MCUPM_CON (SPM_BASE + 0x250) 80 #define SPM_MCUSYS_PWR_CON (SPM_BASE + 0x260) 81 #define SPM_CPUTOP_PWR_CON (SPM_BASE + 0x264) 82 #define SPM_CPU0_PWR_CON (SPM_BASE + 0x268) 83 #define SPM_CPU1_PWR_CON (SPM_BASE + 0x26C) 84 #define SPM_CPU2_PWR_CON (SPM_BASE + 0x270) 85 #define SPM_CPU3_PWR_CON (SPM_BASE + 0x274) 86 #define SPM_CPU4_PWR_CON (SPM_BASE + 0x278) 87 #define SPM_CPU5_PWR_CON (SPM_BASE + 0x27C) 88 #define SPM_CPU6_PWR_CON (SPM_BASE + 0x280) 89 #define SPM_CPU7_PWR_CON (SPM_BASE + 0x284) 90 #define SPM_MCUPM_SPMC_CON (SPM_BASE + 0x288) 91 #define SPM_DPM_P2P_STA (SPM_BASE + 0x2A0) 92 #define SPM_DPM_P2P_CON (SPM_BASE + 0x2A4) 93 #define SPM_DPM_INTF_STA (SPM_BASE + 0x2A8) 94 #define SPM_DPM_WB_CON (SPM_BASE + 0x2AC) 95 #define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x2B0) 96 #define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x2B4) 97 #define SPM_PWRAP_CON (SPM_BASE + 0x300) 98 #define SPM_PWRAP_CON_STA (SPM_BASE + 0x304) 99 #define SPM_PMIC_SPMI_CON (SPM_BASE + 0x308) 100 #define SPM_PWRAP_CMD0 (SPM_BASE + 0x310) 101 #define SPM_PWRAP_CMD1 (SPM_BASE + 0x314) 102 #define SPM_PWRAP_CMD2 (SPM_BASE + 0x318) 103 #define SPM_PWRAP_CMD3 (SPM_BASE + 0x31C) 104 #define SPM_PWRAP_CMD4 (SPM_BASE + 0x320) 105 #define SPM_PWRAP_CMD5 (SPM_BASE + 0x324) 106 #define SPM_PWRAP_CMD6 (SPM_BASE + 0x328) 107 #define SPM_PWRAP_CMD7 (SPM_BASE + 0x32C) 108 #define SPM_PWRAP_CMD8 (SPM_BASE + 0x330) 109 #define SPM_PWRAP_CMD9 (SPM_BASE + 0x334) 110 #define SPM_PWRAP_CMD10 (SPM_BASE + 0x338) 111 #define SPM_PWRAP_CMD11 (SPM_BASE + 0x33C) 112 #define SPM_PWRAP_CMD12 (SPM_BASE + 0x340) 113 #define SPM_PWRAP_CMD13 (SPM_BASE + 0x344) 114 #define SPM_PWRAP_CMD14 (SPM_BASE + 0x348) 115 #define SPM_PWRAP_CMD15 (SPM_BASE + 0x34C) 116 #define SPM_PWRAP_CMD16 (SPM_BASE + 0x350) 117 #define SPM_PWRAP_CMD17 (SPM_BASE + 0x354) 118 #define SPM_PWRAP_CMD18 (SPM_BASE + 0x358) 119 #define SPM_PWRAP_CMD19 (SPM_BASE + 0x35C) 120 #define SPM_PWRAP_CMD20 (SPM_BASE + 0x360) 121 #define SPM_PWRAP_CMD21 (SPM_BASE + 0x364) 122 #define SPM_PWRAP_CMD22 (SPM_BASE + 0x368) 123 #define SPM_PWRAP_CMD23 (SPM_BASE + 0x36C) 124 #define SPM_PWRAP_CMD24 (SPM_BASE + 0x370) 125 #define SPM_PWRAP_CMD25 (SPM_BASE + 0x374) 126 #define SPM_PWRAP_CMD26 (SPM_BASE + 0x378) 127 #define SPM_PWRAP_CMD27 (SPM_BASE + 0x37C) 128 #define SPM_PWRAP_CMD28 (SPM_BASE + 0x380) 129 #define SPM_PWRAP_CMD29 (SPM_BASE + 0x384) 130 #define SPM_PWRAP_CMD30 (SPM_BASE + 0x388) 131 #define SPM_PWRAP_CMD31 (SPM_BASE + 0x38C) 132 #define DVFSRC_EVENT_STA (SPM_BASE + 0x390) 133 #define SPM_FORCE_DVFS (SPM_BASE + 0x394) 134 #define SPM_DVFS_STA (SPM_BASE + 0x398) 135 #define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x39C) 136 #define SPM_DVFS_LEVEL (SPM_BASE + 0x3A0) 137 #define SPM_DVFS_OPP (SPM_BASE + 0x3A4) 138 #define SPM_ULTRA_REQ (SPM_BASE + 0x3A8) 139 #define SPM_DVFS_CON (SPM_BASE + 0x3AC) 140 #define SPM_SRAMRC_CON (SPM_BASE + 0x3B0) 141 #define SPM_SRCLKENRC_CON (SPM_BASE + 0x3B4) 142 #define SPM_DPSW_CON (SPM_BASE + 0x3B8) 143 #define ULPOSC_CON (SPM_BASE + 0x400) 144 #define AP_MDSRC_REQ (SPM_BASE + 0x404) 145 #define SPM2MD_SWITCH_CTRL (SPM_BASE + 0x408) 146 #define RC_SPM_CTRL (SPM_BASE + 0x40C) 147 #define SPM2GPUPM_CON (SPM_BASE + 0x410) 148 #define SPM2APU_CON (SPM_BASE + 0x414) 149 #define SPM2EFUSE_CON (SPM_BASE + 0x418) 150 #define SPM2DFD_CON (SPM_BASE + 0x41C) 151 #define RSV_PLL_CON (SPM_BASE + 0x420) 152 #define EMI_SLB_CON (SPM_BASE + 0x424) 153 #define SPM_SUSPEND_FLAG_CON (SPM_BASE + 0x428) 154 #define SPM2PMSR_CON (SPM_BASE + 0x42C) 155 #define SPM_TOPCK_RTFF_CON (SPM_BASE + 0x430) 156 #define EMI_SHF_CON (SPM_BASE + 0x434) 157 #define CIRQ_BYPASS_CON (SPM_BASE + 0x438) 158 #define AOC_VCORE_SRAM_CON (SPM_BASE + 0x43C) 159 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_0 (SPM_BASE + 0x460) 160 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_1 (SPM_BASE + 0x464) 161 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_2 (SPM_BASE + 0x468) 162 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_3 (SPM_BASE + 0x46C) 163 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_0 (SPM_BASE + 0x470) 164 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_1 (SPM_BASE + 0x474) 165 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_2 (SPM_BASE + 0x478) 166 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_3 (SPM_BASE + 0x47C) 167 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_0 (SPM_BASE + 0x480) 168 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_1 (SPM_BASE + 0x484) 169 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_2 (SPM_BASE + 0x488) 170 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_3 (SPM_BASE + 0x48C) 171 #define REG_MODULE_SW_CG_F26M_REQ_MASK_0 (SPM_BASE + 0x490) 172 #define REG_MODULE_SW_CG_F26M_REQ_MASK_1 (SPM_BASE + 0x494) 173 #define REG_MODULE_SW_CG_F26M_REQ_MASK_2 (SPM_BASE + 0x498) 174 #define REG_MODULE_SW_CG_F26M_REQ_MASK_3 (SPM_BASE + 0x49C) 175 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_0 (SPM_BASE + 0x4A0) 176 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_1 (SPM_BASE + 0x4A4) 177 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_2 (SPM_BASE + 0x4A8) 178 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_3 (SPM_BASE + 0x4AC) 179 #define REG_PWR_STATUS_DDREN_REQ_MASK (SPM_BASE + 0x4B0) 180 #define REG_PWR_STATUS_VRF18_REQ_MASK (SPM_BASE + 0x4B4) 181 #define REG_PWR_STATUS_INFRA_REQ_MASK (SPM_BASE + 0x4B8) 182 #define REG_PWR_STATUS_F26M_REQ_MASK (SPM_BASE + 0x4BC) 183 #define REG_PWR_STATUS_PMIC_REQ_MASK (SPM_BASE + 0x4C0) 184 #define REG_PWR_STATUS_VCORE_REQ_MASK (SPM_BASE + 0x4C4) 185 #define REG_PWR_STATUS_MSB_DDREN_REQ_MASK (SPM_BASE + 0x4C8) 186 #define REG_PWR_STATUS_MSB_VRF18_REQ_MASK (SPM_BASE + 0x4CC) 187 #define REG_PWR_STATUS_MSB_INFRA_REQ_MASK (SPM_BASE + 0x4D0) 188 #define REG_PWR_STATUS_MSB_F26M_REQ_MASK (SPM_BASE + 0x4D4) 189 #define REG_PWR_STATUS_MSB_PMIC_REQ_MASK (SPM_BASE + 0x4D8) 190 #define REG_PWR_STATUS_MSB_VCORE_REQ_MASK (SPM_BASE + 0x4DC) 191 #define REG_MODULE_BUSY_DDREN_REQ_MASK (SPM_BASE + 0x4E0) 192 #define REG_MODULE_BUSY_VRF18_REQ_MASK (SPM_BASE + 0x4E4) 193 #define REG_MODULE_BUSY_INFRA_REQ_MASK (SPM_BASE + 0x4E8) 194 #define REG_MODULE_BUSY_F26M_REQ_MASK (SPM_BASE + 0x4EC) 195 #define REG_MODULE_BUSY_PMIC_REQ_MASK (SPM_BASE + 0x4F0) 196 #define REG_MODULE_BUSY_VCORE_REQ_MASK (SPM_BASE + 0x4F4) 197 #define SYS_TIMER_CON (SPM_BASE + 0x500) 198 #define SYS_TIMER_VALUE_L (SPM_BASE + 0x504) 199 #define SYS_TIMER_VALUE_H (SPM_BASE + 0x508) 200 #define SYS_TIMER_START_L (SPM_BASE + 0x50C) 201 #define SYS_TIMER_START_H (SPM_BASE + 0x510) 202 #define SYS_TIMER_LATCH_L_00 (SPM_BASE + 0x514) 203 #define SYS_TIMER_LATCH_H_00 (SPM_BASE + 0x518) 204 #define SYS_TIMER_LATCH_L_01 (SPM_BASE + 0x51C) 205 #define SYS_TIMER_LATCH_H_01 (SPM_BASE + 0x520) 206 #define SYS_TIMER_LATCH_L_02 (SPM_BASE + 0x524) 207 #define SYS_TIMER_LATCH_H_02 (SPM_BASE + 0x528) 208 #define SYS_TIMER_LATCH_L_03 (SPM_BASE + 0x52C) 209 #define SYS_TIMER_LATCH_H_03 (SPM_BASE + 0x530) 210 #define SYS_TIMER_LATCH_L_04 (SPM_BASE + 0x534) 211 #define SYS_TIMER_LATCH_H_04 (SPM_BASE + 0x538) 212 #define SYS_TIMER_LATCH_L_05 (SPM_BASE + 0x53C) 213 #define SYS_TIMER_LATCH_H_05 (SPM_BASE + 0x540) 214 #define SYS_TIMER_LATCH_L_06 (SPM_BASE + 0x544) 215 #define SYS_TIMER_LATCH_H_06 (SPM_BASE + 0x548) 216 #define SYS_TIMER_LATCH_L_07 (SPM_BASE + 0x54C) 217 #define SYS_TIMER_LATCH_H_07 (SPM_BASE + 0x550) 218 #define SYS_TIMER_LATCH_L_08 (SPM_BASE + 0x554) 219 #define SYS_TIMER_LATCH_H_08 (SPM_BASE + 0x558) 220 #define SYS_TIMER_LATCH_L_09 (SPM_BASE + 0x55C) 221 #define SYS_TIMER_LATCH_H_09 (SPM_BASE + 0x560) 222 #define SYS_TIMER_LATCH_L_10 (SPM_BASE + 0x564) 223 #define SYS_TIMER_LATCH_H_10 (SPM_BASE + 0x568) 224 #define SYS_TIMER_LATCH_L_11 (SPM_BASE + 0x56C) 225 #define SYS_TIMER_LATCH_H_11 (SPM_BASE + 0x570) 226 #define SYS_TIMER_LATCH_L_12 (SPM_BASE + 0x574) 227 #define SYS_TIMER_LATCH_H_12 (SPM_BASE + 0x578) 228 #define SYS_TIMER_LATCH_L_13 (SPM_BASE + 0x57C) 229 #define SYS_TIMER_LATCH_H_13 (SPM_BASE + 0x580) 230 #define SYS_TIMER_LATCH_L_14 (SPM_BASE + 0x584) 231 #define SYS_TIMER_LATCH_H_14 (SPM_BASE + 0x588) 232 #define SYS_TIMER_LATCH_L_15 (SPM_BASE + 0x58C) 233 #define SYS_TIMER_LATCH_H_15 (SPM_BASE + 0x590) 234 #define PCM_TIMER_VAL (SPM_BASE + 0x594) 235 #define PCM_TIMER_OUT (SPM_BASE + 0x598) 236 #define SPM_COUNTER_0 (SPM_BASE + 0x59C) 237 #define SPM_COUNTER_1 (SPM_BASE + 0x5A0) 238 #define SPM_COUNTER_2 (SPM_BASE + 0x5A4) 239 #define PCM_WDT_VAL (SPM_BASE + 0x5A8) 240 #define PCM_WDT_OUT (SPM_BASE + 0x5AC) 241 #define SPM_SW_FLAG_0 (SPM_BASE + 0x600) 242 #define SPM_SW_DEBUG_0 (SPM_BASE + 0x604) 243 #define SPM_SW_FLAG_1 (SPM_BASE + 0x608) 244 #define SPM_SW_DEBUG_1 (SPM_BASE + 0x60C) 245 #define SPM_SW_RSV_0 (SPM_BASE + 0x610) 246 #define SPM_SW_RSV_1 (SPM_BASE + 0x614) 247 #define SPM_SW_RSV_2 (SPM_BASE + 0x618) 248 #define SPM_SW_RSV_3 (SPM_BASE + 0x61C) 249 #define SPM_SW_RSV_4 (SPM_BASE + 0x620) 250 #define SPM_SW_RSV_5 (SPM_BASE + 0x624) 251 #define SPM_SW_RSV_6 (SPM_BASE + 0x628) 252 #define SPM_SW_RSV_7 (SPM_BASE + 0x62C) 253 #define SPM_SW_RSV_8 (SPM_BASE + 0x630) 254 #define SPM_BK_WAKE_EVENT (SPM_BASE + 0x634) 255 #define SPM_BK_VTCXO_DUR (SPM_BASE + 0x638) 256 #define SPM_BK_WAKE_MISC (SPM_BASE + 0x63C) 257 #define SPM_BK_PCM_TIMER (SPM_BASE + 0x640) 258 #define SPM_RSV_CON_0 (SPM_BASE + 0x650) 259 #define SPM_RSV_CON_1 (SPM_BASE + 0x654) 260 #define SPM_RSV_STA_0 (SPM_BASE + 0x658) 261 #define SPM_RSV_STA_1 (SPM_BASE + 0x65C) 262 #define SPM_SPARE_CON (SPM_BASE + 0x660) 263 #define SPM_SPARE_CON_SET (SPM_BASE + 0x664) 264 #define SPM_SPARE_CON_CLR (SPM_BASE + 0x668) 265 #define SPM_CROSS_WAKE_M00_REQ (SPM_BASE + 0x66C) 266 #define SPM_CROSS_WAKE_M01_REQ (SPM_BASE + 0x670) 267 #define SPM_CROSS_WAKE_M02_REQ (SPM_BASE + 0x674) 268 #define SPM_CROSS_WAKE_M03_REQ (SPM_BASE + 0x678) 269 #define SCP_VCORE_LEVEL (SPM_BASE + 0x67C) 270 #define SPM_DDREN_ACK_SEL_CON (SPM_BASE + 0x680) 271 #define SPM_SW_FLAG_2 (SPM_BASE + 0x684) 272 #define SPM_SW_DEBUG_2 (SPM_BASE + 0x688) 273 #define SPM_DV_CON_0 (SPM_BASE + 0x68C) 274 #define SPM_DV_CON_1 (SPM_BASE + 0x690) 275 #define SPM_SEMA_M0 (SPM_BASE + 0x69C) 276 #define SPM_SEMA_M1 (SPM_BASE + 0x6A0) 277 #define SPM_SEMA_M2 (SPM_BASE + 0x6A4) 278 #define SPM_SEMA_M3 (SPM_BASE + 0x6A8) 279 #define SPM_SEMA_M4 (SPM_BASE + 0x6AC) 280 #define SPM_SEMA_M5 (SPM_BASE + 0x6B0) 281 #define SPM_SEMA_M6 (SPM_BASE + 0x6B4) 282 #define SPM_SEMA_M7 (SPM_BASE + 0x6B8) 283 #define SPM2ADSP_MAILBOX (SPM_BASE + 0x6BC) 284 #define ADSP2SPM_MAILBOX (SPM_BASE + 0x6C0) 285 #define VCORE_RTFF_CTRL_MASK_SET (SPM_BASE + 0x6C4) 286 #define VCORE_RTFF_CTRL_MASK_CLR (SPM_BASE + 0x6C8) 287 #define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x6CC) 288 #define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x6D0) 289 #define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x6D4) 290 #define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x6D8) 291 #define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x6DC) 292 #define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x6E0) 293 #define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x6E4) 294 #define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x6E8) 295 #define SPM2SCP_MAILBOX (SPM_BASE + 0x6EC) 296 #define SCP2SPM_MAILBOX (SPM_BASE + 0x6F0) 297 #define SCP_AOV_BUS_CON (SPM_BASE + 0x6F4) 298 #define VCORE_RTFF_CTRL_MASK (SPM_BASE + 0x6F8) 299 #define SPM_SRAM_SRCLKENO_MASK (SPM_BASE + 0x6FC) 300 #define EMI_PDN_REQ (SPM_BASE + 0x700) 301 #define EMI_BUSY_REQ (SPM_BASE + 0x704) 302 #define EMI_RESERVED_STA (SPM_BASE + 0x708) 303 #define SC_UNIVPLL_DIV_RST_B (SPM_BASE + 0x70C) 304 #define ECO_ARMPLL_DIV_CLOCK_OFF (SPM_BASE + 0x710) 305 #define SPM_MCDSR_CG_CHECK_X1 (SPM_BASE + 0x714) 306 #define SPM_SODI2_CG_CHECK_X1 (SPM_BASE + 0x718) 307 #define SPM_WAKEUP_STA (SPM_BASE + 0x800) 308 #define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x804) 309 #define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x808) 310 #define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x80C) 311 #define SPM_WAKEUP_EVENT_SENS (SPM_BASE + 0x810) 312 #define SPM_WAKEUP_EVENT_CLEAR (SPM_BASE + 0x814) 313 #define SPM_SRC_REQ (SPM_BASE + 0x818) 314 #define SPM_SRC_MASK_0 (SPM_BASE + 0x81C) 315 #define SPM_SRC_MASK_1 (SPM_BASE + 0x820) 316 #define SPM_SRC_MASK_2 (SPM_BASE + 0x824) 317 #define SPM_SRC_MASK_3 (SPM_BASE + 0x828) 318 #define SPM_SRC_MASK_4 (SPM_BASE + 0x82C) 319 #define SPM_SRC_MASK_5 (SPM_BASE + 0x830) 320 #define SPM_SRC_MASK_6 (SPM_BASE + 0x834) 321 #define SPM_SRC_MASK_7 (SPM_BASE + 0x838) 322 #define SPM_SRC_MASK_8 (SPM_BASE + 0x83C) 323 #define SPM_SRC_MASK_9 (SPM_BASE + 0x840) 324 #define SPM_SRC_MASK_10 (SPM_BASE + 0x844) 325 #define SPM_SRC_MASK_11 (SPM_BASE + 0x848) 326 #define SPM_SRC_MASK_12 (SPM_BASE + 0x84C) 327 #define SPM_REQ_STA_0 (SPM_BASE + 0x850) 328 #define SPM_REQ_STA_1 (SPM_BASE + 0x854) 329 #define SPM_REQ_STA_2 (SPM_BASE + 0x858) 330 #define SPM_REQ_STA_3 (SPM_BASE + 0x85C) 331 #define SPM_REQ_STA_4 (SPM_BASE + 0x860) 332 #define SPM_REQ_STA_5 (SPM_BASE + 0x864) 333 #define SPM_REQ_STA_6 (SPM_BASE + 0x868) 334 #define SPM_REQ_STA_7 (SPM_BASE + 0x86C) 335 #define SPM_REQ_STA_8 (SPM_BASE + 0x870) 336 #define SPM_REQ_STA_9 (SPM_BASE + 0x874) 337 #define SPM_REQ_STA_10 (SPM_BASE + 0x878) 338 #define SPM_REQ_STA_11 (SPM_BASE + 0x87C) 339 #define SPM_REQ_STA_12 (SPM_BASE + 0x880) 340 #define SPM_IPC_WAKEUP_REQ (SPM_BASE + 0x884) 341 #define IPC_WAKEUP_REQ_MASK_STA (SPM_BASE + 0x888) 342 #define SPM_EVENT_CON_MISC (SPM_BASE + 0x88C) 343 #define DDREN_DBC_CON (SPM_BASE + 0x890) 344 #define SPM_RESOURCE_ACK_CON_0 (SPM_BASE + 0x894) 345 #define SPM_RESOURCE_ACK_CON_1 (SPM_BASE + 0x898) 346 #define SPM_RESOURCE_ACK_MASK_0 (SPM_BASE + 0x89C) 347 #define SPM_RESOURCE_ACK_MASK_1 (SPM_BASE + 0x8A0) 348 #define SPM_RESOURCE_ACK_MASK_2 (SPM_BASE + 0x8A4) 349 #define SPM_RESOURCE_ACK_MASK_3 (SPM_BASE + 0x8A8) 350 #define SPM_RESOURCE_ACK_MASK_4 (SPM_BASE + 0x8AC) 351 #define SPM_RESOURCE_ACK_MASK_5 (SPM_BASE + 0x8B0) 352 #define SPM_RESOURCE_ACK_MASK_6 (SPM_BASE + 0x8B4) 353 #define SPM_EVENT_COUNTER_CLEAR (SPM_BASE + 0x8B8) 354 #define SPM_VCORE_EVENT_COUNT_STA (SPM_BASE + 0x8BC) 355 #define SPM_PMIC_EVENT_COUNT_STA (SPM_BASE + 0x8C0) 356 #define SPM_SRCCLKENA_EVENT_COUNT_STA (SPM_BASE + 0x8C4) 357 #define SPM_INFRA_EVENT_COUNT_STA (SPM_BASE + 0x8C8) 358 #define SPM_VRF18_EVENT_COUNT_STA (SPM_BASE + 0x8CC) 359 #define SPM_EMI_EVENT_COUNT_STA (SPM_BASE + 0x8D0) 360 #define SPM_APSRC_EVENT_COUNT_STA (SPM_BASE + 0x8D4) 361 #define SPM_DDREN_EVENT_COUNT_STA (SPM_BASE + 0x8D8) 362 #define PCM_WDT_LATCH_0 (SPM_BASE + 0x8DC) 363 #define PCM_WDT_LATCH_1 (SPM_BASE + 0x8E0) 364 #define PCM_WDT_LATCH_2 (SPM_BASE + 0x8E4) 365 #define PCM_WDT_LATCH_3 (SPM_BASE + 0x8E8) 366 #define PCM_WDT_LATCH_4 (SPM_BASE + 0x8EC) 367 #define PCM_WDT_LATCH_5 (SPM_BASE + 0x8F0) 368 #define PCM_WDT_LATCH_6 (SPM_BASE + 0x8F4) 369 #define PCM_WDT_LATCH_7 (SPM_BASE + 0x8F8) 370 #define PCM_WDT_LATCH_8 (SPM_BASE + 0x8FC) 371 #define PCM_WDT_LATCH_9 (SPM_BASE + 0x900) 372 #define PCM_WDT_LATCH_10 (SPM_BASE + 0x904) 373 #define PCM_WDT_LATCH_11 (SPM_BASE + 0x908) 374 #define PCM_WDT_LATCH_12 (SPM_BASE + 0x90C) 375 #define PCM_WDT_LATCH_13 (SPM_BASE + 0x910) 376 #define PCM_WDT_LATCH_14 (SPM_BASE + 0x914) 377 #define PCM_WDT_LATCH_15 (SPM_BASE + 0x918) 378 #define PCM_WDT_LATCH_16 (SPM_BASE + 0x91C) 379 #define PCM_WDT_LATCH_17 (SPM_BASE + 0x920) 380 #define PCM_WDT_LATCH_18 (SPM_BASE + 0x924) 381 #define PCM_WDT_LATCH_19 (SPM_BASE + 0x928) 382 #define PCM_WDT_LATCH_20 (SPM_BASE + 0x92C) 383 #define PCM_WDT_LATCH_21 (SPM_BASE + 0x930) 384 #define PCM_WDT_LATCH_22 (SPM_BASE + 0x934) 385 #define PCM_WDT_LATCH_23 (SPM_BASE + 0x938) 386 #define PCM_WDT_LATCH_24 (SPM_BASE + 0x93C) 387 #define PCM_WDT_LATCH_25 (SPM_BASE + 0x940) 388 #define PCM_WDT_LATCH_26 (SPM_BASE + 0x944) 389 #define PCM_WDT_LATCH_27 (SPM_BASE + 0x948) 390 #define PCM_WDT_LATCH_28 (SPM_BASE + 0x94C) 391 #define PCM_WDT_LATCH_29 (SPM_BASE + 0x950) 392 #define PCM_WDT_LATCH_30 (SPM_BASE + 0x954) 393 #define PCM_WDT_LATCH_31 (SPM_BASE + 0x958) 394 #define PCM_WDT_LATCH_32 (SPM_BASE + 0x95C) 395 #define PCM_WDT_LATCH_33 (SPM_BASE + 0x960) 396 #define PCM_WDT_LATCH_34 (SPM_BASE + 0x964) 397 #define PCM_WDT_LATCH_35 (SPM_BASE + 0x968) 398 #define PCM_WDT_LATCH_36 (SPM_BASE + 0x96C) 399 #define PCM_WDT_LATCH_37 (SPM_BASE + 0x970) 400 #define PCM_WDT_LATCH_38 (SPM_BASE + 0x974) 401 #define PCM_WDT_LATCH_39 (SPM_BASE + 0x978) 402 #define PCM_WDT_LATCH_40 (SPM_BASE + 0x97C) 403 #define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x980) 404 #define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x984) 405 #define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x988) 406 #define PCM_WDT_LATCH_SPARE_3 (SPM_BASE + 0x98C) 407 #define PCM_WDT_LATCH_SPARE_4 (SPM_BASE + 0x990) 408 #define PCM_WDT_LATCH_SPARE_5 (SPM_BASE + 0x994) 409 #define PCM_WDT_LATCH_SPARE_6 (SPM_BASE + 0x998) 410 #define PCM_WDT_LATCH_SPARE_7 (SPM_BASE + 0x99C) 411 #define PCM_WDT_LATCH_SPARE_8 (SPM_BASE + 0x9A0) 412 #define PCM_WDT_LATCH_SPARE_9 (SPM_BASE + 0x9A4) 413 #define DRAMC_GATING_ERR_LATCH_0 (SPM_BASE + 0x9A8) 414 #define DRAMC_GATING_ERR_LATCH_1 (SPM_BASE + 0x9AC) 415 #define DRAMC_GATING_ERR_LATCH_2 (SPM_BASE + 0x9B0) 416 #define DRAMC_GATING_ERR_LATCH_3 (SPM_BASE + 0x9B4) 417 #define DRAMC_GATING_ERR_LATCH_4 (SPM_BASE + 0x9B8) 418 #define DRAMC_GATING_ERR_LATCH_5 (SPM_BASE + 0x9BC) 419 #define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x9C0) 420 #define SPM_DEBUG_CON (SPM_BASE + 0x9C4) 421 #define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x9C8) 422 #define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x9CC) 423 #define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x9D0) 424 #define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x9D4) 425 #define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x9D8) 426 #define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x9DC) 427 #define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x9E0) 428 #define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x9E4) 429 #define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x9E8) 430 #define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x9EC) 431 #define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x9F0) 432 #define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x9F4) 433 #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x9F8) 434 #define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x9FC) 435 #define MD1_PWR_CON (SPM_BASE + 0xE00) 436 #define CONN_PWR_CON (SPM_BASE + 0xE04) 437 #define IFR_PWR_CON (SPM_BASE + 0xE08) 438 #define PERI_PWR_CON (SPM_BASE + 0xE0C) 439 #define UFS0_PWR_CON (SPM_BASE + 0xE10) 440 #define UFS0_PHY_PWR_CON (SPM_BASE + 0xE14) 441 #define AUDIO_PWR_CON (SPM_BASE + 0xE18) 442 #define ADSP_TOP_PWR_CON (SPM_BASE + 0xE1C) 443 #define ADSP_INFRA_PWR_CON (SPM_BASE + 0xE20) 444 #define ADSP_AO_PWR_CON (SPM_BASE + 0xE24) 445 #define ISP_IMG1_PWR_CON (SPM_BASE + 0xE28) 446 #define ISP_IMG2_PWR_CON (SPM_BASE + 0xE2C) 447 #define ISP_IPE_PWR_CON (SPM_BASE + 0xE30) 448 #define ISP_VCORE_PWR_CON (SPM_BASE + 0xE34) 449 #define VDE0_PWR_CON (SPM_BASE + 0xE38) 450 #define VDE1_PWR_CON (SPM_BASE + 0xE3C) 451 #define VEN0_PWR_CON (SPM_BASE + 0xE40) 452 #define VEN1_PWR_CON (SPM_BASE + 0xE44) 453 #define CAM_MAIN_PWR_CON (SPM_BASE + 0xE48) 454 #define CAM_MRAW_PWR_CON (SPM_BASE + 0xE4C) 455 #define CAM_SUBA_PWR_CON (SPM_BASE + 0xE50) 456 #define CAM_SUBB_PWR_CON (SPM_BASE + 0xE54) 457 #define CAM_SUBC_PWR_CON (SPM_BASE + 0xE58) 458 #define CAM_VCORE_PWR_CON (SPM_BASE + 0xE5C) 459 #define CAM_CCU_PWR_CON (SPM_BASE + 0xE60) 460 #define CAM_CCU_AO_PWR_CON (SPM_BASE + 0xE64) 461 #define MDP0_PWR_CON (SPM_BASE + 0xE68) 462 #define MDP1_PWR_CON (SPM_BASE + 0xE6C) 463 #define DIS0_PWR_CON (SPM_BASE + 0xE70) 464 #define DIS1_PWR_CON (SPM_BASE + 0xE74) 465 #define MM_INFRA_PWR_CON (SPM_BASE + 0xE78) 466 #define MM_PROC_PWR_CON (SPM_BASE + 0xE7C) 467 #define DP_TX_PWR_CON (SPM_BASE + 0xE80) 468 #define SCP_CORE_PWR_CON (SPM_BASE + 0xE84) 469 #define SCP_PERI_PWR_CON (SPM_BASE + 0xE88) 470 #define DPM0_PWR_CON (SPM_BASE + 0xE8C) 471 #define DPM1_PWR_CON (SPM_BASE + 0xE90) 472 #define EMI0_PWR_CON (SPM_BASE + 0xE94) 473 #define EMI1_PWR_CON (SPM_BASE + 0xE98) 474 #define CSI_RX_PWR_CON (SPM_BASE + 0xE9C) 475 #define SSRSYS_PWR_CON (SPM_BASE + 0xEA0) 476 #define SSPM_PWR_CON (SPM_BASE + 0xEA4) 477 #define SSUSB_PWR_CON (SPM_BASE + 0xEA8) 478 #define SSUSB_PHY_PWR_CON (SPM_BASE + 0xEAC) 479 #define CPUEB_PWR_CON (SPM_BASE + 0xEB0) 480 #define MFG0_PWR_CON (SPM_BASE + 0xEB4) 481 #define MFG1_PWR_CON (SPM_BASE + 0xEB8) 482 #define MFG2_PWR_CON (SPM_BASE + 0xEBC) 483 #define MFG3_PWR_CON (SPM_BASE + 0xEC0) 484 #define MFG4_PWR_CON (SPM_BASE + 0xEC4) 485 #define MFG5_PWR_CON (SPM_BASE + 0xEC8) 486 #define MFG6_PWR_CON (SPM_BASE + 0xECC) 487 #define MFG7_PWR_CON (SPM_BASE + 0xED0) 488 #define ADSP_HRE_SRAM_CON (SPM_BASE + 0xED4) 489 #define CCU_SLEEP_SRAM_CON (SPM_BASE + 0xED8) 490 #define EFUSE_SRAM_CON (SPM_BASE + 0xEDC) 491 #define EMI_HRE_SRAM_CON (SPM_BASE + 0xEE0) 492 #define EMI_SLB_SRAM_CON (SPM_BASE + 0xEE4) 493 #define INFRA_HRE_SRAM_CON (SPM_BASE + 0xEE8) 494 #define INFRA_SLEEP_SRAM_CON (SPM_BASE + 0xEEC) 495 #define MM_HRE_SRAM_CON (SPM_BASE + 0xEF0) 496 #define NTH_EMI_SLB_SRAM_CON (SPM_BASE + 0xEF4) 497 #define NTH_EMI_SLB_SRAM_ACK (SPM_BASE + 0xEF8) 498 #define PERI_SLEEP_SRAM_CON (SPM_BASE + 0xEFC) 499 #define SPM_SRAM_CON (SPM_BASE + 0xF00) 500 #define SSPM_SRAM_CON (SPM_BASE + 0xF04) 501 #define SSR_SLEEP_SRAM_CON (SPM_BASE + 0xF08) 502 #define STH_EMI_SLB_SRAM_CON (SPM_BASE + 0xF0C) 503 #define STH_EMI_SLB_SRAM_ACK (SPM_BASE + 0xF10) 504 #define UFS_PDN_SRAM_CON (SPM_BASE + 0xF14) 505 #define UFS_SLEEP_SRAM_CON (SPM_BASE + 0xF18) 506 #define UNIPRO_PDN_SRAM_CON (SPM_BASE + 0xF1C) 507 #define CPU_BUCK_ISO_CON (SPM_BASE + 0xF20) 508 #define MD_BUCK_ISO_CON (SPM_BASE + 0xF24) 509 #define SOC_BUCK_ISO_CON (SPM_BASE + 0xF28) 510 #define SOC_BUCK_ISO_CON_SET (SPM_BASE + 0xF2C) 511 #define SOC_BUCK_ISO_CON_CLR (SPM_BASE + 0xF30) 512 #define SOC_BUCK_ISO_CON_2 (SPM_BASE + 0xF34) 513 #define SOC_BUCK_ISO_CON_2_SET (SPM_BASE + 0xF38) 514 #define SOC_BUCK_ISO_CON_2_CLR (SPM_BASE + 0xF3C) 515 #define PWR_STATUS (SPM_BASE + 0xF40) 516 #define PWR_STATUS_2ND (SPM_BASE + 0xF44) 517 #define PWR_STATUS_MSB (SPM_BASE + 0xF48) 518 #define PWR_STATUS_MSB_2ND (SPM_BASE + 0xF4C) 519 #define XPU_PWR_STATUS (SPM_BASE + 0xF50) 520 #define XPU_PWR_STATUS_2ND (SPM_BASE + 0xF54) 521 #define DFD_SOC_PWR_LATCH (SPM_BASE + 0xF58) 522 #define SUBSYS_PM_BYPASS (SPM_BASE + 0xF5C) 523 #define VADSP_HRE_SRAM_CON (SPM_BASE + 0xF60) 524 #define VADSP_HRE_SRAM_ACK (SPM_BASE + 0xF64) 525 #define GCPU_SRAM_CON (SPM_BASE + 0xF68) 526 #define GCPU_SRAM_ACK (SPM_BASE + 0xF6C) 527 #define EDP_TX_PWR_CON (SPM_BASE + 0xF70) 528 #define PCIE_PWR_CON (SPM_BASE + 0xF74) 529 #define PCIE_PHY_PWR_CON (SPM_BASE + 0xF78) 530 #define SPM_TWAM_CON (SPM_BASE + 0xF80) 531 #define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0xF84) 532 #define SPM_TWAM_IDLE_SEL (SPM_BASE + 0xF88) 533 #define SPM_TWAM_LAST_STA_0 (SPM_BASE + 0xF8C) 534 #define SPM_TWAM_LAST_STA_1 (SPM_BASE + 0xF90) 535 #define SPM_TWAM_LAST_STA_2 (SPM_BASE + 0xF94) 536 #define SPM_TWAM_LAST_STA_3 (SPM_BASE + 0xF98) 537 #define SPM_TWAM_CURR_STA_0 (SPM_BASE + 0xF9C) 538 #define SPM_TWAM_CURR_STA_1 (SPM_BASE + 0xFA0) 539 #define SPM_TWAM_CURR_STA_2 (SPM_BASE + 0xFA4) 540 #define SPM_TWAM_CURR_STA_3 (SPM_BASE + 0xFA8) 541 #define SPM_TWAM_TIMER_OUT (SPM_BASE + 0xFAC) 542 543 #define EC_SUSPEND_PIN 140 544 545 /* POWERON_CONFIG_EN (0x1C001000+0x000) */ 546 #define BCLK_CG_EN_LSB BIT(0) /* 1b */ 547 #define PROJECT_CODE_LSB BIT(16) /* 16b */ 548 /* SPM_POWER_ON_VAL0 (0x1C001000+0x004) */ 549 #define POWER_ON_VAL0_LSB BIT(0) /* 32b */ 550 /* SPM_POWER_ON_VAL1 (0x1C001000+0x008) */ 551 #define POWER_ON_VAL1_LSB BIT(0) /* 32b */ 552 /* SPM_POWER_ON_VAL2 (0x1C001000+0x00C) */ 553 #define POWER_ON_VAL2_LSB BIT(0) /* 32b */ 554 /* SPM_POWER_ON_VAL3 (0x1C001000+0x010) */ 555 #define POWER_ON_VAL3_LSB BIT(0) /* 32b */ 556 /* PCM_PWR_IO_EN (0x1C001000+0x014) */ 557 #define PCM_PWR_IO_EN_LSB BIT(0) /* 8b */ 558 /* PCM_CON0 (0x1C001000+0x018) */ 559 #define PCM_CK_EN_LSB BIT(2) /* 1b */ 560 #define PCM_SW_RESET_LSB BIT(15) /* 1b */ 561 #define PCM_CON0_PROJECT_CODE_LSB BIT(16) /* 16b */ 562 /* PCM_CON1 (0x1C001000+0x01C) */ 563 #define REG_SPM_APB_INTERNAL_EN_LSB BIT(3) /* 1b */ 564 #define REG_PCM_TIMER_EN_LSB BIT(5) /* 1b */ 565 #define REG_PCM_WDT_EN_LSB BIT(8) /* 1b */ 566 #define REG_PCM_WDT_WAKE_LSB BIT(9) /* 1b */ 567 #define REG_SSPM_APB_P2P_EN_LSB BIT(10) /* 1b */ 568 #define REG_MCUPM_APB_P2P_EN_LSB BIT(11) /* 1b */ 569 #define REG_RSV_APB_P2P_EN_LSB BIT(12) /* 1b */ 570 #define RG_PCM_IRQ_MSK_LSB BIT(15) /* 1b */ 571 #define PCM_CON1_PROJECT_CODE_LSB BIT(16) /* 16b */ 572 /* SPM_SRAM_SLEEP_CTRL (0x1C001000+0x020) */ 573 #define REG_SRAM_ISO_ACTIVE_LSB BIT(0) /* 8b */ 574 #define REG_SRAM_SLP2ISO_TIME_LSB BIT(8) /* 8b */ 575 #define REG_SPM_SRAM_CTRL_MUX_LSB BIT(16) /* 1b */ 576 #define REG_SRAM_SLEEP_TIME_LSB BIT(24) /* 8b */ 577 /* SPM_CLK_CON (0x1C001000+0x024) */ 578 #define REG_SPM_LOCK_INFRA_DCM_LSB BIT(0) /* 1b */ 579 #define REG_CXO32K_REMOVE_EN_LSB BIT(1) /* 1b */ 580 #define REG_SPM_LEAVE_SUSPEND_MERGE_MASK_LSB BIT(4) /* 3b */ 581 #define REG_SRCLKENO0_SRC_MASK_B_LSB BIT(8) /* 8b */ 582 #define REG_SRCLKENO1_SRC_MASK_B_LSB BIT(16) /* 8b */ 583 #define REG_SRCLKENO2_SRC_MASK_B_LSB BIT(24) /* 8b */ 584 /* SPM_CLK_SETTLE (0x1C001000+0x028) */ 585 #define SYSCLK_SETTLE_LSB IT(0) /* 28b */ 586 /* SPM_SW_RST_CON (0x1C001000+0x040) */ 587 #define SPM_SW_RST_CON_LSB BIT(0) /* 16b */ 588 #define SPM_SW_RST_CON_PROJECT_CODE_LSB BIT(16) /* 16b */ 589 /* SPM_SW_RST_CON_SET (0x1C001000+0x044) */ 590 #define SPM_SW_RST_CON_SET_LSB BIT(0) /* 16b */ 591 #define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB BIT(16) /* 16b */ 592 /* SPM_SW_RST_CON_CLR (0x1C001000+0x048) */ 593 #define SPM_SW_RST_CON_CLR_LSB BIT(0) /* 16b */ 594 #define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB BIT(16) /* 16b */ 595 /* R_SEC_READ_MASK (0x1C001000+0x050) */ 596 #define SPM_SEC_READ_MASK_LSB BIT(0) /* 1b */ 597 /* R_ONE_TIME_LOCK_L (0x1C001000+0x054) */ 598 #define SPM_ONE_TIME_LOCK_L_LSB BIT(0) /* 32b */ 599 /* R_ONE_TIME_LOCK_M (0x1C001000+0x058) */ 600 #define SPM_ONE_TIME_LOCK_M_LSB BIT(0) /* 32b */ 601 /* R_ONE_TIME_LOCK_H (0x1C001000+0x05C) */ 602 #define SPM_ONE_TIME_LOCK_H_LSB BIT(0) /* 32b */ 603 /* SSPM_CLK_CON (0x1C001000+0x084) */ 604 #define REG_SSPM_26M_CK_SEL_LSB BIT(0) /* 1b */ 605 #define REG_SSPM_DCM_EN_LSB BIT(1) /* 1b */ 606 /* SCP_CLK_CON (0x1C001000+0x088) */ 607 #define REG_SCP_26M_CK_SEL_LSB BIT(0) /* 1b */ 608 #define REG_SCP_DCM_EN_LSB BIT(1) /* 1b */ 609 #define SCP_SECURE_VREQ_MASK_LSB BIT(2) /* 1b */ 610 #define SCP_SLP_REQ_LSB BIT(3) /* 1b */ 611 #define SCP_SLP_ACK_LSB BIT(4) /* 1b */ 612 /* SPM_SWINT (0x1C001000+0x090) */ 613 #define SPM_SWINT_LSB BIT(0) /* 32b */ 614 /* SPM_SWINT_SET (0x1C001000+0x094) */ 615 #define SPM_SWINT_SET_LSB BIT(0) /* 32b */ 616 /* SPM_SWINT_CLR (0x1C001000+0x098) */ 617 #define SPM_SWINT_CLR_LSB BIT(0) /* 32b */ 618 /* SPM_CPU_WAKEUP_EVENT (0x1C001000+0x0B0) */ 619 #define REG_CPU_WAKEUP_LSB BIT(0) /* 1b */ 620 /* SPM_IRQ_MASK (0x1C001000+0x0B4) */ 621 #define REG_SPM_IRQ_MASK_LSB BIT(0) /* 32b */ 622 /* MD32PCM_SCU_CTRL0 (0x1C001000+0x100) */ 623 #define MD32PCM_CTRL0_LSB BIT(0) /* 32b */ 624 /* MD32PCM_SCU_CTRL1 (0x1C001000+0x104) */ 625 #define MD32PCM_CTRL1_LSB BIT(0) /* 32b */ 626 /* MD32PCM_SCU_CTRL2 (0x1C001000+0x108) */ 627 #define MD32PCM_CTRL2_LSB BIT(0) /* 32b */ 628 /* MD32PCM_SCU_CTRL3 (0x1C001000+0x10C) */ 629 #define MD32PCM_CTRL3_LSB BIT(0) /* 32b */ 630 /* MD32PCM_SCU_STA0 (0x1C001000+0x110) */ 631 #define MD32PCM_STA0_LSB BIT(0) /* 32b */ 632 /* SPM_IRQ_STA (0x1C001000+0x128) */ 633 #define PCM_IRQ_LSB BIT(3) /* 1b */ 634 /* MD32PCM_WAKEUP_STA (0x1C001000+0x130) */ 635 #define MD32PCM_WAKEUP_STA_LSB BIT(0) /* 32b */ 636 /* MD32PCM_EVENT_STA (0x1C001000+0x134) */ 637 #define MD32PCM_EVENT_STA_LSB BIT(0) /* 32b */ 638 /* SPM_WAKEUP_MISC (0x1C001000+0x140) */ 639 #define SRCLKEN_RC_ERR_INT_LSB BIT(0) /* 1b */ 640 #define SPM_TIMEOUT_WAKEUP_0_LSB BIT(1) /* 1b */ 641 #define SPM_TIMEOUT_WAKEUP_1_LSB BIT(2) /* 1b */ 642 #define SPM_TIMEOUT_WAKEUP_2_LSB BIT(3) /* 1b */ 643 #define DVFSRC_IRQ_LSB BIT(4) /* 1b */ 644 #define TWAM_IRQ_B_LSB BIT(5) /* 1b */ 645 #define SPM_ACK_CHK_WAKEUP_0_LSB BIT(6) /* 1b */ 646 #define SPM_ACK_CHK_WAKEUP_1_LSB BIT(7) /* 1b */ 647 #define SPM_ACK_CHK_WAKEUP_2_LSB BIT(8) /* 1b */ 648 #define SPM_ACK_CHK_WAKEUP_3_LSB BIT(9) /* 1b */ 649 #define SPM_ACK_CHK_WAKEUP_ALL_LSB BIT(10) /* 1b */ 650 #define VLP_BUS_TIMEOUT_IRQ_LSB BIT(11) /* 1b */ 651 #define PCM_TIMER_EVENT_LSB BIT(16) /* 1b */ 652 #define PMIC_EINT_OUT_LSB BIT(19) /* 2b */ 653 #define PMIC_IRQ_ACK_LSB BIT(30) /* 1b */ 654 #define PMIC_SCP_IRQ_LSB BIT(31) /* 1b */ 655 /* SPM_CK_STA (0x1C001000+0x164) */ 656 #define PCM_CK_SEL_O_LSB BIT(0) /* 4b */ 657 #define EXT_SRC_STA_LSB BIT(4) /* 3b */ 658 #define CK_SLEEP_EN_LSB BIT(8) /* 1b */ 659 #define SPM_SRAM_CTRL_CK_SEL_LSB BIT(9) /* 1b */ 660 /* MD32PCM_STA (0x1C001000+0x190) */ 661 #define MD32PCM_HALT_LSB BIT(0) /* 1b */ 662 #define MD32PCM_GATED_LSB BIT(1) /* 1b */ 663 /* MD32PCM_PC (0x1C001000+0x194) */ 664 #define MON_PC_LSB BIT(0) /* 32b */ 665 /* SPM_AP_STANDBY_CON (0x1C001000+0x200) */ 666 #define REG_WFI_OP_LSB BIT(0) /* 1b */ 667 #define REG_WFI_TYPE_LSB BIT(1) /* 1b */ 668 #define REG_MP0_CPUTOP_IDLE_MASK_LSB BIT(2) /* 1b */ 669 #define REG_MP1_CPUTOP_IDLE_MASK_LSB BIT(3) /* 1b */ 670 #define REG_MCUSYS_IDLE_MASK_LSB BIT(4) /* 1b */ 671 #define REG_CSYSPWRUP_REQ_MASK_LSB BIT(5) /* 1b */ 672 #define WFI_AF_SEL_LSB BIT(16) /* 8b */ 673 #define CPU_SLEEP_WFI_LSB BIT(31) /* 1b */ 674 /* CPU_WFI_EN (0x1C001000+0x204) */ 675 #define CPU_WFI_EN_LSB BIT(0) /* 8b */ 676 /* CPU_WFI_EN_SET (0x1C001000+0x208) */ 677 #define CPU_WFI_EN_SET_LSB BIT(0) /* 8b */ 678 /* CPU_WFI_EN_CLR (0x1C001000+0x20C) */ 679 #define CPU_WFI_EN_CLR_LSB BIT(0) /* 8b */ 680 /* EXT_INT_WAKEUP_REQ (0x1C001000+0x210) */ 681 #define EXT_INT_WAKEUP_REQ_LSB BIT(0) /* 10b */ 682 /* EXT_INT_WAKEUP_REQ_SET (0x1C001000+0x214) */ 683 #define EXT_INT_WAKEUP_REQ_SET_LSB BIT(0) /* 10b */ 684 /* EXT_INT_WAKEUP_REQ_CLR (0x1C001000+0x218) */ 685 #define EXT_INT_WAKEUP_REQ_CLR_LSB BIT(0) /* 10b */ 686 /* MCUSYS_IDLE_STA (0x1C001000+0x21C) */ 687 #define MCUSYS_DDREN_LSB BIT(0) /* 8b */ 688 #define ARMBUS_IDLE_TO_26M_LSB BIT(8) /* 1b */ 689 #define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB BIT(9) /* 1b */ 690 #define MP0_CPU_IDLE_TO_PWR_OFF_LSB BIT(16) /* 8b */ 691 /* CPU_PWR_STATUS (0x1C001000+0x220) */ 692 #define MP0_SPMC_PWR_ON_ACK_CPU0_LSB BIT(0) /* 1b */ 693 #define MP0_SPMC_PWR_ON_ACK_CPU1_LSB BIT(1) /* 1b */ 694 #define MP0_SPMC_PWR_ON_ACK_CPU2_LSB BIT(2) /* 1b */ 695 #define MP0_SPMC_PWR_ON_ACK_CPU3_LSB BIT(3) /* 1b */ 696 #define MP0_SPMC_PWR_ON_ACK_CPU4_LSB BIT(4) /* 1b */ 697 #define MP0_SPMC_PWR_ON_ACK_CPU5_LSB BIT(5) /* 1b */ 698 #define MP0_SPMC_PWR_ON_ACK_CPU6_LSB BIT(6) /* 1b */ 699 #define MP0_SPMC_PWR_ON_ACK_CPU7_LSB BIT(7) /* 1b */ 700 #define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB BIT(8) /* 1b */ 701 #define MCUSYS_SPMC_PWR_ON_ACK_LSB BIT(9) /* 1b */ 702 /* SW2SPM_WAKEUP (0x1C001000+0x224) */ 703 #define SW2SPM_WAKEUP_LSB BIT(0) /* 4b */ 704 /* SW2SPM_WAKEUP_SET (0x1C001000+0x228) */ 705 #define SW2SPM_WAKEUP_SET_LSB BIT(0) /* 4b */ 706 /* SW2SPM_WAKEUP_CLR (0x1C001000+0x22C) */ 707 #define SW2SPM_WAKEUP_CLR_LSB BIT(0) /* 4b */ 708 /* SW2SPM_MAILBOX_0 (0x1C001000+0x230) */ 709 #define SW2SPM_MAILBOX_0_LSB BIT(0) /* 32b */ 710 /* SW2SPM_MAILBOX_1 (0x1C001000+0x234) */ 711 #define SW2SPM_MAILBOX_1_LSB BIT(0) /* 32b */ 712 /* SW2SPM_MAILBOX_2 (0x1C001000+0x238) */ 713 #define SW2SPM_MAILBOX_2_LSB BIT(0) /* 32b */ 714 /* SW2SPM_MAILBOX_3 (0x1C001000+0x23C) */ 715 #define SW2SPM_MAILBOX_3_LSB BIT(0) /* 32b */ 716 /* SPM2SW_MAILBOX_0 (0x1C001000+0x240) */ 717 #define SPM2SW_MAILBOX_0_LSB BIT(0) /* 32b */ 718 /* SPM2SW_MAILBOX_1 (0x1C001000+0x244) */ 719 #define SPM2SW_MAILBOX_1_LSB BIT(0) /* 32b */ 720 /* SPM2SW_MAILBOX_2 (0x1C001000+0x248) */ 721 #define SPM2SW_MAILBOX_2_LSB BIT(0) /* 32b */ 722 /* SPM2SW_MAILBOX_3 (0x1C001000+0x24C) */ 723 #define SPM2SW_MAILBOX_3_LSB BIT(0) /* 32b */ 724 /* SPM2MCUPM_CON (0x1C001000+0x250) */ 725 #define SPM2MCUPM_SW_RST_B_LSB BIT(0) /* 1b */ 726 #define SPM2MCUPM_SW_INT_LSB BIT(1) /* 1b */ 727 #define MCUPM_WFI_LSB BIT(16) /* 1b */ 728 /* SPM_MCUSYS_PWR_CON (0x1C001000+0x260) */ 729 #define MCUSYS_SPMC_PWR_ON_LSB BIT(2) /* 1b */ 730 #define MCUSYS_SPMC_RESET_PWRON_CONFIG_LSB BIT(5) /* 1b */ 731 #define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB BIT(31) /* 1b */ 732 /* SPM_CPUTOP_PWR_CON (0x1C001000+0x264) */ 733 #define MP0_SPMC_PWR_ON_CPUTOP_LSB BIT(2) /* 1b */ 734 #define MP0_SPMC_RESET_PWRON_CONFIG_CPUTOP_LSB BIT(5) /* 1b */ 735 #define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB BIT(31) /* 1b */ 736 /* SPM_CPU0_PWR_CON (0x1C001000+0x268) */ 737 #define MP0_SPMC_PWR_ON_CPU0_LSB BIT(2) /* 1b */ 738 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU0_LSB BIT(5) /* 1b */ 739 #define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB BIT(31) /* 1b */ 740 /* SPM_CPU1_PWR_CON (0x1C001000+0x26C) */ 741 #define MP0_SPMC_PWR_ON_CPU1_LSB BIT(2) /* 1b */ 742 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU1_LSB BIT(5) /* 1b */ 743 #define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB BIT(31) /* 1b */ 744 /* SPM_CPU2_PWR_CON (0x1C001000+0x270) */ 745 #define MP0_SPMC_PWR_ON_CPU2_LSB BIT(2) /* 1b */ 746 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU2_LSB BIT(5) /* 1b */ 747 #define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB BIT(31) /* 1b */ 748 /* SPM_CPU3_PWR_CON (0x1C001000+0x274) */ 749 #define MP0_SPMC_PWR_ON_CPU3_LSB BIT(2) /* 1b */ 750 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU3_LSB BIT(5) /* 1b */ 751 #define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB BIT(31) /* 1b */ 752 /* SPM_CPU4_PWR_CON (0x1C001000+0x278) */ 753 #define MP0_SPMC_PWR_ON_CPU4_LSB BIT(2) /* 1b */ 754 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU4_LSB BIT(5) /* 1b */ 755 #define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB BIT(31) /* 1b */ 756 /* SPM_CPU5_PWR_CON (0x1C001000+0x27C) */ 757 #define MP0_SPMC_PWR_ON_CPU5_LSB BIT(2) /* 1b */ 758 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU5_LSB BIT(5) /* 1b */ 759 #define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB BIT(31) /* 1b */ 760 /* SPM_CPU6_PWR_CON (0x1C001000+0x280) */ 761 #define MP0_SPMC_PWR_ON_CPU6_LSB BIT(2) /* 1b */ 762 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU6_LSB BIT(5) /* 1b */ 763 #define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB BIT(31) /* 1b */ 764 /* SPM_CPU7_PWR_CON (0x1C001000+0x284) */ 765 #define MP0_SPMC_PWR_ON_CPU7_LSB BIT(2) /* 1b */ 766 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU7_LSB BIT(5) /* 1b */ 767 #define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB BIT(31) /* 1b */ 768 /* SPM_MCUPM_SPMC_CON (0x1C001000+0x288) */ 769 #define CPUEB_STATE_VALID_LSB BIT(0) /* 1b */ 770 #define REQ_PWR_ON_LSB BIT(1) /* 1b */ 771 #define REQ_MEM_RET_LSB BIT(2) /* 1b */ 772 #define RESET_PWR_ON_LSB BIT(4) /* 1b */ 773 #define RESET_MEM_RET_LSB BIT(5) /* 1b */ 774 #define CPUEB_STATE_FINISH_ACK_LSB BIT(31) /* 1b */ 775 /* SPM_DPM_P2P_STA (0x1C001000+0x2A0) */ 776 #define P2P_TX_STA_LSB BIT(0) /* 32b */ 777 /* SPM_DPM_P2P_CON (0x1C001000+0x2A4) */ 778 #define REG_P2P_TX_ERROR_FLAG_EN_LSB BIT(0) /* 1b */ 779 /* SPM_DPM_INTF_STA (0x1C001000+0x2A8) */ 780 #define SC_HW_S1_REQ_LSB BIT(0) /* 1b */ 781 #define REG_HW_S1_ACK_MASK_LSB BIT(4) /* 4b */ 782 #define SC_HW_S1_ACK_LSB BIT(8) /* 4b */ 783 /* SPM_DPM_WB_CON (0x1C001000+0x2AC) */ 784 #define REG_DPM_WB_EN_LSB BIT(0) /* 1b */ 785 /* SPM_ACK_CHK_TIMER_3 (0x1C001000+0x2B0) */ 786 #define SPM_ACK_CHK_TIMER_VAL_3_LSB BIT(0) /* 16b */ 787 #define SPM_ACK_CHK_TIMER_3_LSB BIT(16) /* 16b */ 788 /* SPM_ACK_CHK_STA_3 (0x1C001000+0x2B4) */ 789 #define SPM_ACK_CHK_STA_3_LSB BIT(0) /* 32b */ 790 /* SPM_PWRAP_CON (0x1C001000+0x300) */ 791 #define SPM_PWRAP_CON_LSB BIT(0) /* 32b */ 792 /* SPM_PWRAP_CON_STA (0x1C001000+0x304) */ 793 #define SPM_PWRAP_CON_STA_LSB BIT(0) /* 32b */ 794 /* SPM_PMIC_SPMI_CON (0x1C001000+0x308) */ 795 #define SPM_PMIC_SPMI_CMD_LSB BIT(0) /* 2b */ 796 #define SPM_PMIC_SPMI_SLAVEID_LSB BIT(2) /* 4b */ 797 #define SPM_PMIC_SPMI_PMIFID_LSB BIT(6) /* 1b */ 798 #define SPM_PMIC_SPMI_DBCNT_LSB BIT(7) /* 1b */ 799 /* SPM_PWRAP_CMD0 (0x1C001000+0x310) */ 800 #define SPM_PWRAP_CMD0_LSB BIT(0) /* 32b */ 801 /* SPM_PWRAP_CMD1 (0x1C001000+0x314) */ 802 #define SPM_PWRAP_CMD1_LSB BIT(0) /* 32b */ 803 /* SPM_PWRAP_CMD2 (0x1C001000+0x318) */ 804 #define SPM_PWRAP_CMD2_LSB BIT(0) /* 32b */ 805 /* SPM_PWRAP_CMD3 (0x1C001000+0x31C) */ 806 #define SPM_PWRAP_CMD3_LSB BIT(0) /* 32b */ 807 /* SPM_PWRAP_CMD4 (0x1C001000+0x320) */ 808 #define SPM_PWRAP_CMD4_LSB BIT(0) /* 32b */ 809 /* SPM_PWRAP_CMD5 (0x1C001000+0x324) */ 810 #define SPM_PWRAP_CMD5_LSB BIT(0) /* 32b */ 811 /* SPM_PWRAP_CMD6 (0x1C001000+0x328) */ 812 #define SPM_PWRAP_CMD6_LSB BIT(0) /* 32b */ 813 /* SPM_PWRAP_CMD7 (0x1C001000+0x32C) */ 814 #define SPM_PWRAP_CMD7_LSB BIT(0) /* 32b */ 815 /* SPM_PWRAP_CMD8 (0x1C001000+0x330) */ 816 #define SPM_PWRAP_CMD8_LSB BIT(0) /* 32b */ 817 /* SPM_PWRAP_CMD9 (0x1C001000+0x334) */ 818 #define SPM_PWRAP_CMD9_LSB BIT(0) /* 32b */ 819 /* SPM_PWRAP_CMD10 (0x1C001000+0x338) */ 820 #define SPM_PWRAP_CMD10_LSB BIT(0) /* 32b */ 821 /* SPM_PWRAP_CMD11 (0x1C001000+0x33C) */ 822 #define SPM_PWRAP_CMD11_LSB BIT(0) /* 32b */ 823 /* SPM_PWRAP_CMD12 (0x1C001000+0x340) */ 824 #define SPM_PWRAP_CMD12_LSB BIT(0) /* 32b */ 825 /* SPM_PWRAP_CMD13 (0x1C001000+0x344) */ 826 #define SPM_PWRAP_CMD13_LSB BIT(0) /* 32b */ 827 /* SPM_PWRAP_CMD14 (0x1C001000+0x348) */ 828 #define SPM_PWRAP_CMD14_LSB BIT(0) /* 32b */ 829 /* SPM_PWRAP_CMD15 (0x1C001000+0x34C) */ 830 #define SPM_PWRAP_CMD15_LSB BIT(0) /* 32b */ 831 /* SPM_PWRAP_CMD16 (0x1C001000+0x350) */ 832 #define SPM_PWRAP_CMD16_LSB BIT(0) /* 32b */ 833 /* SPM_PWRAP_CMD17 (0x1C001000+0x354) */ 834 #define SPM_PWRAP_CMD17_LSB BIT(0) /* 32b */ 835 /* SPM_PWRAP_CMD18 (0x1C001000+0x358) */ 836 #define SPM_PWRAP_CMD18_LSB BIT(0) /* 32b */ 837 /* SPM_PWRAP_CMD19 (0x1C001000+0x35C) */ 838 #define SPM_PWRAP_CMD19_LSB BIT(0) /* 32b */ 839 /* SPM_PWRAP_CMD20 (0x1C001000+0x360) */ 840 #define SPM_PWRAP_CMD20_LSB BIT(0) /* 32b */ 841 /* SPM_PWRAP_CMD21 (0x1C001000+0x364) */ 842 #define SPM_PWRAP_CMD21_LSB BIT(0) /* 32b */ 843 /* SPM_PWRAP_CMD22 (0x1C001000+0x368) */ 844 #define SPM_PWRAP_CMD22_LSB BIT(0) /* 32b */ 845 /* SPM_PWRAP_CMD23 (0x1C001000+0x36C) */ 846 #define SPM_PWRAP_CMD23_LSB BIT(0) /* 32b */ 847 /* SPM_PWRAP_CMD24 (0x1C001000+0x370) */ 848 #define SPM_PWRAP_CMD24_LSB BIT(0) /* 32b */ 849 /* SPM_PWRAP_CMD25 (0x1C001000+0x374) */ 850 #define SPM_PWRAP_CMD25_LSB BIT(0) /* 32b */ 851 /* SPM_PWRAP_CMD26 (0x1C001000+0x378) */ 852 #define SPM_PWRAP_CMD26_LSB BIT(0) /* 32b */ 853 /* SPM_PWRAP_CMD27 (0x1C001000+0x37C) */ 854 #define SPM_PWRAP_CMD27_LSB BIT(0) /* 32b */ 855 /* SPM_PWRAP_CMD28 (0x1C001000+0x380) */ 856 #define SPM_PWRAP_CMD28_LSB BIT(0) /* 32b */ 857 /* SPM_PWRAP_CMD29 (0x1C001000+0x384) */ 858 #define SPM_PWRAP_CMD29_LSB BIT(0) /* 32b */ 859 /* SPM_PWRAP_CMD30 (0x1C001000+0x388) */ 860 #define SPM_PWRAP_CMD30_LSB BIT(0) /* 32b */ 861 /* SPM_PWRAP_CMD31 (0x1C001000+0x38C) */ 862 #define SPM_PWRAP_CMD31_LSB BIT(0) /* 32b */ 863 /* DVFSRC_EVENT_STA (0x1C001000+0x390) */ 864 #define DVFSRC_EVENT_LSB BIT(0) /* 32b */ 865 /* SPM_FORCE_DVFS (0x1C001000+0x394) */ 866 #define FORCE_DVFS_LEVEL_LSB BIT(0) /* 32b */ 867 /* SPM_DVFS_STA (0x1C001000+0x398) */ 868 #define TARGET_DVFS_LEVEL_LSB BIT(0) /* 32b */ 869 /* SPM_DVS_DFS_LEVEL (0x1C001000+0x39C) */ 870 #define SPM_DFS_LEVEL_LSB BIT(0) /* 16b */ 871 #define SPM_DVS_LEVEL_LSB BIT(16) /* 16b */ 872 /* SPM_DVFS_LEVEL (0x1C001000+0x3A0) */ 873 #define SPM_DVFS_LEVEL_LSB BIT(0) /* 32b */ 874 /* SPM_DVFS_OPP (0x1C001000+0x3A4) */ 875 #define SPM_DVFS_OPP_LSB BIT(0) /* 5b */ 876 /* SPM_ULTRA_REQ (0x1C001000+0x3A8) */ 877 #define SPM2MM_FORCE_ULTRA_LSB BIT(0) /* 1b */ 878 #define SPM2MM_DBL_OSTD_ACT_LSB BIT(1) /* 1b */ 879 #define SPM2MM_ULTRAREQ_LSB BIT(2) /* 1b */ 880 #define SPM2MD_ULTRAREQ_LSB BIT(3) /* 1b */ 881 #define SPM2ISP_ULTRAREQ_LSB BIT(4) /* 1b */ 882 #define SPM2ISP_ULTRAACK_D2T_LSB BIT(18) /* 1b */ 883 #define SPM2MM_ULTRAACK_D2T_LSB BIT(19) /* 1b */ 884 #define SPM2MD_ULTRAACK_D2T_LSB BIT(20) /* 1b */ 885 /* SPM_DVFS_CON (0x1C001000+0x3AC) */ 886 #define SPM_DVFS_FORCE_ENABLE_LSB BIT(2) /* 1b */ 887 #define FORCE_DVFS_WAKE_LSB BIT(3) /* 1b */ 888 #define SPM_DVFSRC_ENABLE_LSB BIT(4) /* 1b */ 889 #define DVFSRC_WAKEUP_EVENT_MASK_LSB BIT(6) /* 1b */ 890 #define SPM2RC_EVENT_ABORT_LSB BIT(7) /* 1b */ 891 #define DVFSRC_LEVEL_ACK_LSB BIT(8) /* 1b */ 892 /* SPM_SRAMRC_CON (0x1C001000+0x3B0) */ 893 #define VSRAM_GEAR_REQ_LSB BIT(0) /* 1b */ 894 #define VSRAM_GEAR_RDY_LSB BIT(4) /* 1b */ 895 #define VSRAM_VAL_LEVEL_LSB BIT(16) /* 8b */ 896 /* SPM_SRCLKENRC_CON (0x1C001000+0x3B4) */ 897 #define SPM_PMIF_VALID_LSB BIT(0) /* 1b */ 898 #define SPM_PMIF_ACK_LSB BIT(4) /* 1b */ 899 /* SPM_DPSW_CON (0x1C001000+0x3B8) */ 900 #define DPSW_VLOGIC_REQ_LSB BIT(0) /* 1b */ 901 #define DPSW_VLOGIC_ISO_LSB BIT(4) /* 1b */ 902 #define DPSW_VLOGIC_ACK_LSB BIT(8) /* 1b */ 903 #define DPSW_VSRAM_ACK_LSB BIT(12) /* 1b */ 904 /* ULPOSC_CON (0x1C001000+0x400) */ 905 #define ULPOSC_EN_LSB BIT(0) /* 1b */ 906 #define ULPOSC_RST_LSB BIT(1) /* 1b */ 907 #define ULPOSC_CG_EN_LSB BIT(2) /* 1b */ 908 #define ULPOSC_CLK_SEL_LSB BIT(3) /* 1b */ 909 /* AP_MDSRC_REQ (0x1C001000+0x404) */ 910 #define AP_MDSMSRC_REQ_LSB BIT(0) /* 1b */ 911 #define AP_L1SMSRC_REQ_LSB BIT(1) /* 1b */ 912 #define AP2MD_PEER_WAKEUP_LSB BIT(3) /* 1b */ 913 #define AP_MDSMSRC_ACK_LSB BIT(4) /* 1b */ 914 #define AP_L1SMSRC_ACK_LSB BIT(5) /* 1b */ 915 /* SPM2MD_SWITCH_CTRL (0x1C001000+0x408) */ 916 #define SPM2MD_SWITCH_CTRL_LSB BIT(0) /* 10b */ 917 /* RC_SPM_CTRL (0x1C001000+0x40C) */ 918 #define SPM_AP_26M_RDY_LSB BIT(0) /* 1b */ 919 #define SPM2RC_DMY_CTRL_LSB BIT(2) /* 6b */ 920 #define RC2SPM_SRCCLKENO_0_ACK_LSB BIT(16) /* 1b */ 921 /* SPM2GPUPM_CON (0x1C001000+0x410) */ 922 #define SPM2GPUEB_SW_RST_B_LSB BIT(0) /* 1b */ 923 #define SPM2GPUEB_SW_INT_LSB BIT(1) /* 1b */ 924 #define SC_MFG_PLL_EN_LSB BIT(4) /* 1b */ 925 #define GPUEB_WFI_LSB BIT(16) /* 1b */ 926 /* SPM2APU_CON (0x1C001000+0x414) */ 927 #define RPC_SRAM_CTRL_MUX_SEL_LSB BIT(0) /* 1b */ 928 #define APU_VCORE_OFF_ISO_EN_LSB BIT(1) /* 1b */ 929 #define APU_ARE_REQ_LSB BIT(4) /* 1b */ 930 #define APU_ARE_ACK_LSB BIT(8) /* 1b */ 931 #define APU_ACTIVE_STATE_LSB BIT(9) /* 1b */ 932 #define APU_AOV_WAKEUP_LSB BIT(16) /* 1b */ 933 /* SPM2EFUSE_CON (0x1C001000+0x418) */ 934 #define AOC_EFUSE_EN_LSB BIT(0) /* 1b */ 935 #define AOC_EFUSE_RESTORE_RDY_LSB BIT(1) /* 1b */ 936 /* SPM2DFD_CON (0x1C001000+0x41C) */ 937 #define DFD_SOC_MTCMOS_ACK_LSB BIT(0) /* 1b */ 938 #define DFD_SOC_MTCMOS_REQ_LSB BIT(1) /* 1b */ 939 /* RSV_PLL_CON (0x1C001000+0x420) */ 940 #define SC_UNIVPLL_EN_LSB BIT(0) /* 1b */ 941 #define SC_MMPLL_EN_LSB BIT(1) /* 1b */ 942 #define SC_RSV_PLL_EN_LSB BIT(2) /* 14b */ 943 #define APU_26M_CLK_EN_LSB BIT(16) /* 1b */ 944 #define IFR_26M_CLK_EN_LSB BIT(17) /* 1b */ 945 #define VLP_26M2ULPOSC_EN_LSB BIT(18) /* 1b */ 946 #define SC_RSV_CLK_EN_LSB BIT(20) /* 12b */ 947 /* EMI_SLB_CON (0x1C001000+0x424) */ 948 #define EMI_SLB_MODE_MASK_LSB BIT(0) /* 1b */ 949 #define SPM2EMI_SLP_PROT_EN_LSB BIT(1) /* 1b */ 950 #define SPM2EMI_SLP_PROT_SRC_LSB BIT(2) /* 1b */ 951 #define EMI_DRAMC_MD32_SLEEP_IDLE_LSB BIT(4) /* 2b */ 952 #define EMI_SLB_ONLY_MODE_LSB BIT(8) /* 2b */ 953 /* SPM_SUSPEND_FLAG_CON (0x1C001000+0x428) */ 954 #define SPM_SUSPEND_RESUME_FLAG_LSB BIT(0) /* 1b */ 955 /* SPM2PMSR_CON (0x1C001000+0x42C) */ 956 #define SPM2PMSR_DRAMC_S0_FLAG_LSB BIT(0) /* 1b */ 957 #define SPM2PMSR_SYSTEM_POWER_STATE_LSB BIT(4) /* 8b */ 958 /* SPM_TOPCK_RTFF_CON (0x1C001000+0x430) */ 959 #define SPM_CKSYS_RTFF_DIVIDER_RST_LSB BIT(0) /* 1b */ 960 #define SPM_32K_VCORE_CLK_EN_LSB BIT(1) /* 1b */ 961 #define SPM_ULPOSC_VCORE_CLK_EN_LSB BIT(2) /* 1b */ 962 /* EMI_SHF_CON (0x1C001000+0x434) */ 963 #define SPM2EMI_SHF_REQ_LSB BIT(0) /* 2b */ 964 #define SPM2EMI_SHF_REQ_ACK_LSB BIT(4) /* 2b */ 965 /* CIRQ_BYPASS_CON (0x1C001000+0x438) */ 966 #define SPM_CIRQ_BYPASS_MODE_EN_LSB BIT(0) /* 1b */ 967 /* AOC_VCORE_SRAM_CON (0x1C001000+0x43C) */ 968 #define AOC_VCORE_SRAM_PDN_EN_LSB BIT(0) /* 1b */ 969 #define AOC_VCORE_SRAM_PDN_SHIFT_LSB BIT(1) /* 1b */ 970 /* REG_MODULE_SW_CG_DDREN_REQ_MASK_0 (0x1C001000+0x460) */ 971 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_0_LSB BIT(0) /* 32b */ 972 /* REG_MODULE_SW_CG_DDREN_REQ_MASK_1 (0x1C001000+0x464) */ 973 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_1_LSB BIT(0) /* 32b */ 974 /* REG_MODULE_SW_CG_DDREN_REQ_MASK_2 (0x1C001000+0x468) */ 975 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_2_LSB BIT(0) /* 32b */ 976 /* REG_MODULE_SW_CG_DDREN_REQ_MASK_3 (0x1C001000+0x46C) */ 977 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_3_LSB BIT(0) /* 32b */ 978 /* REG_MODULE_SW_CG_VRF18_REQ_MASK_0 (0x1C001000+0x470) */ 979 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_0_LSB BIT(0) /* 32b */ 980 /* REG_MODULE_SW_CG_VRF18_REQ_MASK_1 (0x1C001000+0x474) */ 981 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_1_LSB BIT(0) /* 32b */ 982 /* REG_MODULE_SW_CG_VRF18_REQ_MASK_2 (0x1C001000+0x478) */ 983 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_2_LSB BIT(0) /* 32b */ 984 /* REG_MODULE_SW_CG_VRF18_REQ_MASK_3 (0x1C001000+0x47C) */ 985 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_3_LSB BIT(0) /* 32b */ 986 /* REG_MODULE_SW_CG_INFRA_REQ_MASK_0 (0x1C001000+0x480) */ 987 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_0_LSB BIT(0) /* 32b */ 988 /* REG_MODULE_SW_CG_INFRA_REQ_MASK_1 (0x1C001000+0x484) */ 989 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_1_LSB BIT(0) /* 32b */ 990 /* REG_MODULE_SW_CG_INFRA_REQ_MASK_2 (0x1C001000+0x488) */ 991 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_2_LSB BIT(0) /* 32b */ 992 /* REG_MODULE_SW_CG_INFRA_REQ_MASK_3 (0x1C001000+0x48C) */ 993 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_3_LSB BIT(0) /* 32b */ 994 /* REG_MODULE_SW_CG_F26M_REQ_MASK_0 (0x1C001000+0x490) */ 995 #define REG_MODULE_SW_CG_F26M_REQ_MASK_0_LSB BIT(0) /* 32b */ 996 /* REG_MODULE_SW_CG_F26M_REQ_MASK_1 (0x1C001000+0x494) */ 997 #define REG_MODULE_SW_CG_F26M_REQ_MASK_1_LSB BIT(0) /* 32b */ 998 /* REG_MODULE_SW_CG_F26M_REQ_MASK_2 (0x1C001000+0x498) */ 999 #define REG_MODULE_SW_CG_F26M_REQ_MASK_2_LSB BIT(0) /* 32b */ 1000 /* REG_MODULE_SW_CG_F26M_REQ_MASK_3 (0x1C001000+0x49C) */ 1001 #define REG_MODULE_SW_CG_F26M_REQ_MASK_3_LSB BIT(0) /* 32b */ 1002 /* REG_MODULE_SW_CG_VCORE_REQ_MASK_0 (0x1C001000+0x4A0) */ 1003 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_0_LSB BIT(0) /* 32b */ 1004 /* REG_MODULE_SW_CG_VCORE_REQ_MASK_1 (0x1C001000+0x4A4) */ 1005 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_1_LSB BIT(0) /* 32b */ 1006 /* REG_MODULE_SW_CG_VCORE_REQ_MASK_2 (0x1C001000+0x4A8) */ 1007 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_2_LSB BIT(0) /* 32b */ 1008 /* REG_MODULE_SW_CG_VCORE_REQ_MASK_3 (0x1C001000+0x4AC) */ 1009 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_3_LSB BIT(0) /* 32b */ 1010 /* REG_PWR_STATUS_DDREN_REQ_MASK (0x1C001000+0x4B0) */ 1011 #define REG_PWR_STATUS_DDREN_REQ_MASK_LSB BIT(0) /* 32b */ 1012 /* REG_PWR_STATUS_VRF18_REQ_MASK (0x1C001000+0x4B4) */ 1013 #define REG_PWR_STATUS_VRF18_REQ_MASK_LSB BIT(0) /* 32b */ 1014 /* REG_PWR_STATUS_INFRA_REQ_MASK (0x1C001000+0x4B8) */ 1015 #define REG_PWR_STATUS_INFRA_REQ_MASK_LSB BIT(0) /* 32b */ 1016 /* REG_PWR_STATUS_F26M_REQ_MASK (0x1C001000+0x4BC) */ 1017 #define REG_PWR_STATUS_F26M_REQ_MASK_LSB BIT(0) /* 32b */ 1018 /* REG_PWR_STATUS_PMIC_REQ_MASK (0x1C001000+0x4C0) */ 1019 #define REG_PWR_STATUS_PMIC_REQ_MASK_LSB BIT(0) /* 32b */ 1020 /* REG_PWR_STATUS_VCORE_REQ_MASK (0x1C001000+0x4C4) */ 1021 #define REG_PWR_STATUS_VCORE_REQ_MASK_LSB BIT(0) /* 32b */ 1022 /* REG_PWR_STATUS_MSB_DDREN_REQ_MASK (0x1C001000+0x4C8) */ 1023 #define REG_PWR_STATUS_MSB_DDREN_REQ_MASK_LSB BIT(0) /* 32b */ 1024 /* REG_PWR_STATUS_MSB_VRF18_REQ_MASK (0x1C001000+0x4CC) */ 1025 #define REG_PWR_STATUS_MSB_VRF18_REQ_MASK_LSB BIT(0) /* 32b */ 1026 /* REG_PWR_STATUS_MSB_INFRA_REQ_MASK (0x1C001000+0x4D0) */ 1027 #define REG_PWR_STATUS_MSB_INFRA_REQ_MASK_LSB BIT(0) /* 32b */ 1028 /* REG_PWR_STATUS_MSB_F26M_REQ_MASK (0x1C001000+0x4D4) */ 1029 #define REG_PWR_STATUS_MSB_F26M_REQ_MASK_LSB BIT(0) /* 32b */ 1030 /* REG_PWR_STATUS_MSB_PMIC_REQ_MASK (0x1C001000+0x4D8) */ 1031 #define REG_PWR_STATUS_MSB_PMIC_REQ_MASK_LSB BIT(0) /* 32b */ 1032 /* REG_PWR_STATUS_MSB_VCORE_REQ_MASK (0x1C001000+0x4DC) */ 1033 #define REG_PWR_STATUS_MSB_VCORE_REQ_MASK_LSB BIT(0) /* 32b */ 1034 /* REG_MODULE_BUSY_DDREN_REQ_MASK (0x1C001000+0x4E0) */ 1035 #define REG_MODULE_BUSY_DDREN_REQ_MASK_LSB BIT(0) /* 32b */ 1036 /* REG_MODULE_BUSY_VRF18_REQ_MASK (0x1C001000+0x4E4) */ 1037 #define REG_MODULE_BUSY_VRF18_REQ_MASK_LSB BIT(0) /* 32b */ 1038 /* REG_MODULE_BUSY_INFRA_REQ_MASK (0x1C001000+0x4E8) */ 1039 #define REG_MODULE_BUSY_INFRA_REQ_MASK_LSB BIT(0) /* 32b */ 1040 /* REG_MODULE_BUSY_F26M_REQ_MASK (0x1C001000+0x4EC) */ 1041 #define REG_MODULE_BUSY_F26M_REQ_MASK_LSB BIT(0) /* 32b */ 1042 /* REG_MODULE_BUSY_PMIC_REQ_MASK (0x1C001000+0x4F0) */ 1043 #define REG_MODULE_BUSY_PMIC_REQ_MASK_LSB BIT(0) /* 32b */ 1044 /* REG_MODULE_BUSY_VCORE_REQ_MASK (0x1C001000+0x4F4) */ 1045 #define REG_MODULE_BUSY_VCORE_REQ_MASK_LSB BIT(0) /* 32b */ 1046 /* SYS_TIMER_CON (0x1C001000+0x500) */ 1047 #define SYS_TIMER_START_EN_LSB BIT(0) /* 1b */ 1048 #define SYS_TIMER_LATCH_EN_LSB BIT(1) /* 1b */ 1049 #define SYS_TIMER_ID_LSB BIT(8) /* 8b */ 1050 #define SYS_TIMER_VALID_LSB BIT(31) /* 1b */ 1051 /* SYS_TIMER_VALUE_L (0x1C001000+0x504) */ 1052 #define SYS_TIMER_VALUE_L_LSB BIT(0) /* 32b */ 1053 /* SYS_TIMER_VALUE_H (0x1C001000+0x508) */ 1054 #define SYS_TIMER_VALUE_H_LSB BIT(0) /* 32b */ 1055 /* SYS_TIMER_START_L (0x1C001000+0x50C) */ 1056 #define SYS_TIMER_START_L_LSB BIT(0) /* 32b */ 1057 /* SYS_TIMER_START_H (0x1C001000+0x510) */ 1058 #define SYS_TIMER_START_H_LSB BIT(0) /* 32b */ 1059 /* SYS_TIMER_LATCH_L_00 (0x1C001000+0x514) */ 1060 #define SYS_TIMER_LATCH_L_00_LSB BIT(0) /* 32b */ 1061 /* SYS_TIMER_LATCH_H_00 (0x1C001000+0x518) */ 1062 #define SYS_TIMER_LATCH_H_00_LSB BIT(0) /* 32b */ 1063 /* SYS_TIMER_LATCH_L_01 (0x1C001000+0x51C) */ 1064 #define SYS_TIMER_LATCH_L_01_LSB BIT(0) /* 32b */ 1065 /* SYS_TIMER_LATCH_H_01 (0x1C001000+0x520) */ 1066 #define SYS_TIMER_LATCH_H_01_LSB BIT(0) /* 32b */ 1067 /* SYS_TIMER_LATCH_L_02 (0x1C001000+0x524) */ 1068 #define SYS_TIMER_LATCH_L_02_LSB BIT(0) /* 32b */ 1069 /* SYS_TIMER_LATCH_H_02 (0x1C001000+0x528) */ 1070 #define SYS_TIMER_LATCH_H_02_LSB BIT(0) /* 32b */ 1071 /* SYS_TIMER_LATCH_L_03 (0x1C001000+0x52C) */ 1072 #define SYS_TIMER_LATCH_L_03_LSB BIT(0) /* 32b */ 1073 /* SYS_TIMER_LATCH_H_03 (0x1C001000+0x530) */ 1074 #define SYS_TIMER_LATCH_H_03_LSB BIT(0) /* 32b */ 1075 /* SYS_TIMER_LATCH_L_04 (0x1C001000+0x534) */ 1076 #define SYS_TIMER_LATCH_L_04_LSB BIT(0) /* 32b */ 1077 /* SYS_TIMER_LATCH_H_04 (0x1C001000+0x538) */ 1078 #define SYS_TIMER_LATCH_H_04_LSB BIT(0) /* 32b */ 1079 /* SYS_TIMER_LATCH_L_05 (0x1C001000+0x53C) */ 1080 #define SYS_TIMER_LATCH_L_05_LSB BIT(0) /* 32b */ 1081 /* SYS_TIMER_LATCH_H_05 (0x1C001000+0x540) */ 1082 #define SYS_TIMER_LATCH_H_05_LSB BIT(0) /* 32b */ 1083 /* SYS_TIMER_LATCH_L_06 (0x1C001000+0x544) */ 1084 #define SYS_TIMER_LATCH_L_06_LSB BIT(0) /* 32b */ 1085 /* SYS_TIMER_LATCH_H_06 (0x1C001000+0x548) */ 1086 #define SYS_TIMER_LATCH_H_06_LSB BIT(0) /* 32b */ 1087 /* SYS_TIMER_LATCH_L_07 (0x1C001000+0x54C) */ 1088 #define SYS_TIMER_LATCH_L_07_LSB BIT(0) /* 32b */ 1089 /* SYS_TIMER_LATCH_H_07 (0x1C001000+0x550) */ 1090 #define SYS_TIMER_LATCH_H_07_LSB BIT(0) /* 32b */ 1091 /* SYS_TIMER_LATCH_L_08 (0x1C001000+0x554) */ 1092 #define SYS_TIMER_LATCH_L_08_LSB BIT(0) /* 32b */ 1093 /* SYS_TIMER_LATCH_H_08 (0x1C001000+0x558) */ 1094 #define SYS_TIMER_LATCH_H_08_LSB BIT(0) /* 32b */ 1095 /* SYS_TIMER_LATCH_L_09 (0x1C001000+0x55C) */ 1096 #define SYS_TIMER_LATCH_L_09_LSB BIT(0) /* 32b */ 1097 /* SYS_TIMER_LATCH_H_09 (0x1C001000+0x560) */ 1098 #define SYS_TIMER_LATCH_H_09_LSB BIT(0) /* 32b */ 1099 /* SYS_TIMER_LATCH_L_10 (0x1C001000+0x564) */ 1100 #define SYS_TIMER_LATCH_L_10_LSB BIT(0) /* 32b */ 1101 /* SYS_TIMER_LATCH_H_10 (0x1C001000+0x568) */ 1102 #define SYS_TIMER_LATCH_H_10_LSB BIT(0) /* 32b */ 1103 /* SYS_TIMER_LATCH_L_11 (0x1C001000+0x56C) */ 1104 #define SYS_TIMER_LATCH_L_11_LSB BIT(0) /* 32b */ 1105 /* SYS_TIMER_LATCH_H_11 (0x1C001000+0x570) */ 1106 #define SYS_TIMER_LATCH_H_11_LSB BIT(0) /* 32b */ 1107 /* SYS_TIMER_LATCH_L_12 (0x1C001000+0x574) */ 1108 #define SYS_TIMER_LATCH_L_12_LSB BIT(0) /* 32b */ 1109 /* SYS_TIMER_LATCH_H_12 (0x1C001000+0x578) */ 1110 #define SYS_TIMER_LATCH_H_12_LSB BIT(0) /* 32b */ 1111 /* SYS_TIMER_LATCH_L_13 (0x1C001000+0x57C) */ 1112 #define SYS_TIMER_LATCH_L_13_LSB BIT(0) /* 32b */ 1113 /* SYS_TIMER_LATCH_H_13 (0x1C001000+0x580) */ 1114 #define SYS_TIMER_LATCH_H_13_LSB BIT(0) /* 32b */ 1115 /* SYS_TIMER_LATCH_L_14 (0x1C001000+0x584) */ 1116 #define SYS_TIMER_LATCH_L_14_LSB BIT(0) /* 32b */ 1117 /* SYS_TIMER_LATCH_H_14 (0x1C001000+0x588) */ 1118 #define SYS_TIMER_LATCH_H_14_LSB BIT(0) /* 32b */ 1119 /* SYS_TIMER_LATCH_L_15 (0x1C001000+0x58C) */ 1120 #define SYS_TIMER_LATCH_L_15_LSB BIT(0) /* 32b */ 1121 /* SYS_TIMER_LATCH_H_15 (0x1C001000+0x590) */ 1122 #define SYS_TIMER_LATCH_H_15_LSB BIT(0) /* 32b */ 1123 /* PCM_TIMER_VAL (0x1C001000+0x594) */ 1124 #define REG_PCM_TIMER_VAL_LSB BIT(0) /* 32b */ 1125 /* PCM_TIMER_OUT (0x1C001000+0x598) */ 1126 #define PCM_TIMER_LSB BIT(0) /* 32b */ 1127 /* SPM_COUNTER_0 (0x1C001000+0x59C) */ 1128 #define SPM_COUNTER_VAL_0_LSB BIT(0) /* 14b */ 1129 #define SPM_COUNTER_OUT_0_LSB BIT(14) /* 14b */ 1130 #define SPM_COUNTER_EN_0_LSB BIT(28) /* 1b */ 1131 #define SPM_COUNTER_CLR_0_LSB BIT(29) /* 1b */ 1132 #define SPM_COUNTER_TIMEOUT_0_LSB BIT(30) /* 1b */ 1133 #define SPM_COUNTER_WAKEUP_EN_0_LSB BIT(31) /* 1b */ 1134 /* SPM_COUNTER_1 (0x1C001000+0x5A0) */ 1135 #define SPM_COUNTER_VAL_1_LSB BIT(0) /* 14b */ 1136 #define SPM_COUNTER_OUT_1_LSB BIT(14) /* 14b */ 1137 #define SPM_COUNTER_EN_1_LSB BIT(28) /* 1b */ 1138 #define SPM_COUNTER_CLR_1_LSB BIT(29) /* 1b */ 1139 #define SPM_COUNTER_TIMEOUT_1_LSB BIT(30) /* 1b */ 1140 #define SPM_COUNTER_WAKEUP_EN_1_LSB BIT(31) /* 1b */ 1141 /* SPM_COUNTER_2 (0x1C001000+0x5A4) */ 1142 #define SPM_COUNTER_VAL_2_LSB BIT(0) /* 14b */ 1143 #define SPM_COUNTER_OUT_2_LSB BIT(14) /* 14b */ 1144 #define SPM_COUNTER_EN_2_LSB BIT(28) /* 1b */ 1145 #define SPM_COUNTER_CLR_2_LSB BIT(29) /* 1b */ 1146 #define SPM_COUNTER_TIMEOUT_2_LSB BIT(30) /* 1b */ 1147 #define SPM_COUNTER_WAKEUP_EN_2_LSB BIT(31) /* 1b */ 1148 /* PCM_WDT_VAL (0x1C001000+0x5A8) */ 1149 #define REG_PCM_WDT_VAL_LSB BIT(0) /* 32b */ 1150 /* PCM_WDT_OUT (0x1C001000+0x5AC) */ 1151 #define PCM_WDT_TIMER_VAL_OUT_LSB BIT(0) /* 32b */ 1152 /* SPM_SW_FLAG_0 (0x1C001000+0x600) */ 1153 #define SPM_SW_FLAG_LSB BIT(0) /* 32b */ 1154 /* SPM_SW_DEBUG_0 (0x1C001000+0x604) */ 1155 #define SPM_SW_DEBUG_0_LSB BIT(0) /* 32b */ 1156 /* SPM_SW_FLAG_1 (0x1C001000+0x608) */ 1157 #define SPM_SW_FLAG_1_LSB BIT(0) /* 32b */ 1158 /* SPM_SW_DEBUG_1 (0x1C001000+0x60C) */ 1159 #define SPM_SW_DEBUG_1_LSB BIT(0) /* 32b */ 1160 /* SPM_SW_RSV_0 (0x1C001000+0x610) */ 1161 #define SPM_SW_RSV_0_LSB BIT(0) /* 32b */ 1162 /* SPM_SW_RSV_1 (0x1C001000+0x614) */ 1163 #define SPM_SW_RSV_1_LSB BIT(0) /* 32b */ 1164 /* SPM_SW_RSV_2 (0x1C001000+0x618) */ 1165 #define SPM_SW_RSV_2_LSB BIT(0) /* 32b */ 1166 /* SPM_SW_RSV_3 (0x1C001000+0x61C) */ 1167 #define SPM_SW_RSV_3_LSB BIT(0) /* 32b */ 1168 /* SPM_SW_RSV_4 (0x1C001000+0x620) */ 1169 #define SPM_SW_RSV_4_LSB BIT(0) /* 32b */ 1170 /* SPM_SW_RSV_5 (0x1C001000+0x624) */ 1171 #define SPM_SW_RSV_5_LSB BIT(0) /* 32b */ 1172 /* SPM_SW_RSV_6 (0x1C001000+0x628) */ 1173 #define SPM_SW_RSV_6_LSB BIT(0) /* 32b */ 1174 /* SPM_SW_RSV_7 (0x1C001000+0x62C) */ 1175 #define SPM_SW_RSV_7_LSB BIT(0) /* 32b */ 1176 /* SPM_SW_RSV_8 (0x1C001000+0x630) */ 1177 #define SPM_SW_RSV_8_LSB BIT(0) /* 32b */ 1178 /* SPM_BK_WAKE_EVENT (0x1C001000+0x634) */ 1179 #define SPM_BK_WAKE_EVENT_LSB BIT(0) /* 32b */ 1180 /* SPM_BK_VTCXO_DUR (0x1C001000+0x638) */ 1181 #define SPM_BK_VTCXO_DUR_LSB BIT(0) /* 32b */ 1182 /* SPM_BK_WAKE_MISC (0x1C001000+0x63C) */ 1183 #define SPM_BK_WAKE_MISC_LSB BIT(0) /* 32b */ 1184 /* SPM_BK_PCM_TIMER (0x1C001000+0x640) */ 1185 #define SPM_BK_PCM_TIMER_LSB BIT(0) /* 32b */ 1186 /* SPM_RSV_CON_0 (0x1C001000+0x650) */ 1187 #define SPM_RSV_CON_0_LSB BIT(0) /* 32b */ 1188 /* SPM_RSV_CON_1 (0x1C001000+0x654) */ 1189 #define SPM_RSV_CON_1_LSB BIT(0) /* 32b */ 1190 /* SPM_RSV_STA_0 (0x1C001000+0x658) */ 1191 #define SPM_RSV_STA_0_LSB BIT(0) /* 32b */ 1192 /* SPM_RSV_STA_1 (0x1C001000+0x65C) */ 1193 #define SPM_RSV_STA_1_LSB BIT(0) /* 32b */ 1194 /* SPM_SPARE_CON (0x1C001000+0x660) */ 1195 #define SPM_SPARE_CON_LSB BIT(0) /* 32b */ 1196 /* SPM_SPARE_CON_SET (0x1C001000+0x664) */ 1197 #define SPM_SPARE_CON_SET_LSB BIT(0) /* 32b */ 1198 /* SPM_SPARE_CON_CLR (0x1C001000+0x668) */ 1199 #define SPM_SPARE_CON_CLR_LSB BIT(0) /* 32b */ 1200 /* SPM_CROSS_WAKE_M00_REQ (0x1C001000+0x66C) */ 1201 #define SPM_M0_CROSS_WAKE_REQ_LSB BIT(0) /* 4b */ 1202 #define SPM_CROSS_WAKE_M0_CHK_LSB BIT(4) /* 4b */ 1203 /* SPM_CROSS_WAKE_M01_REQ (0x1C001000+0x670) */ 1204 #define SPM_M1_CROSS_WAKE_REQ_LSB BIT(0) /* 4b */ 1205 #define SPM_CROSS_WAKE_M1_CHK_LSB BIT(4) /* 4b */ 1206 /* SPM_CROSS_WAKE_M02_REQ (0x1C001000+0x674) */ 1207 #define SPM_M2_CROSS_WAKE_REQ_LSB BIT(0) /* 4b */ 1208 #define SPM_CROSS_WAKE_M2_CHK_LSB BIT(4) /* 4b */ 1209 /* SPM_CROSS_WAKE_M03_REQ (0x1C001000+0x678) */ 1210 #define SPM_M3_CROSS_WAKE_REQ_LSB BIT(0) /* 4b */ 1211 #define SPM_CROSS_WAKE_M3_CHK_LSB BIT(4) /* 4b */ 1212 /* SCP_VCORE_LEVEL (0x1C001000+0x67C) */ 1213 #define SCP_VCORE_LEVEL_LSB BIT(0) /* 16b */ 1214 /* SPM_DDREN_ACK_SEL_CON (0x1C001000+0x680) */ 1215 #define SPM_DDREN_ACK_SEL_OTHERS_LSB BIT(0) /* 1b */ 1216 #define SPM_DDREN_ACK_SEL_MCU_LSB BIT(1) /* 1b */ 1217 /* SPM_SW_FLAG_2 (0x1C001000+0x684) */ 1218 #define SPM_SW_FLAG_2_LSB BIT(0) /* 32b */ 1219 /* SPM_SW_DEBUG_2 (0x1C001000+0x688) */ 1220 #define SPM_SW_DEBUG_2_LSB BIT(0) /* 32b */ 1221 /* SPM_DV_CON_0 (0x1C001000+0x68C) */ 1222 #define SPM_DV_CON_0_LSB BIT(0) /* 32b */ 1223 /* SPM_DV_CON_1 (0x1C001000+0x690) */ 1224 #define SPM_DV_CON_1_LSB BIT(0) /* 32b */ 1225 /* SPM_SEMA_M0 (0x1C001000+0x69C) */ 1226 #define SPM_SEMA_M0_LSB BIT(0) /* 8b */ 1227 /* SPM_SEMA_M1 (0x1C001000+0x6A0) */ 1228 #define SPM_SEMA_M1_LSB BIT(0) /* 8b */ 1229 /* SPM_SEMA_M2 (0x1C001000+0x6A4) */ 1230 #define SPM_SEMA_M2_LSB BIT(0) /* 8b */ 1231 /* SPM_SEMA_M3 (0x1C001000+0x6A8) */ 1232 #define SPM_SEMA_M3_LSB BIT(0) /* 8b */ 1233 /* SPM_SEMA_M4 (0x1C001000+0x6AC) */ 1234 #define SPM_SEMA_M4_LSB BIT(0) /* 8b */ 1235 /* SPM_SEMA_M5 (0x1C001000+0x6B0) */ 1236 #define SPM_SEMA_M5_LSB BIT(0) /* 8b */ 1237 /* SPM_SEMA_M6 (0x1C001000+0x6B4) */ 1238 #define SPM_SEMA_M6_LSB BIT(0) /* 8b */ 1239 /* SPM_SEMA_M7 (0x1C001000+0x6B8) */ 1240 #define SPM_SEMA_M7_LSB BIT(0) /* 8b */ 1241 /* SPM2ADSP_MAILBOX (0x1C001000+0x6BC) */ 1242 #define SPM2ADSP_MAILBOX_LSB BIT(0) /* 32b */ 1243 /* ADSP2SPM_MAILBOX (0x1C001000+0x6C0) */ 1244 #define ADSP2SPM_MAILBOX_LSB BIT(0) /* 32b */ 1245 /* VCORE_RTFF_CTRL_MASK_SET (0x1C001000+0x6C4) */ 1246 #define VCORE_RTFF_CTRL_MASK_LSB BIT(0) /* 32b */ 1247 /* VCORE_RTFF_CTRL_MASK_CLR (0x1C001000+0x6C8) */ 1248 #define VCORE_RTFF_CTRL_MASK_CLR_VCORE_RTFF_CTRL_MASK_LSB BIT(0) /* 32b */ 1249 /* SPM2PMCU_MAILBOX_0 (0x1C001000+0x6CC) */ 1250 #define SPM2PMCU_MAILBOX_0_LSB BIT(0) /* 32b */ 1251 /* SPM2PMCU_MAILBOX_1 (0x1C001000+0x6D0) */ 1252 #define SPM2PMCU_MAILBOX_1_LSB BIT(0) /* 32b */ 1253 /* SPM2PMCU_MAILBOX_2 (0x1C001000+0x6D4) */ 1254 #define SPM2PMCU_MAILBOX_2_LSB BIT(0) /* 32b */ 1255 /* SPM2PMCU_MAILBOX_3 (0x1C001000+0x6D8) */ 1256 #define SPM2PMCU_MAILBOX_3_LSB BIT(0) /* 32b */ 1257 /* PMCU2SPM_MAILBOX_0 (0x1C001000+0x6DC) */ 1258 #define PMCU2SPM_MAILBOX_0_LSB BIT(0) /* 32b */ 1259 /* PMCU2SPM_MAILBOX_1 (0x1C001000+0x6E0) */ 1260 #define PMCU2SPM_MAILBOX_1_LSB BIT(0) /* 32b */ 1261 /* PMCU2SPM_MAILBOX_2 (0x1C001000+0x6E4) */ 1262 #define PMCU2SPM_MAILBOX_2_LSB BIT(0) /* 32b */ 1263 /* PMCU2SPM_MAILBOX_3 (0x1C001000+0x6E8) */ 1264 #define PMCU2SPM_MAILBOX_3_LSB BIT(0) /* 32b */ 1265 /* SPM2SCP_MAILBOX (0x1C001000+0x6EC) */ 1266 #define SPM_SCP_MAILBOX_LSB BIT(0) /* 32b */ 1267 /* SCP2SPM_MAILBOX (0x1C001000+0x6F0) */ 1268 #define SCP_SPM_MAILBOX_LSB BIT(0) /* 32b */ 1269 /* SCP_AOV_BUS_CON (0x1C001000+0x6F4) */ 1270 #define SCP_AOV_BUS_REQ_LSB BIT(0) /* 1b */ 1271 #define SCP_AOV_BUS_ACK_LSB BIT(8) /* 1b */ 1272 /* VCORE_RTFF_CTRL_MASK (0x1C001000+0x6F8) */ 1273 #define VCORE_RTFF_CTRL_MASK_VCORE_RTFF_CTRL_MASK_LSB BIT(0) /* 32b */ 1274 /* SPM_SRAM_SRCLKENO_MASK (0x1C001000+0x6FC) */ 1275 #define SPM_SRAM_SRCLKENO_MASK_LSB BIT(0) /* 1b */ 1276 /* EMI_PDN_REQ (0x1C001000+0x700) */ 1277 #define EMI_PDN_REQ_LSB BIT(0) /* 32b */ 1278 /* EMI_BUSY_REQ (0x1C001000+0x704) */ 1279 #define EMI_BUSY_REQ_LSB BIT(0) /* 32b */ 1280 /* EMI_RESERVED_STA (0x1C001000+0x708) */ 1281 #define EMI_RESERVED_STA_LSB BIT(0) /* 32b */ 1282 /* SC_UNIVPLL_DIV_RST_B (0x1C001000+0x70C) */ 1283 #define SC_UNIVPLL_DIV_RST_B_LSB BIT(0) /* 32b */ 1284 /* ECO_ARMPLL_DIV_CLOCK_OFF (0x1C001000+0x710) */ 1285 #define ECO_ARMPLL_DIV_CLOCK_OFF_LSB BIT(0) /* 32b */ 1286 /* SPM_MCDSR_CG_CHECK_X1 (0x1C001000+0x714) */ 1287 #define SPM_MCDSR_CG_CHECK_X1_LSB BIT(0) /* 32b */ 1288 /* SPM_SODI2_CG_CHECK_X1 (0x1C001000+0x718) */ 1289 #define SPM_SODI2_CG_CHECK_X1_LSB BIT(0) /* 32b */ 1290 /* SPM_WAKEUP_STA (0x1C001000+0x800) */ 1291 #define SPM_WAKEUP_EVENT_L_LSB BIT(0) /* 32b */ 1292 /* SPM_WAKEUP_EXT_STA (0x1C001000+0x804) */ 1293 #define EXT_WAKEUP_EVENT_LSB BIT(0) /* 32b */ 1294 /* SPM_WAKEUP_EVENT_MASK (0x1C001000+0x808) */ 1295 #define REG_WAKEUP_EVENT_MASK_LSB BIT(0) /* 32b */ 1296 /* SPM_WAKEUP_EVENT_EXT_MASK (0x1C001000+0x80C) */ 1297 #define REG_EXT_WAKEUP_EVENT_MASK_LSB BIT(0) /* 32b */ 1298 /* SPM_WAKEUP_EVENT_SENS (0x1C001000+0x810) */ 1299 #define REG_WAKEUP_EVENT_SENS_LSB BIT(0) /* 32b */ 1300 /* SPM_WAKEUP_EVENT_CLEAR (0x1C001000+0x814) */ 1301 #define REG_WAKEUP_EVENT_CLR_LSB BIT(0) /* 32b */ 1302 /* SPM_SRC_REQ (0x1C001000+0x818) */ 1303 #define REG_SPM_ADSP_MAILBOX_REQ_LSB BIT(0) /* 1b */ 1304 #define REG_SPM_APSRC_REQ_LSB BIT(1) /* 1b */ 1305 #define REG_SPM_DDREN_REQ_LSB BIT(2) /* 1b */ 1306 #define REG_SPM_DVFS_REQ_LSB BIT(3) /* 1b */ 1307 #define REG_SPM_EMI_REQ_LSB BIT(4) /* 1b */ 1308 #define REG_SPM_F26M_REQ_LSB BIT(5) /* 1b */ 1309 #define REG_SPM_INFRA_REQ_LSB BIT(6) /* 1b */ 1310 #define REG_SPM_PMIC_REQ_LSB BIT(7) /* 1b */ 1311 #define REG_SPM_SCP_MAILBOX_REQ_LSB BIT(8) /* 1b */ 1312 #define REG_SPM_SSPM_MAILBOX_REQ_LSB BIT(9) /* 1b */ 1313 #define REG_SPM_SW_MAILBOX_REQ_LSB BIT(10) /* 1b */ 1314 #define REG_SPM_VCORE_REQ_LSB BIT(11) /* 1b */ 1315 #define REG_SPM_VRF18_REQ_LSB BIT(12) /* 1b */ 1316 #define ADSP_MAILBOX_STATE_LSB BIT(16) /* 1b */ 1317 #define APSRC_STATE_LSB BIT(17) /* 1b */ 1318 #define DDREN_STATE_LSB BIT(18) /* 1b */ 1319 #define DVFS_STATE_LSB BIT(19) /* 1b */ 1320 #define EMI_STATE_LSB BIT(20) /* 1b */ 1321 #define F26M_STATE_LSB BIT(21) /* 1b */ 1322 #define INFRA_STATE_LSB BIT(22) /* 1b */ 1323 #define PMIC_STATE_LSB BIT(23) /* 1b */ 1324 #define SCP_MAILBOX_STATE_LSB BIT(24) /* 1b */ 1325 #define SSPM_MAILBOX_STATE_LSB BIT(25) /* 1b */ 1326 #define SW_MAILBOX_STATE_LSB BIT(26) /* 1b */ 1327 #define VCORE_STATE_LSB BIT(27) /* 1b */ 1328 #define VRF18_STATE_LSB BIT(28) /* 1b */ 1329 /* SPM_SRC_MASK_0 (0x1C001000+0x81C) */ 1330 #define REG_APU_APSRC_REQ_MASK_B_LSB BIT(0) /* 1b */ 1331 #define REG_APU_DDREN_REQ_MASK_B_LSB BIT(1) /* 1b */ 1332 #define REG_APU_EMI_REQ_MASK_B_LSB BIT(2) /* 1b */ 1333 #define REG_APU_INFRA_REQ_MASK_B_LSB BIT(3) /* 1b */ 1334 #define REG_APU_PMIC_REQ_MASK_B_LSB BIT(4) /* 1b */ 1335 #define REG_APU_SRCCLKENA_MASK_B_LSB BIT(5) /* 1b */ 1336 #define REG_APU_VRF18_REQ_MASK_B_LSB BIT(6) /* 1b */ 1337 #define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB BIT(7) /* 1b */ 1338 #define REG_AUDIO_DSP_DDREN_REQ_MASK_B_LSB BIT(8) /* 1b */ 1339 #define REG_AUDIO_DSP_EMI_REQ_MASK_B_LSB BIT(9) /* 1b */ 1340 #define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB BIT(10) /* 1b */ 1341 #define REG_AUDIO_DSP_PMIC_REQ_MASK_B_LSB BIT(11) /* 1b */ 1342 #define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB BIT(12) /* 1b */ 1343 #define REG_AUDIO_DSP_VCORE_REQ_MASK_B_LSB BIT(13) /* 1b */ 1344 #define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB BIT(14) /* 1b */ 1345 #define REG_CAM_APSRC_REQ_MASK_B_LSB BIT(15) /* 1b */ 1346 #define REG_CAM_DDREN_REQ_MASK_B_LSB BIT(16) /* 1b */ 1347 #define REG_CAM_EMI_REQ_MASK_B_LSB BIT(17) /* 1b */ 1348 #define REG_CAM_INFRA_REQ_MASK_B_LSB BIT(18) /* 1b */ 1349 #define REG_CAM_PMIC_REQ_MASK_B_LSB BIT(19) /* 1b */ 1350 #define REG_CAM_SRCCLKENA_MASK_B_LSB BIT(20) /* 1b */ 1351 #define REG_CAM_VRF18_REQ_MASK_B_LSB BIT(21) /* 1b */ 1352 /* SPM_SRC_MASK_1 (0x1C001000+0x820) */ 1353 #define REG_CCIF_APSRC_REQ_MASK_B_LSB BIT(0) /* 12b */ 1354 #define REG_CCIF_EMI_REQ_MASK_B_LSB BIT(12) /* 12b */ 1355 /* SPM_SRC_MASK_2 (0x1C001000+0x824) */ 1356 #define REG_CCIF_INFRA_REQ_MASK_B_LSB BIT(0) /* 12b */ 1357 #define REG_CCIF_PMIC_REQ_MASK_B_LSB BIT(12) /* 12b */ 1358 /* SPM_SRC_MASK_3 (0x1C001000+0x828) */ 1359 #define REG_CCIF_SRCCLKENA_MASK_B_LSB BIT(0) /* 12b */ 1360 #define REG_CCIF_VRF18_REQ_MASK_B_LSB BIT(12) /* 12b */ 1361 #define REG_CCU_APSRC_REQ_MASK_B_LSB BIT(24) /* 1b */ 1362 #define REG_CCU_DDREN_REQ_MASK_B_LSB BIT(25) /* 1b */ 1363 #define REG_CCU_EMI_REQ_MASK_B_LSB BIT(26) /* 1b */ 1364 #define REG_CCU_INFRA_REQ_MASK_B_LSB BIT(27) /* 1b */ 1365 #define REG_CCU_PMIC_REQ_MASK_B_LSB BIT(28) /* 1b */ 1366 #define REG_CCU_SRCCLKENA_MASK_B_LSB BIT(29) /* 1b */ 1367 #define REG_CCU_VRF18_REQ_MASK_B_LSB BIT(30) /* 1b */ 1368 #define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB BIT(31) /* 1b */ 1369 /* SPM_SRC_MASK_4 (0x1C001000+0x82C) */ 1370 #define REG_CG_CHECK_DDREN_REQ_MASK_B_LSB BIT(0) /* 1b */ 1371 #define REG_CG_CHECK_EMI_REQ_MASK_B_LSB BIT(1) /* 1b */ 1372 #define REG_CG_CHECK_INFRA_REQ_MASK_B_LSB BIT(2) /* 1b */ 1373 #define REG_CG_CHECK_PMIC_REQ_MASK_B_LSB BIT(3) /* 1b */ 1374 #define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB BIT(4) /* 1b */ 1375 #define REG_CG_CHECK_VCORE_REQ_MASK_B_LSB BIT(5) /* 1b */ 1376 #define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB BIT(6) /* 1b */ 1377 #define REG_CONN_APSRC_REQ_MASK_B_LSB BIT(7) /* 1b */ 1378 #define REG_CONN_DDREN_REQ_MASK_B_LSB BIT(8) /* 1b */ 1379 #define REG_CONN_EMI_REQ_MASK_B_LSB BIT(9) /* 1b */ 1380 #define REG_CONN_INFRA_REQ_MASK_B_LSB BIT(10) /* 1b */ 1381 #define REG_CONN_PMIC_REQ_MASK_B_LSB BIT(11) /* 1b */ 1382 #define REG_CONN_SRCCLKENA_MASK_B_LSB BIT(12) /* 1b */ 1383 #define REG_CONN_SRCCLKENB_MASK_B_LSB BIT(13) /* 1b */ 1384 #define REG_CONN_VCORE_REQ_MASK_B_LSB BIT(14) /* 1b */ 1385 #define REG_CONN_VRF18_REQ_MASK_B_LSB BIT(15) /* 1b */ 1386 #define REG_CPUEB_APSRC_REQ_MASK_B_LSB BIT(16) /* 1b */ 1387 #define REG_CPUEB_DDREN_REQ_MASK_B_LSB BIT(17) /* 1b */ 1388 #define REG_CPUEB_EMI_REQ_MASK_B_LSB BIT(18) /* 1b */ 1389 #define REG_CPUEB_INFRA_REQ_MASK_B_LSB BIT(19) /* 1b */ 1390 #define REG_CPUEB_PMIC_REQ_MASK_B_LSB BIT(20) /* 1b */ 1391 #define REG_CPUEB_SRCCLKENA_MASK_B_LSB BIT(21) /* 1b */ 1392 #define REG_CPUEB_VRF18_REQ_MASK_B_LSB BIT(22) /* 1b */ 1393 #define REG_DISP0_APSRC_REQ_MASK_B_LSB BIT(23) /* 1b */ 1394 #define REG_DISP0_DDREN_REQ_MASK_B_LSB BIT(24) /* 1b */ 1395 #define REG_DISP0_EMI_REQ_MASK_B_LSB BIT(25) /* 1b */ 1396 #define REG_DISP0_INFRA_REQ_MASK_B_LSB BIT(26) /* 1b */ 1397 #define REG_DISP0_PMIC_REQ_MASK_B_LSB BIT(27) /* 1b */ 1398 #define REG_DISP0_SRCCLKENA_MASK_B_LSB BIT(28) /* 1b */ 1399 #define REG_DISP0_VRF18_REQ_MASK_B_LSB BIT(29) /* 1b */ 1400 #define REG_DISP1_APSRC_REQ_MASK_B_LSB BIT(30) /* 1b */ 1401 #define REG_DISP1_DDREN_REQ_MASK_B_LSB BIT(31) /* 1b */ 1402 /* SPM_SRC_MASK_5 (0x1C001000+0x830) */ 1403 #define REG_DISP1_EMI_REQ_MASK_B_LSB BIT(0) /* 1b */ 1404 #define REG_DISP1_INFRA_REQ_MASK_B_LSB BIT(1) /* 1b */ 1405 #define REG_DISP1_PMIC_REQ_MASK_B_LSB BIT(2) /* 1b */ 1406 #define REG_DISP1_SRCCLKENA_MASK_B_LSB BIT(3) /* 1b */ 1407 #define REG_DISP1_VRF18_REQ_MASK_B_LSB BIT(4) /* 1b */ 1408 #define REG_DPM_APSRC_REQ_MASK_B_LSB BIT(5) /* 4b */ 1409 #define REG_DPM_DDREN_REQ_MASK_B_LSB BIT(9) /* 4b */ 1410 #define REG_DPM_EMI_REQ_MASK_B_LSB BIT(13) /* 4b */ 1411 #define REG_DPM_INFRA_REQ_MASK_B_LSB BIT(17) /* 4b */ 1412 #define REG_DPM_PMIC_REQ_MASK_B_LSB BIT(21) /* 4b */ 1413 #define REG_DPM_SRCCLKENA_MASK_B_LSB BIT(25) /* 4b */ 1414 /* SPM_SRC_MASK_6 (0x1C001000+0x834) */ 1415 #define REG_DPM_VCORE_REQ_MASK_B_LSB BIT(0) /* 4b */ 1416 #define REG_DPM_VRF18_REQ_MASK_B_LSB BIT(4) /* 4b */ 1417 #define REG_DPMAIF_APSRC_REQ_MASK_B_LSB BIT(8) /* 1b */ 1418 #define REG_DPMAIF_DDREN_REQ_MASK_B_LSB BIT(9) /* 1b */ 1419 #define REG_DPMAIF_EMI_REQ_MASK_B_LSB BIT(10) /* 1b */ 1420 #define REG_DPMAIF_INFRA_REQ_MASK_B_LSB BIT(11) /* 1b */ 1421 #define REG_DPMAIF_PMIC_REQ_MASK_B_LSB BIT(12) /* 1b */ 1422 #define REG_DPMAIF_SRCCLKENA_MASK_B_LSB BIT(13) /* 1b */ 1423 #define REG_DPMAIF_VRF18_REQ_MASK_B_LSB BIT(14) /* 1b */ 1424 #define REG_DVFSRC_LEVEL_REQ_MASK_B_LSB BIT(15) /* 1b */ 1425 #define REG_EMISYS_APSRC_REQ_MASK_B_LSB BIT(16) /* 1b */ 1426 #define REG_EMISYS_DDREN_REQ_MASK_B_LSB BIT(17) /* 1b */ 1427 #define REG_EMISYS_EMI_REQ_MASK_B_LSB BIT(18) /* 1b */ 1428 #define REG_GCE_D_APSRC_REQ_MASK_B_LSB BIT(19) /* 1b */ 1429 #define REG_GCE_D_DDREN_REQ_MASK_B_LSB BIT(20) /* 1b */ 1430 #define REG_GCE_D_EMI_REQ_MASK_B_LSB BIT(21) /* 1b */ 1431 #define REG_GCE_D_INFRA_REQ_MASK_B_LSB BIT(22) /* 1b */ 1432 #define REG_GCE_D_PMIC_REQ_MASK_B_LSB BIT(23) /* 1b */ 1433 #define REG_GCE_D_SRCCLKENA_MASK_B_LSB BIT(24) /* 1b */ 1434 #define REG_GCE_D_VRF18_REQ_MASK_B_LSB BIT(25) /* 1b */ 1435 #define REG_GCE_M_APSRC_REQ_MASK_B_LSB BIT(26) /* 1b */ 1436 #define REG_GCE_M_DDREN_REQ_MASK_B_LSB BIT(27) /* 1b */ 1437 #define REG_GCE_M_EMI_REQ_MASK_B_LSB BIT(28) /* 1b */ 1438 #define REG_GCE_M_INFRA_REQ_MASK_B_LSB BIT(29) /* 1b */ 1439 #define REG_GCE_M_PMIC_REQ_MASK_B_LSB BIT(30) /* 1b */ 1440 #define REG_GCE_M_SRCCLKENA_MASK_B_LSB BIT(31) /* 1b */ 1441 /* SPM_SRC_MASK_7 (0x1C001000+0x838) */ 1442 #define REG_GCE_M_VRF18_REQ_MASK_B_LSB BIT(0) /* 1b */ 1443 #define REG_GPUEB_APSRC_REQ_MASK_B_LSB BIT(1) /* 1b */ 1444 #define REG_GPUEB_DDREN_REQ_MASK_B_LSB BIT(2) /* 1b */ 1445 #define REG_GPUEB_EMI_REQ_MASK_B_LSB BIT(3) /* 1b */ 1446 #define REG_GPUEB_INFRA_REQ_MASK_B_LSB BIT(4) /* 1b */ 1447 #define REG_GPUEB_PMIC_REQ_MASK_B_LSB BIT(5) /* 1b */ 1448 #define REG_GPUEB_SRCCLKENA_MASK_B_LSB BIT(6) /* 1b */ 1449 #define REG_GPUEB_VRF18_REQ_MASK_B_LSB BIT(7) /* 1b */ 1450 #define REG_HWCCF_APSRC_REQ_MASK_B_LSB BIT(8) /* 1b */ 1451 #define REG_HWCCF_DDREN_REQ_MASK_B_LSB BIT(9) /* 1b */ 1452 #define REG_HWCCF_EMI_REQ_MASK_B_LSB BIT(10) /* 1b */ 1453 #define REG_HWCCF_INFRA_REQ_MASK_B_LSB BIT(11) /* 1b */ 1454 #define REG_HWCCF_PMIC_REQ_MASK_B_LSB BIT(12) /* 1b */ 1455 #define REG_HWCCF_SRCCLKENA_MASK_B_LSB BIT(13) /* 1b */ 1456 #define REG_HWCCF_VCORE_REQ_MASK_B_LSB BIT(14) /* 1b */ 1457 #define REG_HWCCF_VRF18_REQ_MASK_B_LSB BIT(15) /* 1b */ 1458 #define REG_IMG_APSRC_REQ_MASK_B_LSB BIT(16) /* 1b */ 1459 #define REG_IMG_DDREN_REQ_MASK_B_LSB BIT(17) /* 1b */ 1460 #define REG_IMG_EMI_REQ_MASK_B_LSB BIT(18) /* 1b */ 1461 #define REG_IMG_INFRA_REQ_MASK_B_LSB BIT(19) /* 1b */ 1462 #define REG_IMG_PMIC_REQ_MASK_B_LSB BIT(20) /* 1b */ 1463 #define REG_IMG_SRCCLKENA_MASK_B_LSB BIT(21) /* 1b */ 1464 #define REG_IMG_VRF18_REQ_MASK_B_LSB BIT(22) /* 1b */ 1465 #define REG_INFRASYS_APSRC_REQ_MASK_B_LSB BIT(23) /* 1b */ 1466 #define REG_INFRASYS_DDREN_REQ_MASK_B_LSB BIT(24) /* 1b */ 1467 #define REG_INFRASYS_EMI_REQ_MASK_B_LSB BIT(25) /* 1b */ 1468 #define REG_IPIC_INFRA_REQ_MASK_B_LSB BIT(26) /* 1b */ 1469 #define REG_IPIC_VRF18_REQ_MASK_B_LSB BIT(27) /* 1b */ 1470 #define REG_MCU_APSRC_REQ_MASK_B_LSB BIT(28) /* 1b */ 1471 #define REG_MCU_DDREN_REQ_MASK_B_LSB BIT(29) /* 1b */ 1472 #define REG_MCU_EMI_REQ_MASK_B_LSB BIT(30) /* 1b */ 1473 /* SPM_SRC_MASK_8 (0x1C001000+0x83C) */ 1474 #define REG_MCUSYS_APSRC_REQ_MASK_B_LSB BIT(0) /* 8b */ 1475 #define REG_MCUSYS_DDREN_REQ_MASK_B_LSB BIT(8) /* 8b */ 1476 #define REG_MCUSYS_EMI_REQ_MASK_B_LSB BIT(16) /* 8b */ 1477 #define REG_MCUSYS_INFRA_REQ_MASK_B_LSB BIT(24) /* 8b */ 1478 /* SPM_SRC_MASK_9 (0x1C001000+0x840) */ 1479 #define REG_MCUSYS_PMIC_REQ_MASK_B_LSB BIT(0) /* 8b */ 1480 #define REG_MCUSYS_SRCCLKENA_MASK_B_LSB BIT(8) /* 8b */ 1481 #define REG_MCUSYS_VRF18_REQ_MASK_B_LSB BIT(16) /* 8b */ 1482 #define REG_MD_APSRC_REQ_MASK_B_LSB BIT(24) /* 1b */ 1483 #define REG_MD_DDREN_REQ_MASK_B_LSB BIT(25) /* 1b */ 1484 #define REG_MD_EMI_REQ_MASK_B_LSB BIT(26) /* 1b */ 1485 #define REG_MD_INFRA_REQ_MASK_B_LSB BIT(27) /* 1b */ 1486 #define REG_MD_PMIC_REQ_MASK_B_LSB BIT(28) /* 1b */ 1487 #define REG_MD_SRCCLKENA_MASK_B_LSB BIT(29) /* 1b */ 1488 #define REG_MD_SRCCLKENA1_MASK_B_LSB BIT(30) /* 1b */ 1489 #define REG_MD_VCORE_REQ_MASK_B_LSB BIT(31) /* 1b */ 1490 /* SPM_SRC_MASK_10 (0x1C001000+0x844) */ 1491 #define REG_MD_VRF18_REQ_MASK_B_LSB BIT(0) /* 1b */ 1492 #define REG_MDP_APSRC_REQ_MASK_B_LSB BIT(1) /* 1b */ 1493 #define REG_MDP_DDREN_REQ_MASK_B_LSB BIT(2) /* 1b */ 1494 #define REG_MM_PROC_APSRC_REQ_MASK_B_LSB BIT(3) /* 1b */ 1495 #define REG_MM_PROC_DDREN_REQ_MASK_B_LSB BIT(4) /* 1b */ 1496 #define REG_MM_PROC_EMI_REQ_MASK_B_LSB BIT(5) /* 1b */ 1497 #define REG_MM_PROC_INFRA_REQ_MASK_B_LSB BIT(6) /* 1b */ 1498 #define REG_MM_PROC_PMIC_REQ_MASK_B_LSB BIT(7) /* 1b */ 1499 #define REG_MM_PROC_SRCCLKENA_MASK_B_LSB BIT(8) /* 1b */ 1500 #define REG_MM_PROC_VRF18_REQ_MASK_B_LSB BIT(9) /* 1b */ 1501 #define REG_MMSYS_APSRC_REQ_MASK_B_LSB BIT(10) /* 1b */ 1502 #define REG_MMSYS_DDREN_REQ_MASK_B_LSB BIT(11) /* 1b */ 1503 #define REG_MMSYS_VRF18_REQ_MASK_B_LSB BIT(12) /* 1b */ 1504 #define REG_PCIE0_APSRC_REQ_MASK_B_LSB BIT(13) /* 1b */ 1505 #define REG_PCIE0_DDREN_REQ_MASK_B_LSB BIT(14) /* 1b */ 1506 #define REG_PCIE0_INFRA_REQ_MASK_B_LSB BIT(15) /* 1b */ 1507 #define REG_PCIE0_SRCCLKENA_MASK_B_LSB BIT(16) /* 1b */ 1508 #define REG_PCIE0_VRF18_REQ_MASK_B_LSB BIT(17) /* 1b */ 1509 #define REG_PCIE1_APSRC_REQ_MASK_B_LSB BIT(18) /* 1b */ 1510 #define REG_PCIE1_DDREN_REQ_MASK_B_LSB BIT(19) /* 1b */ 1511 #define REG_PCIE1_INFRA_REQ_MASK_B_LSB BIT(20) /* 1b */ 1512 #define REG_PCIE1_SRCCLKENA_MASK_B_LSB BIT(21) /* 1b */ 1513 #define REG_PCIE1_VRF18_REQ_MASK_B_LSB BIT(22) /* 1b */ 1514 #define REG_PERISYS_APSRC_REQ_MASK_B_LSB BIT(23) /* 1b */ 1515 #define REG_PERISYS_DDREN_REQ_MASK_B_LSB BIT(24) /* 1b */ 1516 #define REG_PERISYS_EMI_REQ_MASK_B_LSB BIT(25) /* 1b */ 1517 #define REG_PERISYS_INFRA_REQ_MASK_B_LSB BIT(26) /* 1b */ 1518 #define REG_PERISYS_PMIC_REQ_MASK_B_LSB BIT(27) /* 1b */ 1519 #define REG_PERISYS_SRCCLKENA_MASK_B_LSB BIT(28) /* 1b */ 1520 #define REG_PERISYS_VCORE_REQ_MASK_B_LSB BIT(29) /* 1b */ 1521 #define REG_PERISYS_VRF18_REQ_MASK_B_LSB BIT(30) /* 1b */ 1522 #define REG_SCP_APSRC_REQ_MASK_B_LSB BIT(31) /* 1b */ 1523 /* SPM_SRC_MASK_11 (0x1C001000+0x848) */ 1524 #define REG_SCP_DDREN_REQ_MASK_B_LSB BIT(0) /* 1b */ 1525 #define REG_SCP_EMI_REQ_MASK_B_LSB BIT(1) /* 1b */ 1526 #define REG_SCP_INFRA_REQ_MASK_B_LSB BIT(2) /* 1b */ 1527 #define REG_SCP_PMIC_REQ_MASK_B_LSB BIT(3) /* 1b */ 1528 #define REG_SCP_SRCCLKENA_MASK_B_LSB BIT(4) /* 1b */ 1529 #define REG_SCP_VCORE_REQ_MASK_B_LSB BIT(5) /* 1b */ 1530 #define REG_SCP_VRF18_REQ_MASK_B_LSB BIT(6) /* 1b */ 1531 #define REG_SRCCLKENI_INFRA_REQ_MASK_B_LSB BIT(7) /* 2b */ 1532 #define REG_SRCCLKENI_PMIC_REQ_MASK_B_LSB BIT(9) /* 2b */ 1533 #define REG_SRCCLKENI_SRCCLKENA_MASK_B_LSB BIT(11) /* 2b */ 1534 #define REG_SSPM_APSRC_REQ_MASK_B_LSB BIT(13) /* 1b */ 1535 #define REG_SSPM_DDREN_REQ_MASK_B_LSB BIT(14) /* 1b */ 1536 #define REG_SSPM_EMI_REQ_MASK_B_LSB BIT(15) /* 1b */ 1537 #define REG_SSPM_INFRA_REQ_MASK_B_LSB BIT(16) /* 1b */ 1538 #define REG_SSPM_PMIC_REQ_MASK_B_LSB BIT(17) /* 1b */ 1539 #define REG_SSPM_SRCCLKENA_MASK_B_LSB BIT(18) /* 1b */ 1540 #define REG_SSPM_VRF18_REQ_MASK_B_LSB BIT(19) /* 1b */ 1541 #define REG_SSR_APSRC_REQ_MASK_B_LSB BIT(20) /* 1b */ 1542 #define REG_SSR_DDREN_REQ_MASK_B_LSB BIT(21) /* 1b */ 1543 #define REG_SSR_EMI_REQ_MASK_B_LSB BIT(22) /* 1b */ 1544 #define REG_SSR_INFRA_REQ_MASK_B_LSB BIT(23) /* 1b */ 1545 #define REG_SSR_PMIC_REQ_MASK_B_LSB BIT(24) /* 1b */ 1546 #define REG_SSR_SRCCLKENA_MASK_B_LSB BIT(25) /* 1b */ 1547 #define REG_SSR_VRF18_REQ_MASK_B_LSB BIT(26) /* 1b */ 1548 #define REG_UFS_APSRC_REQ_MASK_B_LSB BIT(27) /* 1b */ 1549 #define REG_UFS_DDREN_REQ_MASK_B_LSB BIT(28) /* 1b */ 1550 #define REG_UFS_EMI_REQ_MASK_B_LSB BIT(29) /* 1b */ 1551 #define REG_UFS_INFRA_REQ_MASK_B_LSB BIT(30) /* 1b */ 1552 #define REG_UFS_PMIC_REQ_MASK_B_LSB BIT(31) /* 1b */ 1553 /* SPM_SRC_MASK_12 (0x1C001000+0x84C) */ 1554 #define REG_UFS_SRCCLKENA_MASK_B_LSB BIT(0) /* 1b */ 1555 #define REG_UFS_VRF18_REQ_MASK_B_LSB BIT(1) /* 1b */ 1556 #define REG_VDEC_APSRC_REQ_MASK_B_LSB BIT(2) /* 1b */ 1557 #define REG_VDEC_DDREN_REQ_MASK_B_LSB BIT(3) /* 1b */ 1558 #define REG_VDEC_EMI_REQ_MASK_B_LSB BIT(4) /* 1b */ 1559 #define REG_VDEC_INFRA_REQ_MASK_B_LSB BIT(5) /* 1b */ 1560 #define REG_VDEC_PMIC_REQ_MASK_B_LSB BIT(6) /* 1b */ 1561 #define REG_VDEC_SRCCLKENA_MASK_B_LSB BIT(7) /* 1b */ 1562 #define REG_VDEC_VRF18_REQ_MASK_B_LSB BIT(8) /* 1b */ 1563 #define REG_VENC_APSRC_REQ_MASK_B_LSB BIT(9) /* 1b */ 1564 #define REG_VENC_DDREN_REQ_MASK_B_LSB BIT(10) /* 1b */ 1565 #define REG_VENC_EMI_REQ_MASK_B_LSB BIT(11) /* 1b */ 1566 #define REG_VENC_INFRA_REQ_MASK_B_LSB BIT(12) /* 1b */ 1567 #define REG_VENC_PMIC_REQ_MASK_B_LSB BIT(13) /* 1b */ 1568 #define REG_VENC_SRCCLKENA_MASK_B_LSB BIT(14) /* 1b */ 1569 #define REG_VENC_VRF18_REQ_MASK_B_LSB BIT(15) /* 1b */ 1570 /* SPM_REQ_STA_0 (0x1C001000+0x850) */ 1571 #define APU_APSRC_REQ_LSB BIT(0) /* 1b */ 1572 #define APU_DDREN_REQ_LSB BIT(1) /* 1b */ 1573 #define APU_EMI_REQ_LSB BIT(2) /* 1b */ 1574 #define APU_INFRA_REQ_LSB BIT(3) /* 1b */ 1575 #define APU_PMIC_REQ_LSB BIT(4) /* 1b */ 1576 #define APU_SRCCLKENA_LSB BIT(5) /* 1b */ 1577 #define APU_VRF18_REQ_LSB BIT(6) /* 1b */ 1578 #define AUDIO_DSP_APSRC_REQ_LSB BIT(7) /* 1b */ 1579 #define AUDIO_DSP_DDREN_REQ_LSB BIT(8) /* 1b */ 1580 #define AUDIO_DSP_EMI_REQ_LSB BIT(9) /* 1b */ 1581 #define AUDIO_DSP_INFRA_REQ_LSB BIT(10) /* 1b */ 1582 #define AUDIO_DSP_PMIC_REQ_LSB BIT(11) /* 1b */ 1583 #define AUDIO_DSP_SRCCLKENA_LSB BIT(12) /* 1b */ 1584 #define AUDIO_DSP_VCORE_REQ_LSB BIT(13) /* 1b */ 1585 #define AUDIO_DSP_VRF18_REQ_LSB BIT(14) /* 1b */ 1586 #define CAM_APSRC_REQ_LSB BIT(15) /* 1b */ 1587 #define CAM_DDREN_REQ_LSB BIT(16) /* 1b */ 1588 #define CAM_EMI_REQ_LSB BIT(17) /* 1b */ 1589 #define CAM_INFRA_REQ_LSB BIT(18) /* 1b */ 1590 #define CAM_PMIC_REQ_LSB BIT(19) /* 1b */ 1591 #define CAM_SRCCLKENA_LSB BIT(20) /* 1b */ 1592 #define CAM_VRF18_REQ_LSB BIT(21) /* 1b */ 1593 /* SPM_REQ_STA_1 (0x1C001000+0x854) */ 1594 #define CCIF_APSRC_REQ_LSB BIT(0) /* 12b */ 1595 #define CCIF_EMI_REQ_LSB BIT(12) /* 12b */ 1596 /* SPM_REQ_STA_2 (0x1C001000+0x858) */ 1597 #define CCIF_INFRA_REQ_LSB BIT(0) /* 12b */ 1598 #define CCIF_PMIC_REQ_LSB BIT(12) /* 12b */ 1599 /* SPM_REQ_STA_3 (0x1C001000+0x85C) */ 1600 #define CCIF_SRCCLKENA_LSB BIT(0) /* 12b */ 1601 #define CCIF_VRF18_REQ_LSB BIT(12) /* 12b */ 1602 #define CCU_APSRC_REQ_LSB BIT(24) /* 1b */ 1603 #define CCU_DDREN_REQ_LSB BIT(25) /* 1b */ 1604 #define CCU_EMI_REQ_LSB BIT(26) /* 1b */ 1605 #define CCU_INFRA_REQ_LSB BIT(27) /* 1b */ 1606 #define CCU_PMIC_REQ_LSB BIT(28) /* 1b */ 1607 #define CCU_SRCCLKENA_LSB BIT(29) /* 1b */ 1608 #define CCU_VRF18_REQ_LSB BIT(30) /* 1b */ 1609 #define CG_CHECK_APSRC_REQ_LSB BIT(31) /* 1b */ 1610 /* SPM_REQ_STA_4 (0x1C001000+0x860) */ 1611 #define CG_CHECK_DDREN_REQ_LSB BIT(0) /* 1b */ 1612 #define CG_CHECK_EMI_REQ_LSB BIT(1) /* 1b */ 1613 #define CG_CHECK_INFRA_REQ_LSB BIT(2) /* 1b */ 1614 #define CG_CHECK_PMIC_REQ_LSB BIT(3) /* 1b */ 1615 #define CG_CHECK_SRCCLKENA_LSB BIT(4) /* 1b */ 1616 #define CG_CHECK_VCORE_REQ_LSB BIT(5) /* 1b */ 1617 #define CG_CHECK_VRF18_REQ_LSB BIT(6) /* 1b */ 1618 #define CONN_APSRC_REQ_LSB BIT(7) /* 1b */ 1619 #define CONN_DDREN_REQ_LSB BIT(8) /* 1b */ 1620 #define CONN_EMI_REQ_LSB BIT(9) /* 1b */ 1621 #define CONN_INFRA_REQ_LSB BIT(10) /* 1b */ 1622 #define CONN_PMIC_REQ_LSB BIT(11) /* 1b */ 1623 #define CONN_SRCCLKENA_LSB BIT(12) /* 1b */ 1624 #define CONN_SRCCLKENB_LSB BIT(13) /* 1b */ 1625 #define CONN_VCORE_REQ_LSB BIT(14) /* 1b */ 1626 #define CONN_VRF18_REQ_LSB BIT(15) /* 1b */ 1627 #define CPUEB_APSRC_REQ_LSB BIT(16) /* 1b */ 1628 #define CPUEB_DDREN_REQ_LSB BIT(17) /* 1b */ 1629 #define CPUEB_EMI_REQ_LSB BIT(18) /* 1b */ 1630 #define CPUEB_INFRA_REQ_LSB BIT(19) /* 1b */ 1631 #define CPUEB_PMIC_REQ_LSB BIT(20) /* 1b */ 1632 #define CPUEB_SRCCLKENA_LSB BIT(21) /* 1b */ 1633 #define CPUEB_VRF18_REQ_LSB BIT(22) /* 1b */ 1634 #define DISP0_APSRC_REQ_LSB BIT(23) /* 1b */ 1635 #define DISP0_DDREN_REQ_LSB BIT(24) /* 1b */ 1636 #define DISP0_EMI_REQ_LSB BIT(25) /* 1b */ 1637 #define DISP0_INFRA_REQ_LSB BIT(26) /* 1b */ 1638 #define DISP0_PMIC_REQ_LSB BIT(27) /* 1b */ 1639 #define DISP0_SRCCLKENA_LSB BIT(28) /* 1b */ 1640 #define DISP0_VRF18_REQ_LSB BIT(29) /* 1b */ 1641 #define DISP1_APSRC_REQ_LSB BIT(30) /* 1b */ 1642 #define DISP1_DDREN_REQ_LSB BIT(31) /* 1b */ 1643 /* SPM_REQ_STA_5 (0x1C001000+0x864) */ 1644 #define DISP1_EMI_REQ_LSB BIT(0) /* 1b */ 1645 #define DISP1_INFRA_REQ_LSB BIT(1) /* 1b */ 1646 #define DISP1_PMIC_REQ_LSB BIT(2) /* 1b */ 1647 #define DISP1_SRCCLKENA_LSB BIT(3) /* 1b */ 1648 #define DISP1_VRF18_REQ_LSB BIT(4) /* 1b */ 1649 #define DPM_APSRC_REQ_LSB BIT(5) /* 4b */ 1650 #define DPM_DDREN_REQ_LSB BIT(9) /* 4b */ 1651 #define DPM_EMI_REQ_LSB BIT(13) /* 4b */ 1652 #define DPM_INFRA_REQ_LSB BIT(17) /* 4b */ 1653 #define DPM_PMIC_REQ_LSB BIT(21) /* 4b */ 1654 #define DPM_SRCCLKENA_LSB BIT(25) /* 4b */ 1655 /* SPM_REQ_STA_6 (0x1C001000+0x868) */ 1656 #define DPM_VCORE_REQ_LSB BIT(0) /* 4b */ 1657 #define DPM_VRF18_REQ_LSB BIT(4) /* 4b */ 1658 #define DPMAIF_APSRC_REQ_LSB BIT(8) /* 1b */ 1659 #define DPMAIF_DDREN_REQ_LSB BIT(9) /* 1b */ 1660 #define DPMAIF_EMI_REQ_LSB BIT(10) /* 1b */ 1661 #define DPMAIF_INFRA_REQ_LSB BIT(11) /* 1b */ 1662 #define DPMAIF_PMIC_REQ_LSB BIT(12) /* 1b */ 1663 #define DPMAIF_SRCCLKENA_LSB BIT(13) /* 1b */ 1664 #define DPMAIF_VRF18_REQ_LSB BIT(14) /* 1b */ 1665 #define DVFSRC_LEVEL_REQ_LSB BIT(15) /* 1b */ 1666 #define EMISYS_APSRC_REQ_LSB BIT(16) /* 1b */ 1667 #define EMISYS_DDREN_REQ_LSB BIT(17) /* 1b */ 1668 #define EMISYS_EMI_REQ_LSB BIT(18) /* 1b */ 1669 #define GCE_D_APSRC_REQ_LSB BIT(19) /* 1b */ 1670 #define GCE_D_DDREN_REQ_LSB BIT(20) /* 1b */ 1671 #define GCE_D_EMI_REQ_LSB BIT(21) /* 1b */ 1672 #define GCE_D_INFRA_REQ_LSB BIT(22) /* 1b */ 1673 #define GCE_D_PMIC_REQ_LSB BIT(23) /* 1b */ 1674 #define GCE_D_SRCCLKENA_LSB BIT(24) /* 1b */ 1675 #define GCE_D_VRF18_REQ_LSB BIT(25) /* 1b */ 1676 #define GCE_M_APSRC_REQ_LSB BIT(26) /* 1b */ 1677 #define GCE_M_DDREN_REQ_LSB BIT(27) /* 1b */ 1678 #define GCE_M_EMI_REQ_LSB BIT(28) /* 1b */ 1679 #define GCE_M_INFRA_REQ_LSB BIT(29) /* 1b */ 1680 #define GCE_M_PMIC_REQ_LSB BIT(30) /* 1b */ 1681 #define GCE_M_SRCCLKENA_LSB BIT(31) /* 1b */ 1682 /* SPM_REQ_STA_7 (0x1C001000+0x86C) */ 1683 #define GCE_M_VRF18_REQ_LSB BIT(0) /* 1b */ 1684 #define GPUEB_APSRC_REQ_LSB BIT(1) /* 1b */ 1685 #define GPUEB_DDREN_REQ_LSB BIT(2) /* 1b */ 1686 #define GPUEB_EMI_REQ_LSB BIT(3) /* 1b */ 1687 #define GPUEB_INFRA_REQ_LSB BIT(4) /* 1b */ 1688 #define GPUEB_PMIC_REQ_LSB BIT(5) /* 1b */ 1689 #define GPUEB_SRCCLKENA_LSB BIT(6) /* 1b */ 1690 #define GPUEB_VRF18_REQ_LSB BIT(7) /* 1b */ 1691 #define HWCCF_APSRC_REQ_LSB BIT(8) /* 1b */ 1692 #define HWCCF_DDREN_REQ_LSB BIT(9) /* 1b */ 1693 #define HWCCF_EMI_REQ_LSB BIT(10) /* 1b */ 1694 #define HWCCF_INFRA_REQ_LSB BIT(11) /* 1b */ 1695 #define HWCCF_PMIC_REQ_LSB BIT(12) /* 1b */ 1696 #define HWCCF_SRCCLKENA_LSB BIT(13) /* 1b */ 1697 #define HWCCF_VCORE_REQ_LSB BIT(14) /* 1b */ 1698 #define HWCCF_VRF18_REQ_LSB BIT(15) /* 1b */ 1699 #define IMG_APSRC_REQ_LSB BIT(16) /* 1b */ 1700 #define IMG_DDREN_REQ_LSB BIT(17) /* 1b */ 1701 #define IMG_EMI_REQ_LSB BIT(18) /* 1b */ 1702 #define IMG_INFRA_REQ_LSB BIT(19) /* 1b */ 1703 #define IMG_PMIC_REQ_LSB BIT(20) /* 1b */ 1704 #define IMG_SRCCLKENA_LSB BIT(21) /* 1b */ 1705 #define IMG_VRF18_REQ_LSB BIT(22) /* 1b */ 1706 #define INFRASYS_APSRC_REQ_LSB BIT(23) /* 1b */ 1707 #define INFRASYS_DDREN_REQ_LSB BIT(24) /* 1b */ 1708 #define INFRASYS_EMI_REQ_LSB BIT(25) /* 1b */ 1709 #define IPIC_INFRA_REQ_LSB BIT(26) /* 1b */ 1710 #define IPIC_VRF18_REQ_LSB BIT(27) /* 1b */ 1711 #define MCU_APSRC_REQ_LSB BIT(28) /* 1b */ 1712 #define MCU_DDREN_REQ_LSB BIT(29) /* 1b */ 1713 #define MCU_EMI_REQ_LSB BIT(30) /* 1b */ 1714 /* SPM_REQ_STA_8 (0x1C001000+0x870) */ 1715 #define MCUSYS_APSRC_REQ_LSB BIT(0) /* 8b */ 1716 #define MCUSYS_DDREN_REQ_LSB BIT(8) /* 8b */ 1717 #define MCUSYS_EMI_REQ_LSB BIT(16) /* 8b */ 1718 #define MCUSYS_INFRA_REQ_LSB BIT(24) /* 8b */ 1719 /* SPM_REQ_STA_9 (0x1C001000+0x874) */ 1720 #define MCUSYS_PMIC_REQ_LSB BIT(0) /* 8b */ 1721 #define MCUSYS_SRCCLKENA_LSB BIT(8) /* 8b */ 1722 #define MCUSYS_VRF18_REQ_LSB BIT(16) /* 8b */ 1723 #define MD_APSRC_REQ_LSB BIT(24) /* 1b */ 1724 #define MD_DDREN_REQ_LSB BIT(25) /* 1b */ 1725 #define MD_EMI_REQ_LSB BIT(26) /* 1b */ 1726 #define MD_INFRA_REQ_LSB BIT(27) /* 1b */ 1727 #define MD_PMIC_REQ_LSB BIT(28) /* 1b */ 1728 #define MD_SRCCLKENA_LSB BIT(29) /* 1b */ 1729 #define MD_SRCCLKENA1_LSB BIT(30) /* 1b */ 1730 #define MD_VCORE_REQ_LSB BIT(31) /* 1b */ 1731 /* SPM_REQ_STA_10 (0x1C001000+0x878) */ 1732 #define MD_VRF18_REQ_LSB BIT(0) /* 1b */ 1733 #define MDP_APSRC_REQ_LSB BIT(1) /* 1b */ 1734 #define MDP_DDREN_REQ_LSB BIT(2) /* 1b */ 1735 #define MM_PROC_APSRC_REQ_LSB BIT(3) /* 1b */ 1736 #define MM_PROC_DDREN_REQ_LSB BIT(4) /* 1b */ 1737 #define MM_PROC_EMI_REQ_LSB BIT(5) /* 1b */ 1738 #define MM_PROC_INFRA_REQ_LSB BIT(6) /* 1b */ 1739 #define MM_PROC_PMIC_REQ_LSB BIT(7) /* 1b */ 1740 #define MM_PROC_SRCCLKENA_LSB BIT(8) /* 1b */ 1741 #define MM_PROC_VRF18_REQ_LSB BIT(9) /* 1b */ 1742 #define MMSYS_APSRC_REQ_LSB BIT(10) /* 1b */ 1743 #define MMSYS_DDREN_REQ_LSB BIT(11) /* 1b */ 1744 #define MMSYS_VRF18_REQ_LSB BIT(12) /* 1b */ 1745 #define PCIE0_APSRC_REQ_LSB BIT(13) /* 1b */ 1746 #define PCIE0_DDREN_REQ_LSB BIT(14) /* 1b */ 1747 #define PCIE0_INFRA_REQ_LSB BIT(15) /* 1b */ 1748 #define PCIE0_SRCCLKENA_LSB BIT(16) /* 1b */ 1749 #define PCIE0_VRF18_REQ_LSB BIT(17) /* 1b */ 1750 #define PCIE1_APSRC_REQ_LSB BIT(18) /* 1b */ 1751 #define PCIE1_DDREN_REQ_LSB BIT(19) /* 1b */ 1752 #define PCIE1_INFRA_REQ_LSB BIT(20) /* 1b */ 1753 #define PCIE1_SRCCLKENA_LSB BIT(21) /* 1b */ 1754 #define PCIE1_VRF18_REQ_LSB BIT(22) /* 1b */ 1755 #define PERISYS_APSRC_REQ_LSB BIT(23) /* 1b */ 1756 #define PERISYS_DDREN_REQ_LSB BIT(24) /* 1b */ 1757 #define PERISYS_EMI_REQ_LSB BIT(25) /* 1b */ 1758 #define PERISYS_INFRA_REQ_LSB BIT(26) /* 1b */ 1759 #define PERISYS_PMIC_REQ_LSB BIT(27) /* 1b */ 1760 #define PERISYS_SRCCLKENA_LSB BIT(28) /* 1b */ 1761 #define PERISYS_VCORE_REQ_LSB BIT(29) /* 1b */ 1762 #define PERISYS_VRF18_REQ_LSB BIT(30) /* 1b */ 1763 #define SCP_APSRC_REQ_LSB BIT(31) /* 1b */ 1764 /* SPM_REQ_STA_11 (0x1C001000+0x87C) */ 1765 #define SCP_DDREN_REQ_LSB BIT(0) /* 1b */ 1766 #define SCP_EMI_REQ_LSB BIT(1) /* 1b */ 1767 #define SCP_INFRA_REQ_LSB BIT(2) /* 1b */ 1768 #define SCP_PMIC_REQ_LSB BIT(3) /* 1b */ 1769 #define SCP_SRCCLKENA_LSB BIT(4) /* 1b */ 1770 #define SCP_VCORE_REQ_LSB BIT(5) /* 1b */ 1771 #define SCP_VRF18_REQ_LSB BIT(6) /* 1b */ 1772 #define SRCCLKENI_INFRA_REQ_LSB BIT(7) /* 2b */ 1773 #define SRCCLKENI_PMIC_REQ_LSB BIT(9) /* 2b */ 1774 #define SRCCLKENI_SRCCLKENA_LSB BIT(11) /* 2b */ 1775 #define SSPM_APSRC_REQ_LSB BIT(13) /* 1b */ 1776 #define SSPM_DDREN_REQ_LSB BIT(14) /* 1b */ 1777 #define SSPM_EMI_REQ_LSB BIT(15) /* 1b */ 1778 #define SSPM_INFRA_REQ_LSB BIT(16) /* 1b */ 1779 #define SSPM_PMIC_REQ_LSB BIT(17) /* 1b */ 1780 #define SSPM_SRCCLKENA_LSB BIT(18) /* 1b */ 1781 #define SSPM_VRF18_REQ_LSB BIT(19) /* 1b */ 1782 #define SSR_APSRC_REQ_LSB BIT(20) /* 1b */ 1783 #define SSR_DDREN_REQ_LSB BIT(21) /* 1b */ 1784 #define SSR_EMI_REQ_LSB BIT(22) /* 1b */ 1785 #define SSR_INFRA_REQ_LSB BIT(23) /* 1b */ 1786 #define SSR_PMIC_REQ_LSB BIT(24) /* 1b */ 1787 #define SSR_SRCCLKENA_LSB BIT(25) /* 1b */ 1788 #define SSR_VRF18_REQ_LSB BIT(26) /* 1b */ 1789 #define UFS_APSRC_REQ_LSB BIT(27) /* 1b */ 1790 #define UFS_DDREN_REQ_LSB BIT(28) /* 1b */ 1791 #define UFS_EMI_REQ_LSB BIT(29) /* 1b */ 1792 #define UFS_INFRA_REQ_LSB BIT(30) /* 1b */ 1793 #define UFS_PMIC_REQ_LSB BIT(31) /* 1b */ 1794 /* SPM_REQ_STA_12 (0x1C001000+0x880) */ 1795 #define UFS_SRCCLKENA_LSB BIT(0) /* 1b */ 1796 #define UFS_VRF18_REQ_LSB BIT(1) /* 1b */ 1797 #define VDEC_APSRC_REQ_LSB BIT(2) /* 1b */ 1798 #define VDEC_DDREN_REQ_LSB BIT(3) /* 1b */ 1799 #define VDEC_EMI_REQ_LSB BIT(4) /* 1b */ 1800 #define VDEC_INFRA_REQ_LSB BIT(5) /* 1b */ 1801 #define VDEC_PMIC_REQ_LSB BIT(6) /* 1b */ 1802 #define VDEC_SRCCLKENA_LSB BIT(7) /* 1b */ 1803 #define VDEC_VRF18_REQ_LSB BIT(8) /* 1b */ 1804 #define VENC_APSRC_REQ_LSB BIT(9) /* 1b */ 1805 #define VENC_DDREN_REQ_LSB BIT(10) /* 1b */ 1806 #define VENC_EMI_REQ_LSB BIT(11) /* 1b */ 1807 #define VENC_INFRA_REQ_LSB BIT(12) /* 1b */ 1808 #define VENC_PMIC_REQ_LSB BIT(13) /* 1b */ 1809 #define VENC_SRCCLKENA_LSB BIT(14) /* 1b */ 1810 #define VENC_VRF18_REQ_LSB BIT(15) /* 1b */ 1811 /* SPM_IPC_WAKEUP_REQ (0x1C001000+0x884) */ 1812 #define SPM2SSPM_WAKEUP_LSB BIT(0) /* 1b */ 1813 #define SPM2SCP_WAKEUP_LSB BIT(1) /* 1b */ 1814 #define SPM2ADSP_WAKEUP_LSB BIT(2) /* 1b */ 1815 /* IPC_WAKEUP_REQ_MASK_STA (0x1C001000+0x888) */ 1816 #define REG_SW2SPM_WAKEUP_MASK_B_LSB BIT(0) /* 4b */ 1817 #define REG_SSPM2SPM_WAKEUP_MASK_B_LSB BIT(4) /* 1b */ 1818 #define REG_SCP2SPM_WAKEUP_MASK_B_LSB BIT(5) /* 1b */ 1819 #define REG_ADSP2SPM_WAKEUP_MASK_B_LSB BIT(6) /* 1b */ 1820 #define SSPM2SPM_WAKEUP_LSB BIT(20) /* 1b */ 1821 #define SCP2SPM_WAKEUP_LSB BIT(21) /* 1b */ 1822 #define ADSP2SPM_WAKEUP_LSB BIT(22) /* 1b */ 1823 /* SPM_EVENT_CON_MISC (0x1C001000+0x88C) */ 1824 #define REG_SRCCLKEN_FAST_RESP_LSB BIT(0) /* 1b */ 1825 #define REG_CSYSPWRUP_ACK_MASK_LSB BIT(1) /* 1b */ 1826 /* DDREN_DBC_CON (0x1C001000+0x890) */ 1827 #define REG_DDREN_DBC_LEN_LSB BIT(0) /* 10b */ 1828 #define REG_DDREN_DBC_EN_LSB BIT(16) /* 1b */ 1829 /* SPM_RESOURCE_ACK_CON_0 (0x1C001000+0x894) */ 1830 #define SPM_VCORE_ACK_WAIT_CYCLE_LSB BIT(0) /* 8b */ 1831 #define SPM_PMIC_ACK_WAIT_CYCLE_LSB BIT(8) /* 8b */ 1832 #define SPM_SRCCLKENA_ACK_WAIT_CYCLE_LSB BIT(16) /* 8b */ 1833 #define SPM_INFRA_ACK_WAIT_CYCLE_LSB BIT(24) /* 8b */ 1834 /* SPM_RESOURCE_ACK_CON_1 (0x1C001000+0x898) */ 1835 #define SPM_VRF18_ACK_WAIT_CYCLE_LSB BIT(0) /* 8b */ 1836 #define SPM_EMI_ACK_WAIT_CYCLE_LSB BIT(8) /* 8b */ 1837 #define SPM_APSRC_ACK_WAIT_CYCLE_LSB BIT(16) /* 8b */ 1838 #define SPM_DDREN_ACK_WAIT_CYCLE_LSB BIT(24) /* 8b */ 1839 /* SPM_RESOURCE_ACK_MASK_0 (0x1C001000+0x89C) */ 1840 #define REG_APU_APSRC_ACK_MASK_LSB BIT(0) /* 1b */ 1841 #define REG_APU_DDREN_ACK_MASK_LSB BIT(1) /* 1b */ 1842 #define REG_APU_EMI_ACK_MASK_LSB BIT(2) /* 1b */ 1843 #define REG_APU_INFRA_ACK_MASK_LSB BIT(3) /* 1b */ 1844 #define REG_APU_PMIC_ACK_MASK_LSB BIT(4) /* 1b */ 1845 #define REG_APU_SRCCLKENA_ACK_MASK_LSB BIT(5) /* 1b */ 1846 #define REG_APU_VRF18_ACK_MASK_LSB BIT(6) /* 1b */ 1847 #define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB BIT(7) /* 1b */ 1848 #define REG_AUDIO_DSP_DDREN_ACK_MASK_LSB BIT(8) /* 1b */ 1849 #define REG_AUDIO_DSP_EMI_ACK_MASK_LSB BIT(9) /* 1b */ 1850 #define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB BIT(10) /* 1b */ 1851 #define REG_AUDIO_DSP_PMIC_ACK_MASK_LSB BIT(11) /* 1b */ 1852 #define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB BIT(12) /* 1b */ 1853 #define REG_AUDIO_DSP_VCORE_ACK_MASK_LSB BIT(13) /* 1b */ 1854 #define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB BIT(14) /* 1b */ 1855 #define REG_CAM_APSRC_ACK_MASK_LSB BIT(15) /* 1b */ 1856 #define REG_CAM_DDREN_ACK_MASK_LSB BIT(16) /* 1b */ 1857 #define REG_CAM_EMI_ACK_MASK_LSB BIT(17) /* 1b */ 1858 #define REG_CAM_INFRA_ACK_MASK_LSB BIT(18) /* 1b */ 1859 #define REG_CAM_PMIC_ACK_MASK_LSB BIT(19) /* 1b */ 1860 #define REG_CAM_SRCCLKENA_ACK_MASK_LSB BIT(20) /* 1b */ 1861 #define REG_CAM_VRF18_ACK_MASK_LSB BIT(21) /* 1b */ 1862 #define REG_CCU_APSRC_ACK_MASK_LSB BIT(22) /* 1b */ 1863 #define REG_CCU_DDREN_ACK_MASK_LSB BIT(23) /* 1b */ 1864 #define REG_CCU_EMI_ACK_MASK_LSB BIT(24) /* 1b */ 1865 #define REG_CCU_INFRA_ACK_MASK_LSB BIT(25) /* 1b */ 1866 #define REG_CCU_PMIC_ACK_MASK_LSB BIT(26) /* 1b */ 1867 #define REG_CCU_SRCCLKENA_ACK_MASK_LSB BIT(27) /* 1b */ 1868 #define REG_CCU_VRF18_ACK_MASK_LSB BIT(28) /* 1b */ 1869 #define REG_CONN_APSRC_ACK_MASK_LSB BIT(29) /* 1b */ 1870 #define REG_CONN_DDREN_ACK_MASK_LSB BIT(30) /* 1b */ 1871 #define REG_CONN_EMI_ACK_MASK_LSB BIT(31) /* 1b */ 1872 /* SPM_RESOURCE_ACK_MASK_1 (0x1C001000+0x8A0) */ 1873 #define REG_CONN_INFRA_ACK_MASK_LSB BIT(0) /* 1b */ 1874 #define REG_CONN_PMIC_ACK_MASK_LSB BIT(1) /* 1b */ 1875 #define REG_CONN_SRCCLKENA_ACK_MASK_LSB BIT(2) /* 1b */ 1876 #define REG_CONN_VCORE_ACK_MASK_LSB BIT(3) /* 1b */ 1877 #define REG_CONN_VRF18_ACK_MASK_LSB BIT(4) /* 1b */ 1878 #define REG_CPUEB_APSRC_ACK_MASK_LSB BIT(5) /* 1b */ 1879 #define REG_CPUEB_DDREN_ACK_MASK_LSB BIT(6) /* 1b */ 1880 #define REG_CPUEB_EMI_ACK_MASK_LSB BIT(7) /* 1b */ 1881 #define REG_CPUEB_INFRA_ACK_MASK_LSB BIT(8) /* 1b */ 1882 #define REG_CPUEB_PMIC_ACK_MASK_LSB BIT(9) /* 1b */ 1883 #define REG_CPUEB_SRCCLKENA_ACK_MASK_LSB BIT(10) /* 1b */ 1884 #define REG_CPUEB_VRF18_ACK_MASK_LSB BIT(11) /* 1b */ 1885 #define REG_DISP0_APSRC_ACK_MASK_LSB BIT(12) /* 1b */ 1886 #define REG_DISP0_DDREN_ACK_MASK_LSB BIT(13) /* 1b */ 1887 #define REG_DISP0_EMI_ACK_MASK_LSB BIT(14) /* 1b */ 1888 #define REG_DISP0_INFRA_ACK_MASK_LSB BIT(15) /* 1b */ 1889 #define REG_DISP0_PMIC_ACK_MASK_LSB BIT(16) /* 1b */ 1890 #define REG_DISP0_SRCCLKENA_ACK_MASK_LSB BIT(17) /* 1b */ 1891 #define REG_DISP0_VRF18_ACK_MASK_LSB BIT(18) /* 1b */ 1892 #define REG_DISP1_APSRC_ACK_MASK_LSB BIT(19) /* 1b */ 1893 #define REG_DISP1_DDREN_ACK_MASK_LSB BIT(20) /* 1b */ 1894 #define REG_DISP1_EMI_ACK_MASK_LSB BIT(21) /* 1b */ 1895 #define REG_DISP1_INFRA_ACK_MASK_LSB BIT(22) /* 1b */ 1896 #define REG_DISP1_PMIC_ACK_MASK_LSB BIT(23) /* 1b */ 1897 #define REG_DISP1_SRCCLKENA_ACK_MASK_LSB BIT(24) /* 1b */ 1898 #define REG_DISP1_VRF18_ACK_MASK_LSB BIT(25) /* 1b */ 1899 #define REG_DPM_APSRC_ACK_MASK_LSB BIT(26) /* 4b */ 1900 /* SPM_RESOURCE_ACK_MASK_2 (0x1C001000+0x8A4) */ 1901 #define REG_DPM_DDREN_ACK_MASK_LSB BIT(0) /* 4b */ 1902 #define REG_DPM_EMI_ACK_MASK_LSB BIT(4) /* 4b */ 1903 #define REG_DPM_INFRA_ACK_MASK_LSB BIT(8) /* 4b */ 1904 #define REG_DPM_PMIC_ACK_MASK_LSB BIT(12) /* 4b */ 1905 #define REG_DPM_SRCCLKENA_ACK_MASK_LSB BIT(16) /* 4b */ 1906 #define REG_DPM_VCORE_ACK_MASK_LSB BIT(20) /* 4b */ 1907 #define REG_DPM_VRF18_ACK_MASK_LSB BIT(24) /* 4b */ 1908 #define REG_EMISYS_APSRC_ACK_MASK_LSB BIT(28) /* 1b */ 1909 #define REG_EMISYS_DDREN_ACK_MASK_LSB BIT(29) /* 1b */ 1910 #define REG_EMISYS_EMI_ACK_MASK_LSB BIT(30) /* 1b */ 1911 #define REG_GCE_D_APSRC_ACK_MASK_LSB BIT(31) /* 1b */ 1912 /* SPM_RESOURCE_ACK_MASK_3 (0x1C001000+0x8A8) */ 1913 #define REG_GCE_D_DDREN_ACK_MASK_LSB BIT(0) /* 1b */ 1914 #define REG_GCE_D_EMI_ACK_MASK_LSB BIT(1) /* 1b */ 1915 #define REG_GCE_D_INFRA_ACK_MASK_LSB BIT(2) /* 1b */ 1916 #define REG_GCE_D_PMIC_ACK_MASK_LSB BIT(3) /* 1b */ 1917 #define REG_GCE_D_SRCCLKENA_ACK_MASK_LSB BIT(4) /* 1b */ 1918 #define REG_GCE_D_VRF18_ACK_MASK_LSB BIT(5) /* 1b */ 1919 #define REG_GCE_M_APSRC_ACK_MASK_LSB BIT(6) /* 1b */ 1920 #define REG_GCE_M_DDREN_ACK_MASK_LSB BIT(7) /* 1b */ 1921 #define REG_GCE_M_EMI_ACK_MASK_LSB BIT(8) /* 1b */ 1922 #define REG_GCE_M_INFRA_ACK_MASK_LSB BIT(9) /* 1b */ 1923 #define REG_GCE_M_PMIC_ACK_MASK_LSB BIT(10) /* 1b */ 1924 #define REG_GCE_M_SRCCLKENA_ACK_MASK_LSB BIT(11) /* 1b */ 1925 #define REG_GCE_M_VRF18_ACK_MASK_LSB BIT(12) /* 1b */ 1926 #define REG_GPUEB_APSRC_ACK_MASK_LSB BIT(13) /* 1b */ 1927 #define REG_GPUEB_DDREN_ACK_MASK_LSB BIT(14) /* 1b */ 1928 #define REG_GPUEB_EMI_ACK_MASK_LSB BIT(15) /* 1b */ 1929 #define REG_GPUEB_INFRA_ACK_MASK_LSB BIT(16) /* 1b */ 1930 #define REG_GPUEB_PMIC_ACK_MASK_LSB BIT(17) /* 1b */ 1931 #define REG_GPUEB_SRCCLKENA_ACK_MASK_LSB BIT(18) /* 1b */ 1932 #define REG_GPUEB_VRF18_ACK_MASK_LSB BIT(19) /* 1b */ 1933 #define REG_HWCCF_APSRC_ACK_MASK_LSB BIT(20) /* 1b */ 1934 #define REG_HWCCF_DDREN_ACK_MASK_LSB BIT(21) /* 1b */ 1935 #define REG_HWCCF_EMI_ACK_MASK_LSB BIT(22) /* 1b */ 1936 #define REG_HWCCF_INFRA_ACK_MASK_LSB BIT(23) /* 1b */ 1937 #define REG_HWCCF_PMIC_ACK_MASK_LSB BIT(24) /* 1b */ 1938 #define REG_HWCCF_SRCCLKENA_ACK_MASK_LSB BIT(25) /* 1b */ 1939 #define REG_HWCCF_VCORE_ACK_MASK_LSB BIT(26) /* 1b */ 1940 #define REG_HWCCF_VRF18_ACK_MASK_LSB BIT(27) /* 1b */ 1941 #define REG_IMG_APSRC_ACK_MASK_LSB BIT(28) /* 1b */ 1942 #define REG_IMG_DDREN_ACK_MASK_LSB BIT(29) /* 1b */ 1943 #define REG_IMG_EMI_ACK_MASK_LSB BIT(30) /* 1b */ 1944 #define REG_IMG_INFRA_ACK_MASK_LSB BIT(31) /* 1b */ 1945 /* SPM_RESOURCE_ACK_MASK_4 (0x1C001000+0x8AC) */ 1946 #define REG_IMG_PMIC_ACK_MASK_LSB BIT(0) /* 1b */ 1947 #define REG_IMG_SRCCLKENA_ACK_MASK_LSB BIT(1) /* 1b */ 1948 #define REG_IMG_VRF18_ACK_MASK_LSB BIT(2) /* 1b */ 1949 #define REG_MCU_APSRC_ACK_MASK_LSB BIT(3) /* 1b */ 1950 #define REG_MCU_DDREN_ACK_MASK_LSB BIT(4) /* 1b */ 1951 #define REG_MCU_EMI_ACK_MASK_LSB BIT(5) /* 1b */ 1952 #define REG_MD_APSRC_ACK_MASK_LSB BIT(6) /* 1b */ 1953 #define REG_MD_DDREN_ACK_MASK_LSB BIT(7) /* 1b */ 1954 #define REG_MD_EMI_ACK_MASK_LSB BIT(8) /* 1b */ 1955 #define REG_MD_INFRA_ACK_MASK_LSB BIT(9) /* 1b */ 1956 #define REG_MD_PMIC_ACK_MASK_LSB BIT(10) /* 1b */ 1957 #define REG_MD_SRCCLKENA_ACK_MASK_LSB BIT(11) /* 1b */ 1958 #define REG_MD_VCORE_ACK_MASK_LSB BIT(12) /* 1b */ 1959 #define REG_MD_VRF18_ACK_MASK_LSB BIT(13) /* 1b */ 1960 #define REG_MM_PROC_APSRC_ACK_MASK_LSB BIT(14) /* 1b */ 1961 #define REG_MM_PROC_DDREN_ACK_MASK_LSB BIT(15) /* 1b */ 1962 #define REG_MM_PROC_EMI_ACK_MASK_LSB BIT(16) /* 1b */ 1963 #define REG_MM_PROC_INFRA_ACK_MASK_LSB BIT(17) /* 1b */ 1964 #define REG_MM_PROC_PMIC_ACK_MASK_LSB BIT(18) /* 1b */ 1965 #define REG_MM_PROC_SRCCLKENA_ACK_MASK_LSB BIT(19) /* 1b */ 1966 #define REG_MM_PROC_VRF18_ACK_MASK_LSB BIT(20) /* 1b */ 1967 #define REG_PCIE0_APSRC_ACK_MASK_LSB BIT(21) /* 1b */ 1968 #define REG_PCIE0_DDREN_ACK_MASK_LSB BIT(22) /* 1b */ 1969 #define REG_PCIE0_INFRA_ACK_MASK_LSB BIT(23) /* 1b */ 1970 #define REG_PCIE0_SRCCLKENA_ACK_MASK_LSB BIT(24) /* 1b */ 1971 #define REG_PCIE0_VRF18_ACK_MASK_LSB BIT(25) /* 1b */ 1972 #define REG_PCIE1_APSRC_ACK_MASK_LSB BIT(26) /* 1b */ 1973 #define REG_PCIE1_DDREN_ACK_MASK_LSB BIT(27) /* 1b */ 1974 #define REG_PCIE1_INFRA_ACK_MASK_LSB BIT(28) /* 1b */ 1975 #define REG_PCIE1_SRCCLKENA_ACK_MASK_LSB BIT(29) /* 1b */ 1976 #define REG_PCIE1_VRF18_ACK_MASK_LSB BIT(30) /* 1b */ 1977 #define REG_PERISYS_APSRC_ACK_MASK_LSB BIT(31) /* 1b */ 1978 /* SPM_RESOURCE_ACK_MASK_5 (0x1C001000+0x8B0) */ 1979 #define REG_PERISYS_DDREN_ACK_MASK_LSB BIT(0) /* 1b */ 1980 #define REG_PERISYS_EMI_ACK_MASK_LSB BIT(1) /* 1b */ 1981 #define REG_PERISYS_INFRA_ACK_MASK_LSB BIT(2) /* 1b */ 1982 #define REG_PERISYS_PMIC_ACK_MASK_LSB BIT(3) /* 1b */ 1983 #define REG_PERISYS_SRCCLKENA_ACK_MASK_LSB BIT(4) /* 1b */ 1984 #define REG_PERISYS_VCORE_ACK_MASK_LSB BIT(5) /* 1b */ 1985 #define REG_PERISYS_VRF18_ACK_MASK_LSB BIT(6) /* 1b */ 1986 #define REG_SCP_APSRC_ACK_MASK_LSB BIT(7) /* 1b */ 1987 #define REG_SCP_DDREN_ACK_MASK_LSB BIT(8) /* 1b */ 1988 #define REG_SCP_EMI_ACK_MASK_LSB BIT(9) /* 1b */ 1989 #define REG_SCP_INFRA_ACK_MASK_LSB BIT(10) /* 1b */ 1990 #define REG_SCP_PMIC_ACK_MASK_LSB BIT(11) /* 1b */ 1991 #define REG_SCP_SRCCLKENA_ACK_MASK_LSB BIT(12) /* 1b */ 1992 #define REG_SCP_VCORE_ACK_MASK_LSB BIT(13) /* 1b */ 1993 #define REG_SCP_VRF18_ACK_MASK_LSB BIT(14) /* 1b */ 1994 #define REG_SSPM_APSRC_ACK_MASK_LSB BIT(15) /* 1b */ 1995 #define REG_SSPM_DDREN_ACK_MASK_LSB BIT(16) /* 1b */ 1996 #define REG_SSPM_EMI_ACK_MASK_LSB BIT(17) /* 1b */ 1997 #define REG_SSPM_INFRA_ACK_MASK_LSB BIT(18) /* 1b */ 1998 #define REG_SSPM_PMIC_ACK_MASK_LSB BIT(19) /* 1b */ 1999 #define REG_SSPM_SRCCLKENA_ACK_MASK_LSB BIT(20) /* 1b */ 2000 #define REG_SSPM_VRF18_ACK_MASK_LSB BIT(21) /* 1b */ 2001 #define REG_SSR_APSRC_ACK_MASK_LSB BIT(22) /* 1b */ 2002 #define REG_SSR_DDREN_ACK_MASK_LSB BIT(23) /* 1b */ 2003 #define REG_SSR_EMI_ACK_MASK_LSB BIT(24) /* 1b */ 2004 #define REG_SSR_INFRA_ACK_MASK_LSB BIT(25) /* 1b */ 2005 #define REG_SSR_PMIC_ACK_MASK_LSB BIT(26) /* 1b */ 2006 #define REG_SSR_SRCCLKENA_ACK_MASK_LSB BIT(27) /* 1b */ 2007 #define REG_SSR_VRF18_ACK_MASK_LSB BIT(28) /* 1b */ 2008 #define REG_UFS_APSRC_ACK_MASK_LSB BIT(29) /* 1b */ 2009 #define REG_UFS_DDREN_ACK_MASK_LSB BIT(30) /* 1b */ 2010 #define REG_UFS_EMI_ACK_MASK_LSB BIT(31) /* 1b */ 2011 /* SPM_RESOURCE_ACK_MASK_6 (0x1C001000+0x8B4) */ 2012 #define REG_UFS_INFRA_ACK_MASK_LSB BIT(0) /* 1b */ 2013 #define REG_UFS_PMIC_ACK_MASK_LSB BIT(1) /* 1b */ 2014 #define REG_UFS_SRCCLKENA_ACK_MASK_LSB BIT(2) /* 1b */ 2015 #define REG_UFS_VRF18_ACK_MASK_LSB BIT(3) /* 1b */ 2016 #define REG_VDEC_APSRC_ACK_MASK_LSB BIT(4) /* 1b */ 2017 #define REG_VDEC_DDREN_ACK_MASK_LSB BIT(5) /* 1b */ 2018 #define REG_VDEC_EMI_ACK_MASK_LSB BIT(6) /* 1b */ 2019 #define REG_VDEC_INFRA_ACK_MASK_LSB BIT(7) /* 1b */ 2020 #define REG_VDEC_PMIC_ACK_MASK_LSB BIT(8) /* 1b */ 2021 #define REG_VDEC_SRCCLKENA_ACK_MASK_LSB BIT(9) /* 1b */ 2022 #define REG_VDEC_VRF18_ACK_MASK_LSB BIT(10) /* 1b */ 2023 #define REG_VENC_APSRC_ACK_MASK_LSB BIT(11) /* 1b */ 2024 #define REG_VENC_DDREN_ACK_MASK_LSB BIT(12) /* 1b */ 2025 #define REG_VENC_EMI_ACK_MASK_LSB BIT(13) /* 1b */ 2026 #define REG_VENC_INFRA_ACK_MASK_LSB BIT(14) /* 1b */ 2027 #define REG_VENC_PMIC_ACK_MASK_LSB BIT(15) /* 1b */ 2028 #define REG_VENC_SRCCLKENA_ACK_MASK_LSB BIT(16) /* 1b */ 2029 #define REG_VENC_VRF18_ACK_MASK_LSB BIT(17) /* 1b */ 2030 /* SPM_EVENT_COUNTER_CLEAR (0x1C001000+0x8B8) */ 2031 #define REG_SPM_EVENT_COUNTER_CLR_LSB BIT(0) /* 1b */ 2032 /* SPM_VCORE_EVENT_COUNT_STA (0x1C001000+0x8BC) */ 2033 #define SPM_VCORE_SLEEP_COUNT_LSB BIT(0) /* 16b */ 2034 #define SPM_VCORE_WAKE_COUNT_LSB BIT(16) /* 16b */ 2035 /* SPM_PMIC_EVENT_COUNT_STA (0x1C001000+0x8C0) */ 2036 #define SPM_PMIC_SLEEP_COUNT_LSB BIT(0) /* 16b */ 2037 #define SPM_PMIC_WAKE_COUNT_LSB BIT(16) /* 16b */ 2038 /* SPM_SRCCLKENA_EVENT_COUNT_STA (0x1C001000+0x8C4) */ 2039 #define SPM_SRCCLKENA_SLEEP_COUNT_LSB BIT(0) /* 16b */ 2040 #define SPM_SRCCLKENA_WAKE_COUNT_LSB BIT(16) /* 16b */ 2041 /* SPM_INFRA_EVENT_COUNT_STA (0x1C001000+0x8C8) */ 2042 #define SPM_INFRA_SLEEP_COUNT_LSB BIT(0) /* 16b */ 2043 #define SPM_INFRA_WAKE_COUNT_LSB BIT(16) /* 16b */ 2044 /* SPM_VRF18_EVENT_COUNT_STA (0x1C001000+0x8CC) */ 2045 #define SPM_VRF18_SLEEP_COUNT_LSB BIT(0) /* 16b */ 2046 #define SPM_VRF18_WAKE_COUNT_LSB BIT(16) /* 16b */ 2047 /* SPM_EMI_EVENT_COUNT_STA (0x1C001000+0x8D0) */ 2048 #define SPM_EMI_SLEEP_COUNT_LSB BIT(0) /* 16b */ 2049 #define SPM_EMI_WAKE_COUNT_LSB BIT(16) /* 16b */ 2050 /* SPM_APSRC_EVENT_COUNT_STA (0x1C001000+0x8D4) */ 2051 #define SPM_APSRC_SLEEP_COUNT_LSB BIT(0) /* 16b */ 2052 #define SPM_APSRC_WAKE_COUNT_LSB BIT(16) /* 16b */ 2053 /* SPM_DDREN_EVENT_COUNT_STA (0x1C001000+0x8D8) */ 2054 #define SPM_DDREN_SLEEP_COUNT_LSB BIT(0) /* 16b */ 2055 #define SPM_DDREN_WAKE_COUNT_LSB BIT(16) /* 16b */ 2056 /* PCM_WDT_LATCH_0 (0x1C001000+0x8DC) */ 2057 #define PCM_WDT_LATCH_0_LSB BIT(0) /* 32b */ 2058 /* PCM_WDT_LATCH_1 (0x1C001000+0x8E0) */ 2059 #define PCM_WDT_LATCH_1_LSB BIT(0) /* 32b */ 2060 /* PCM_WDT_LATCH_2 (0x1C001000+0x8E4) */ 2061 #define PCM_WDT_LATCH_2_LSB BIT(0) /* 32b */ 2062 /* PCM_WDT_LATCH_3 (0x1C001000+0x8E8) */ 2063 #define PCM_WDT_LATCH_3_LSB BIT(0) /* 32b */ 2064 /* PCM_WDT_LATCH_4 (0x1C001000+0x8EC) */ 2065 #define PCM_WDT_LATCH_4_LSB BIT(0) /* 32b */ 2066 /* PCM_WDT_LATCH_5 (0x1C001000+0x8F0) */ 2067 #define PCM_WDT_LATCH_5_LSB BIT(0) /* 32b */ 2068 /* PCM_WDT_LATCH_6 (0x1C001000+0x8F4) */ 2069 #define PCM_WDT_LATCH_6_LSB BIT(0) /* 32b */ 2070 /* PCM_WDT_LATCH_7 (0x1C001000+0x8F8) */ 2071 #define PCM_WDT_LATCH_7_LSB BIT(0) /* 32b */ 2072 /* PCM_WDT_LATCH_8 (0x1C001000+0x8FC) */ 2073 #define PCM_WDT_LATCH_8_LSB BIT(0) /* 32b */ 2074 /* PCM_WDT_LATCH_9 (0x1C001000+0x900) */ 2075 #define PCM_WDT_LATCH_9_LSB BIT(0) /* 32b */ 2076 /* PCM_WDT_LATCH_10 (0x1C001000+0x904) */ 2077 #define PCM_WDT_LATCH_10_LSB BIT(0) /* 32b */ 2078 /* PCM_WDT_LATCH_11 (0x1C001000+0x908) */ 2079 #define PCM_WDT_LATCH_11_LSB BIT(0) /* 32b */ 2080 /* PCM_WDT_LATCH_12 (0x1C001000+0x90C) */ 2081 #define PCM_WDT_LATCH_12_LSB BIT(0) /* 32b */ 2082 /* PCM_WDT_LATCH_13 (0x1C001000+0x910) */ 2083 #define PCM_WDT_LATCH_13_LSB BIT(0) /* 32b */ 2084 /* PCM_WDT_LATCH_14 (0x1C001000+0x914) */ 2085 #define PCM_WDT_LATCH_14_LSB BIT(0) /* 32b */ 2086 /* PCM_WDT_LATCH_15 (0x1C001000+0x918) */ 2087 #define PCM_WDT_LATCH_15_LSB BIT(0) /* 32b */ 2088 /* PCM_WDT_LATCH_16 (0x1C001000+0x91C) */ 2089 #define PCM_WDT_LATCH_16_LSB BIT(0) /* 32b */ 2090 /* PCM_WDT_LATCH_17 (0x1C001000+0x920) */ 2091 #define PCM_WDT_LATCH_17_LSB BIT(0) /* 32b */ 2092 /* PCM_WDT_LATCH_18 (0x1C001000+0x924) */ 2093 #define PCM_WDT_LATCH_18_LSB BIT(0) /* 32b */ 2094 /* PCM_WDT_LATCH_19 (0x1C001000+0x928) */ 2095 #define PCM_WDT_LATCH_19_LSB BIT(0) /* 32b */ 2096 /* PCM_WDT_LATCH_20 (0x1C001000+0x92C) */ 2097 #define PCM_WDT_LATCH_20_LSB BIT(0) /* 32b */ 2098 /* PCM_WDT_LATCH_21 (0x1C001000+0x930) */ 2099 #define PCM_WDT_LATCH_21_LSB BIT(0) /* 32b */ 2100 /* PCM_WDT_LATCH_22 (0x1C001000+0x934) */ 2101 #define PCM_WDT_LATCH_22_LSB BIT(0) /* 32b */ 2102 /* PCM_WDT_LATCH_23 (0x1C001000+0x938) */ 2103 #define PCM_WDT_LATCH_23_LSB BIT(0) /* 32b */ 2104 /* PCM_WDT_LATCH_24 (0x1C001000+0x93C) */ 2105 #define PCM_WDT_LATCH_24_LSB BIT(0) /* 32b */ 2106 /* PCM_WDT_LATCH_25 (0x1C001000+0x940) */ 2107 #define PCM_WDT_LATCH_25_LSB BIT(0) /* 32b */ 2108 /* PCM_WDT_LATCH_26 (0x1C001000+0x944) */ 2109 #define PCM_WDT_LATCH_26_LSB BIT(0) /* 32b */ 2110 /* PCM_WDT_LATCH_27 (0x1C001000+0x948) */ 2111 #define PCM_WDT_LATCH_27_LSB BIT(0) /* 32b */ 2112 /* PCM_WDT_LATCH_28 (0x1C001000+0x94C) */ 2113 #define PCM_WDT_LATCH_28_LSB BIT(0) /* 32b */ 2114 /* PCM_WDT_LATCH_29 (0x1C001000+0x950) */ 2115 #define PCM_WDT_LATCH_29_LSB BIT(0) /* 32b */ 2116 /* PCM_WDT_LATCH_30 (0x1C001000+0x954) */ 2117 #define PCM_WDT_LATCH_30_LSB BIT(0) /* 32b */ 2118 /* PCM_WDT_LATCH_31 (0x1C001000+0x958) */ 2119 #define PCM_WDT_LATCH_31_LSB BIT(0) /* 32b */ 2120 /* PCM_WDT_LATCH_32 (0x1C001000+0x95C) */ 2121 #define PCM_WDT_LATCH_32_LSB BIT(0) /* 32b */ 2122 /* PCM_WDT_LATCH_33 (0x1C001000+0x960) */ 2123 #define PCM_WDT_LATCH_33_LSB BIT(0) /* 32b */ 2124 /* PCM_WDT_LATCH_34 (0x1C001000+0x964) */ 2125 #define PCM_WDT_LATCH_34_LSB BIT(0) /* 32b */ 2126 /* PCM_WDT_LATCH_35 (0x1C001000+0x968) */ 2127 #define PCM_WDT_LATCH_35_LSB BIT(0) /* 32b */ 2128 /* PCM_WDT_LATCH_36 (0x1C001000+0x96C) */ 2129 #define PCM_WDT_LATCH_36_LSB BIT(0) /* 32b */ 2130 /* PCM_WDT_LATCH_37 (0x1C001000+0x970) */ 2131 #define PCM_WDT_LATCH_37_LSB BIT(0) /* 32b */ 2132 /* PCM_WDT_LATCH_38 (0x1C001000+0x974) */ 2133 #define PCM_WDT_LATCH_38_LSB BIT(0) /* 32b */ 2134 /* PCM_WDT_LATCH_39 (0x1C001000+0x978) */ 2135 #define PCM_WDT_LATCH_39_LSB BIT(0) /* 32b */ 2136 /* PCM_WDT_LATCH_40 (0x1C001000+0x97C) */ 2137 #define PCM_WDT_LATCH_40_LSB BIT(0) /* 32b */ 2138 /* PCM_WDT_LATCH_SPARE_0 (0x1C001000+0x980) */ 2139 #define PCM_WDT_LATCH_SPARE_0_LSB BIT(0) /* 32b */ 2140 /* PCM_WDT_LATCH_SPARE_1 (0x1C001000+0x984) */ 2141 #define PCM_WDT_LATCH_SPARE_1_LSB BIT(0) /* 32b */ 2142 /* PCM_WDT_LATCH_SPARE_2 (0x1C001000+0x988) */ 2143 #define PCM_WDT_LATCH_SPARE_2_LSB BIT(0) /* 32b */ 2144 /* PCM_WDT_LATCH_SPARE_3 (0x1C001000+0x98C) */ 2145 #define PCM_WDT_LATCH_SPARE_3_LSB BIT(0) /* 32b */ 2146 /* PCM_WDT_LATCH_SPARE_4 (0x1C001000+0x990) */ 2147 #define PCM_WDT_LATCH_SPARE_4_LSB BIT(0) /* 32b */ 2148 /* PCM_WDT_LATCH_SPARE_5 (0x1C001000+0x994) */ 2149 #define PCM_WDT_LATCH_SPARE_5_LSB BIT(0) /* 32b */ 2150 /* PCM_WDT_LATCH_SPARE_6 (0x1C001000+0x998) */ 2151 #define PCM_WDT_LATCH_SPARE_6_LSB BIT(0) /* 32b */ 2152 /* PCM_WDT_LATCH_SPARE_7 (0x1C001000+0x99C) */ 2153 #define PCM_WDT_LATCH_SPARE_7_LSB BIT(0) /* 32b */ 2154 /* PCM_WDT_LATCH_SPARE_8 (0x1C001000+0x9A0) */ 2155 #define PCM_WDT_LATCH_SPARE_8_LSB BIT(0) /* 32b */ 2156 /* PCM_WDT_LATCH_SPARE_9 (0x1C001000+0x9A4) */ 2157 #define PCM_WDT_LATCH_SPARE_9_LSB BIT(0) /* 32b */ 2158 /* DRAMC_GATING_ERR_LATCH_0 (0x1C001000+0x9A8) */ 2159 #define DRAMC_GATING_ERR_LATCH_0_LSB BIT(0) /* 32b */ 2160 /* DRAMC_GATING_ERR_LATCH_1 (0x1C001000+0x9AC) */ 2161 #define DRAMC_GATING_ERR_LATCH_1_LSB BIT(0) /* 32b */ 2162 /* DRAMC_GATING_ERR_LATCH_2 (0x1C001000+0x9B0) */ 2163 #define DRAMC_GATING_ERR_LATCH_2_LSB BIT(0) /* 32b */ 2164 /* DRAMC_GATING_ERR_LATCH_3 (0x1C001000+0x9B4) */ 2165 #define DRAMC_GATING_ERR_LATCH_3_LSB BIT(0) /* 32b */ 2166 /* DRAMC_GATING_ERR_LATCH_4 (0x1C001000+0x9B8) */ 2167 #define DRAMC_GATING_ERR_LATCH_4_LSB BIT(0) /* 32b */ 2168 /* DRAMC_GATING_ERR_LATCH_5 (0x1C001000+0x9BC) */ 2169 #define DRAMC_GATING_ERR_LATCH_5_LSB BIT(0) /* 32b */ 2170 /* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x1C001000+0x9C0) */ 2171 #define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB BIT(0) /* 32b */ 2172 /* SPM_DEBUG_CON (0x1C001000+0x9C4) */ 2173 #define SPM_DEBUG_OUT_ENABLE_LSB BIT(0) /* 1b */ 2174 /* SPM_ACK_CHK_CON_0 (0x1C001000+0x9C8) */ 2175 #define SPM_ACK_CHK_SW_EN_0_LSB BIT(0) /* 1b */ 2176 #define SPM_ACK_CHK_CLR_ALL_0_LSB BIT(1) /* 1b */ 2177 #define SPM_ACK_CHK_CLR_TIMER_0_LSB BIT(2) /* 1b */ 2178 #define SPM_ACK_CHK_CLR_IRQ_0_LSB BIT(3) /* 1b */ 2179 #define SPM_ACK_CHK_STA_EN_0_LSB BIT(4) /* 1b */ 2180 #define SPM_ACK_CHK_WAKEUP_EN_0_LSB BIT(5) /* 1b */ 2181 #define SPM_ACK_CHK_WDT_EN_0_LSB BIT(6) /* 1b */ 2182 #define SPM_ACK_CHK_SWINT_EN_0_LSB BIT(7) /* 1b */ 2183 #define SPM_ACK_CHK_HW_EN_0_LSB BIT(8) /* 1b */ 2184 #define SPM_ACK_CHK_HW_MODE_0_LSB BIT(9) /* 3b */ 2185 #define SPM_ACK_CHK_FAIL_0_LSB BIT(15) /* 1b */ 2186 /* SPM_ACK_CHK_SEL_0 (0x1C001000+0x9CC) */ 2187 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB BIT(0) /* 5b */ 2188 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB BIT(5) /* 3b */ 2189 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB BIT(16) /* 5b */ 2190 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB BIT(21) /* 3b */ 2191 /* SPM_ACK_CHK_TIMER_0 (0x1C001000+0x9D0) */ 2192 #define SPM_ACK_CHK_TIMER_VAL_0_LSB BIT(0) /* 16b */ 2193 #define SPM_ACK_CHK_TIMER_0_LSB BIT(16) /* 16b */ 2194 /* SPM_ACK_CHK_STA_0 (0x1C001000+0x9D4) */ 2195 #define SPM_ACK_CHK_STA_0_LSB BIT(0) /* 32b */ 2196 /* SPM_ACK_CHK_CON_1 (0x1C001000+0x9D8) */ 2197 #define SPM_ACK_CHK_SW_EN_1_LSB BIT(0) /* 1b */ 2198 #define SPM_ACK_CHK_CLR_ALL_1_LSB BIT(1) /* 1b */ 2199 #define SPM_ACK_CHK_CLR_TIMER_1_LSB BIT(2) /* 1b */ 2200 #define SPM_ACK_CHK_CLR_IRQ_1_LSB BIT(3) /* 1b */ 2201 #define SPM_ACK_CHK_STA_EN_1_LSB BIT(4) /* 1b */ 2202 #define SPM_ACK_CHK_WAKEUP_EN_1_LSB BIT(5) /* 1b */ 2203 #define SPM_ACK_CHK_WDT_EN_1_LSB BIT(6) /* 1b */ 2204 #define SPM_ACK_CHK_SWINT_EN_1_LSB BIT(7) /* 1b */ 2205 #define SPM_ACK_CHK_HW_EN_1_LSB BIT(8) /* 1b */ 2206 #define SPM_ACK_CHK_HW_MODE_1_LSB BIT(9) /* 3b */ 2207 #define SPM_ACK_CHK_FAIL_1_LSB BIT(15) /* 1b */ 2208 /* SPM_ACK_CHK_SEL_1 (0x1C001000+0x9DC) */ 2209 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB BIT(0) /* 5b */ 2210 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB BIT(5) /* 3b */ 2211 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB BIT(16) /* 5b */ 2212 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB BIT(21) /* 3b */ 2213 /* SPM_ACK_CHK_TIMER_1 (0x1C001000+0x9E0) */ 2214 #define SPM_ACK_CHK_TIMER_VAL_1_LSB BIT(0) /* 16b */ 2215 #define SPM_ACK_CHK_TIMER_1_LSB BIT(16) /* 16b */ 2216 /* SPM_ACK_CHK_STA_1 (0x1C001000+0x9E4) */ 2217 #define SPM_ACK_CHK_STA_1_LSB BIT(0) /* 32b */ 2218 /* SPM_ACK_CHK_CON_2 (0x1C001000+0x9E8) */ 2219 #define SPM_ACK_CHK_SW_EN_2_LSB BIT(0) /* 1b */ 2220 #define SPM_ACK_CHK_CLR_ALL_2_LSB BIT(1) /* 1b */ 2221 #define SPM_ACK_CHK_CLR_TIMER_2_LSB BIT(2) /* 1b */ 2222 #define SPM_ACK_CHK_CLR_IRQ_2_LSB BIT(3) /* 1b */ 2223 #define SPM_ACK_CHK_STA_EN_2_LSB BIT(4) /* 1b */ 2224 #define SPM_ACK_CHK_WAKEUP_EN_2_LSB BIT(5) /* 1b */ 2225 #define SPM_ACK_CHK_WDT_EN_2_LSB BIT(6) /* 1b */ 2226 #define SPM_ACK_CHK_SWINT_EN_2_LSB BIT(7) /* 1b */ 2227 #define SPM_ACK_CHK_HW_EN_2_LSB BIT(8) /* 1b */ 2228 #define SPM_ACK_CHK_HW_MODE_2_LSB BIT(9) /* 3b */ 2229 #define SPM_ACK_CHK_FAIL_2_LSB BIT(15) /* 1b */ 2230 /* SPM_ACK_CHK_SEL_2 (0x1C001000+0x9EC) */ 2231 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB BIT(0) /* 5b */ 2232 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB BIT(5) /* 3b */ 2233 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB BIT(16) /* 5b */ 2234 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB BIT(21) /* 3b */ 2235 /* SPM_ACK_CHK_TIMER_2 (0x1C001000+0x9F0) */ 2236 #define SPM_ACK_CHK_TIMER_VAL_2_LSB BIT(0) /* 16b */ 2237 #define SPM_ACK_CHK_TIMER_2_LSB BIT(16) /* 16b */ 2238 /* SPM_ACK_CHK_STA_2 (0x1C001000+0x9F4) */ 2239 #define SPM_ACK_CHK_STA_2_LSB BIT(0) /* 32b */ 2240 /* SPM_ACK_CHK_CON_3 (0x1C001000+0x9F8) */ 2241 #define SPM_ACK_CHK_SW_EN_3_LSB BIT(0) /* 1b */ 2242 #define SPM_ACK_CHK_CLR_ALL_3_LSB BIT(1) /* 1b */ 2243 #define SPM_ACK_CHK_CLR_TIMER_3_LSB BIT(2) /* 1b */ 2244 #define SPM_ACK_CHK_CLR_IRQ_3_LSB BIT(3) /* 1b */ 2245 #define SPM_ACK_CHK_STA_EN_3_LSB BIT(4) /* 1b */ 2246 #define SPM_ACK_CHK_WAKEUP_EN_3_LSB BIT(5) /* 1b */ 2247 #define SPM_ACK_CHK_WDT_EN_3_LSB BIT(6) /* 1b */ 2248 #define SPM_ACK_CHK_SWINT_EN_3_LSB BIT(7) /* 1b */ 2249 #define SPM_ACK_CHK_HW_EN_3_LSB BIT(8) /* 1b */ 2250 #define SPM_ACK_CHK_HW_MODE_3_LSB BIT(9) /* 3b */ 2251 #define SPM_ACK_CHK_FAIL_3_LSB BIT(15) /* 1b */ 2252 /* SPM_ACK_CHK_SEL_3 (0x1C001000+0x9FC) */ 2253 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB BIT(0) /* 5b */ 2254 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB BIT(5) /* 3b */ 2255 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB BIT(16) /* 5b */ 2256 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB BIT(21) /* 3b */ 2257 /* MD1_PWR_CON (0x1C001000+0xE00) */ 2258 #define MD1_PWR_RST_B_LSB BIT(0) /* 1b */ 2259 #define MD1_PWR_ISO_LSB BIT(1) /* 1b */ 2260 #define MD1_PWR_ON_LSB BIT(2) /* 1b */ 2261 #define MD1_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2262 #define MD1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2263 #define MD1_RTFF_SAVE_LSB BIT(24) /* 1b */ 2264 #define MD1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2265 #define MD1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2266 #define SC_MD1_PWR_ACK_LSB BIT(30) /* 1b */ 2267 #define SC_MD1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2268 /* CONN_PWR_CON (0x1C001000+0xE04) */ 2269 #define CONN_PWR_RST_B_LSB BIT(0) /* 1b */ 2270 #define CONN_PWR_ISO_LSB BIT(1) /* 1b */ 2271 #define CONN_PWR_ON_LSB BIT(2) /* 1b */ 2272 #define CONN_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2273 #define CONN_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2274 #define CONN_RTFF_SAVE_LSB BIT(24) /* 1b */ 2275 #define CONN_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2276 #define CONN_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2277 #define SC_CONN_PWR_ACK_LSB BIT(30) /* 1b */ 2278 #define SC_CONN_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2279 /* IFR_PWR_CON (0x1C001000+0xE08) */ 2280 #define IFR_PWR_RST_B_LSB BIT(0) /* 1b */ 2281 #define IFR_PWR_ISO_LSB BIT(1) /* 1b */ 2282 #define IFR_PWR_ON_LSB BIT(2) /* 1b */ 2283 #define IFR_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2284 #define IFR_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2285 #define IFR_SRAM_CKISO_LSB BIT(5) /* 1b */ 2286 #define IFR_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2287 #define IFR_SRAM_PDN_LSB BIT(8) /* 1b */ 2288 #define IFR_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2289 #define SC_IFR_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2290 #define SC_IFR_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2291 #define IFR_RTFF_SAVE_LSB BIT(24) /* 1b */ 2292 #define IFR_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2293 #define IFR_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2294 #define SC_IFR_PWR_ACK_LSB BIT(30) /* 1b */ 2295 #define SC_IFR_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2296 /* PERI_PWR_CON (0x1C001000+0xE0C) */ 2297 #define PERI_PWR_RST_B_LSB BIT(0) /* 1b */ 2298 #define PERI_PWR_ISO_LSB BIT(1) /* 1b */ 2299 #define PERI_PWR_ON_LSB BIT(2) /* 1b */ 2300 #define PERI_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2301 #define PERI_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2302 #define PERI_SRAM_CKISO_LSB BIT(5) /* 1b */ 2303 #define PERI_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2304 #define PERI_SRAM_PDN_LSB BIT(8) /* 1b */ 2305 #define PERI_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2306 #define SC_PERI_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2307 #define SC_PERI_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2308 #define PERI_RTFF_SAVE_LSB BIT(24) /* 1b */ 2309 #define PERI_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2310 #define PERI_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2311 #define SC_PERI_PWR_ACK_LSB BIT(30) /* 1b */ 2312 #define SC_PERI_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2313 /* UFS0_PWR_CON (0x1C001000+0xE10) */ 2314 #define UFS0_PWR_RST_B_LSB BIT(0) /* 1b */ 2315 #define UFS0_PWR_ISO_LSB BIT(1) /* 1b */ 2316 #define UFS0_PWR_ON_LSB BIT(2) /* 1b */ 2317 #define UFS0_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2318 #define UFS0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2319 #define UFS0_SRAM_CKISO_LSB BIT(5) /* 1b */ 2320 #define UFS0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2321 #define UFS0_SRAM_PDN_LSB BIT(8) /* 1b */ 2322 #define UFS0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2323 #define SC_UFS0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2324 #define SC_UFS0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2325 #define UFS0_RTFF_SAVE_LSB BIT(24) /* 1b */ 2326 #define UFS0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2327 #define UFS0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2328 #define SC_UFS0_PWR_ACK_LSB BIT(30) /* 1b */ 2329 #define SC_UFS0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2330 /* UFS0_PHY_PWR_CON (0x1C001000+0xE14) */ 2331 #define UFS0_PHY_PWR_RST_B_LSB BIT(0) /* 1b */ 2332 #define UFS0_PHY_PWR_ISO_LSB BIT(1) /* 1b */ 2333 #define UFS0_PHY_PWR_ON_LSB BIT(2) /* 1b */ 2334 #define UFS0_PHY_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2335 #define UFS0_PHY_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2336 #define UFS0_PHY_RTFF_SAVE_LSB BIT(24) /* 1b */ 2337 #define UFS0_PHY_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2338 #define UFS0_PHY_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2339 #define SC_UFS0_PHY_PWR_ACK_LSB BIT(30) /* 1b */ 2340 #define SC_UFS0_PHY_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2341 /* AUDIO_PWR_CON (0x1C001000+0xE18) */ 2342 #define AUDIO_PWR_RST_B_LSB BIT(0) /* 1b */ 2343 #define AUDIO_PWR_ISO_LSB BIT(1) /* 1b */ 2344 #define AUDIO_PWR_ON_LSB BIT(2) /* 1b */ 2345 #define AUDIO_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2346 #define AUDIO_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2347 #define AUDIO_SRAM_PDN_LSB BIT(8) /* 1b */ 2348 #define SC_AUDIO_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2349 #define AUDIO_RTFF_SAVE_LSB BIT(24) /* 1b */ 2350 #define AUDIO_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2351 #define AUDIO_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2352 #define SC_AUDIO_PWR_ACK_LSB BIT(30) /* 1b */ 2353 #define SC_AUDIO_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2354 /* ADSP_TOP_PWR_CON (0x1C001000+0xE1C) */ 2355 #define ADSP_TOP_PWR_RST_B_LSB BIT(0) /* 1b */ 2356 #define ADSP_TOP_PWR_ISO_LSB BIT(1) /* 1b */ 2357 #define ADSP_TOP_PWR_ON_LSB BIT(2) /* 1b */ 2358 #define ADSP_TOP_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2359 #define ADSP_TOP_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2360 #define ADSP_TOP_SRAM_CKISO_LSB BIT(5) /* 1b */ 2361 #define ADSP_TOP_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2362 #define ADSP_TOP_SRAM_PDN_LSB BIT(8) /* 1b */ 2363 #define ADSP_TOP_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2364 #define SC_ADSP_TOP_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2365 #define SC_ADSP_TOP_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2366 #define ADSP_TOP_RTFF_SAVE_LSB BIT(24) /* 1b */ 2367 #define ADSP_TOP_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2368 #define ADSP_TOP_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2369 #define SC_ADSP_TOP_PWR_ACK_LSB BIT(30) /* 1b */ 2370 #define SC_ADSP_TOP_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2371 /* ADSP_INFRA_PWR_CON (0x1C001000+0xE20) */ 2372 #define ADSP_INFRA_PWR_RST_B_LSB BIT(0) /* 1b */ 2373 #define ADSP_INFRA_PWR_ISO_LSB BIT(1) /* 1b */ 2374 #define ADSP_INFRA_PWR_ON_LSB BIT(2) /* 1b */ 2375 #define ADSP_INFRA_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2376 #define ADSP_INFRA_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2377 #define ADSP_INFRA_RTFF_SAVE_LSB BIT(24) /* 1b */ 2378 #define ADSP_INFRA_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2379 #define ADSP_INFRA_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2380 #define SC_ADSP_INFRA_PWR_ACK_LSB BIT(30) /* 1b */ 2381 #define SC_ADSP_INFRA_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2382 /* ADSP_AO_PWR_CON (0x1C001000+0xE24) */ 2383 #define ADSP_AO_PWR_RST_B_LSB BIT(0) /* 1b */ 2384 #define ADSP_AO_PWR_ISO_LSB BIT(1) /* 1b */ 2385 #define ADSP_AO_PWR_ON_LSB BIT(2) /* 1b */ 2386 #define ADSP_AO_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2387 #define ADSP_AO_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2388 #define ADSP_AO_RTFF_SAVE_LSB BIT(24) /* 1b */ 2389 #define ADSP_AO_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2390 #define ADSP_AO_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2391 #define SC_ADSP_AO_PWR_ACK_LSB BIT(30) /* 1b */ 2392 #define SC_ADSP_AO_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2393 /* ISP_IMG1_PWR_CON (0x1C001000+0xE28) */ 2394 #define ISP_MAIN_PWR_RST_B_LSB BIT(0) /* 1b */ 2395 #define ISP_MAIN_PWR_ISO_LSB BIT(1) /* 1b */ 2396 #define ISP_MAIN_PWR_ON_LSB BIT(2) /* 1b */ 2397 #define ISP_MAIN_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2398 #define ISP_MAIN_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2399 #define ISP_MAIN_SRAM_PDN_LSB BIT(8) /* 1b */ 2400 #define SC_ISP_MAIN_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2401 #define ISP_MAIN_RTFF_SAVE_LSB BIT(24) /* 1b */ 2402 #define ISP_MAIN_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2403 #define ISP_MAIN_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2404 #define SC_ISP_MAIN_PWR_ACK_LSB BIT(30) /* 1b */ 2405 #define SC_ISP_MAIN_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2406 /* ISP_IMG2_PWR_CON (0x1C001000+0xE2C) */ 2407 #define ISP_DIP1_PWR_RST_B_LSB BIT(0) /* 1b */ 2408 #define ISP_DIP1_PWR_ISO_LSB BIT(1) /* 1b */ 2409 #define ISP_DIP1_PWR_ON_LSB BIT(2) /* 1b */ 2410 #define ISP_DIP1_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2411 #define ISP_DIP1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2412 #define ISP_DIP1_SRAM_PDN_LSB BIT(8) /* 1b */ 2413 #define SC_ISP_DIP1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2414 #define ISP_DIP1_RTFF_SAVE_LSB BIT(24) /* 1b */ 2415 #define ISP_DIP1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2416 #define ISP_DIP1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2417 #define SC_ISP_DIP1_PWR_ACK_LSB BIT(30) /* 1b */ 2418 #define SC_ISP_DIP1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2419 /* ISP_IPE_PWR_CON (0x1C001000+0xE30) */ 2420 #define ISP_IPE_PWR_RST_B_LSB BIT(0) /* 1b */ 2421 #define ISP_IPE_PWR_ISO_LSB BIT(1) /* 1b */ 2422 #define ISP_IPE_PWR_ON_LSB BIT(2) /* 1b */ 2423 #define ISP_IPE_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2424 #define ISP_IPE_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2425 #define ISP_IPE_SRAM_PDN_LSB BIT(8) /* 1b */ 2426 #define SC_ISP_IPE_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2427 #define ISP_IPE_RTFF_SAVE_LSB BIT(24) /* 1b */ 2428 #define ISP_IPE_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2429 #define ISP_IPE_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2430 #define SC_ISP_IPE_PWR_ACK_LSB BIT(30) /* 1b */ 2431 #define SC_ISP_IPE_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2432 /* ISP_VCORE_PWR_CON (0x1C001000+0xE34) */ 2433 #define ISP_VCORE_PWR_RST_B_LSB BIT(0) /* 1b */ 2434 #define ISP_VCORE_PWR_ISO_LSB BIT(1) /* 1b */ 2435 #define ISP_VCORE_PWR_ON_LSB BIT(2) /* 1b */ 2436 #define ISP_VCORE_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2437 #define ISP_VCORE_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2438 #define ISP_VCORE_RTFF_SAVE_LSB BIT(24) /* 1b */ 2439 #define ISP_VCORE_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2440 #define ISP_VCORE_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2441 #define SC_ISP_VCORE_PWR_ACK_LSB BIT(30) /* 1b */ 2442 #define SC_ISP_VCORE_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2443 /* VDE0_PWR_CON (0x1C001000+0xE38) */ 2444 #define VDE0_PWR_RST_B_LSB BIT(0) /* 1b */ 2445 #define VDE0_PWR_ISO_LSB BIT(1) /* 1b */ 2446 #define VDE0_PWR_ON_LSB BIT(2) /* 1b */ 2447 #define VDE0_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2448 #define VDE0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2449 #define VDE0_SRAM_PDN_LSB BIT(8) /* 1b */ 2450 #define SC_VDE0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2451 #define VDE0_RTFF_SAVE_LSB BIT(24) /* 1b */ 2452 #define VDE0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2453 #define VDE0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2454 #define SC_VDE0_PWR_ACK_LSB BIT(30) /* 1b */ 2455 #define SC_VDE0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2456 /* VDE1_PWR_CON (0x1C001000+0xE3C) */ 2457 #define VDE1_PWR_RST_B_LSB BIT(0) /* 1b */ 2458 #define VDE1_PWR_ISO_LSB BIT(1) /* 1b */ 2459 #define VDE1_PWR_ON_LSB BIT(2) /* 1b */ 2460 #define VDE1_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2461 #define VDE1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2462 #define VDE1_SRAM_PDN_LSB BIT(8) /* 1b */ 2463 #define SC_VDE1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2464 #define VDE1_RTFF_SAVE_LSB BIT(24) /* 1b */ 2465 #define VDE1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2466 #define VDE1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2467 #define SC_VDE1_PWR_ACK_LSB BIT(30) /* 1b */ 2468 #define SC_VDE1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2469 /* VEN0_PWR_CON (0x1C001000+0xE40) */ 2470 #define VEN0_PWR_RST_B_LSB BIT(0) /* 1b */ 2471 #define VEN0_PWR_ISO_LSB BIT(1) /* 1b */ 2472 #define VEN0_PWR_ON_LSB BIT(2) /* 1b */ 2473 #define VEN0_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2474 #define VEN0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2475 #define VEN0_SRAM_PDN_LSB BIT(8) /* 1b */ 2476 #define SC_VEN0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2477 #define VEN0_RTFF_SAVE_LSB BIT(24) /* 1b */ 2478 #define VEN0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2479 #define VEN0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2480 #define SC_VEN0_PWR_ACK_LSB BIT(30) /* 1b */ 2481 #define SC_VEN0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2482 /* VEN1_PWR_CON (0x1C001000+0xE44) */ 2483 #define VEN1_PWR_RST_B_LSB BIT(0) /* 1b */ 2484 #define VEN1_PWR_ISO_LSB BIT(1) /* 1b */ 2485 #define VEN1_PWR_ON_LSB BIT(2) /* 1b */ 2486 #define VEN1_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2487 #define VEN1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2488 #define VEN1_SRAM_PDN_LSB BIT(8) /* 1b */ 2489 #define SC_VEN1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2490 #define VEN1_RTFF_SAVE_LSB BIT(24) /* 1b */ 2491 #define VEN1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2492 #define VEN1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2493 #define SC_VEN1_PWR_ACK_LSB BIT(30) /* 1b */ 2494 #define SC_VEN1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2495 /* CAM_MAIN_PWR_CON (0x1C001000+0xE48) */ 2496 #define CAM_MAIN_PWR_RST_B_LSB BIT(0) /* 1b */ 2497 #define CAM_MAIN_PWR_ISO_LSB BIT(1) /* 1b */ 2498 #define CAM_MAIN_PWR_ON_LSB BIT(2) /* 1b */ 2499 #define CAM_MAIN_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2500 #define CAM_MAIN_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2501 #define CAM_MAIN_SRAM_PDN_LSB BIT(8) /* 1b */ 2502 #define SC_CAM_MAIN_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2503 #define CAM_MAIN_RTFF_SAVE_LSB BIT(24) /* 1b */ 2504 #define CAM_MAIN_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2505 #define CAM_MAIN_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2506 #define SC_CAM_MAIN_PWR_ACK_LSB BIT(30) /* 1b */ 2507 #define SC_CAM_MAIN_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2508 /* CAM_MRAW_PWR_CON (0x1C001000+0xE4C) */ 2509 #define CAM_MRAW_PWR_RST_B_LSB BIT(0) /* 1b */ 2510 #define CAM_MRAW_PWR_ISO_LSB BIT(1) /* 1b */ 2511 #define CAM_MRAW_PWR_ON_LSB BIT(2) /* 1b */ 2512 #define CAM_MRAW_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2513 #define CAM_MRAW_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2514 #define CAM_MRAW_SRAM_PDN_LSB BIT(8) /* 1b */ 2515 #define SC_CAM_MRAW_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2516 #define CAM_MRAW_RTFF_SAVE_LSB BIT(24) /* 1b */ 2517 #define CAM_MRAW_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2518 #define CAM_MRAW_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2519 #define SC_CAM_MRAW_PWR_ACK_LSB BIT(30) /* 1b */ 2520 #define SC_CAM_MRAW_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2521 /* CAM_SUBA_PWR_CON (0x1C001000+0xE50) */ 2522 #define CAM_SUBA_PWR_RST_B_LSB BIT(0) /* 1b */ 2523 #define CAM_SUBA_PWR_ISO_LSB BIT(1) /* 1b */ 2524 #define CAM_SUBA_PWR_ON_LSB BIT(2) /* 1b */ 2525 #define CAM_SUBA_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2526 #define CAM_SUBA_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2527 #define CAM_SUBA_SRAM_PDN_LSB BIT(8) /* 1b */ 2528 #define SC_CAM_SUBA_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2529 #define CAM_SUBA_RTFF_SAVE_LSB BIT(24) /* 1b */ 2530 #define CAM_SUBA_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2531 #define CAM_SUBA_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2532 #define SC_CAM_SUBA_PWR_ACK_LSB BIT(30) /* 1b */ 2533 #define SC_CAM_SUBA_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2534 /* CAM_SUBB_PWR_CON (0x1C001000+0xE54) */ 2535 #define CAM_SUBB_PWR_RST_B_LSB BIT(0) /* 1b */ 2536 #define CAM_SUBB_PWR_ISO_LSB BIT(1) /* 1b */ 2537 #define CAM_SUBB_PWR_ON_LSB BIT(2) /* 1b */ 2538 #define CAM_SUBB_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2539 #define CAM_SUBB_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2540 #define CAM_SUBB_SRAM_PDN_LSB BIT(8) /* 1b */ 2541 #define SC_CAM_SUBB_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2542 #define CAM_SUBB_RTFF_SAVE_LSB BIT(24) /* 1b */ 2543 #define CAM_SUBB_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2544 #define CAM_SUBB_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2545 #define SC_CAM_SUBB_PWR_ACK_LSB BIT(30) /* 1b */ 2546 #define SC_CAM_SUBB_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2547 /* CAM_SUBC_PWR_CON (0x1C001000+0xE58) */ 2548 #define CAM_SUBC_PWR_RST_B_LSB BIT(0) /* 1b */ 2549 #define CAM_SUBC_PWR_ISO_LSB BIT(1) /* 1b */ 2550 #define CAM_SUBC_PWR_ON_LSB BIT(2) /* 1b */ 2551 #define CAM_SUBC_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2552 #define CAM_SUBC_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2553 #define CAM_SUBC_SRAM_PDN_LSB BIT(8) /* 1b */ 2554 #define SC_CAM_SUBC_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2555 #define CAM_SUBC_RTFF_SAVE_LSB BIT(24) /* 1b */ 2556 #define CAM_SUBC_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2557 #define CAM_SUBC_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2558 #define SC_CAM_SUBC_PWR_ACK_LSB BIT(30) /* 1b */ 2559 #define SC_CAM_SUBC_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2560 /* CAM_VCORE_PWR_CON (0x1C001000+0xE5C) */ 2561 #define CAM_VCORE_PWR_RST_B_LSB BIT(0) /* 1b */ 2562 #define CAM_VCORE_PWR_ISO_LSB BIT(1) /* 1b */ 2563 #define CAM_VCORE_PWR_ON_LSB BIT(2) /* 1b */ 2564 #define CAM_VCORE_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2565 #define CAM_VCORE_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2566 #define CAM_VCORE_RTFF_SAVE_LSB BIT(24) /* 1b */ 2567 #define CAM_VCORE_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2568 #define CAM_VCORE_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2569 #define SC_CAM_VCORE_PWR_ACK_LSB BIT(30) /* 1b */ 2570 #define SC_CAM_VCORE_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2571 /* CAM_CCU_PWR_CON (0x1C001000+0xE60) */ 2572 #define CAM_CCU_PWR_RST_B_LSB BIT(0) /* 1b */ 2573 #define CAM_CCU_PWR_ISO_LSB BIT(1) /* 1b */ 2574 #define CAM_CCU_PWR_ON_LSB BIT(2) /* 1b */ 2575 #define CAM_CCU_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2576 #define CAM_CCU_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2577 #define CAM_CCU_SRAM_PDN_LSB BIT(8) /* 1b */ 2578 #define SC_CAM_CCU_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2579 #define CAM_CCU_RTFF_SAVE_LSB BIT(24) /* 1b */ 2580 #define CAM_CCU_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2581 #define CAM_CCU_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2582 #define SC_CAM_CCU_PWR_ACK_LSB BIT(30) /* 1b */ 2583 #define SC_CAM_CCU_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2584 /* CAM_CCU_AO_PWR_CON (0x1C001000+0xE64) */ 2585 #define CAM_CCU_AO_PWR_RST_B_LSB BIT(0) /* 1b */ 2586 #define CAM_CCU_AO_PWR_ISO_LSB BIT(1) /* 1b */ 2587 #define CAM_CCU_AO_PWR_ON_LSB BIT(2) /* 1b */ 2588 #define CAM_CCU_AO_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2589 #define CAM_CCU_AO_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2590 #define CAM_CCU_AO_SRAM_CKISO_LSB BIT(5) /* 1b */ 2591 #define CAM_CCU_AO_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2592 #define CAM_CCU_AO_SRAM_PDN_LSB BIT(8) /* 1b */ 2593 #define CAM_CCU_AO_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2594 #define SC_CAM_CCU_AO_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2595 #define SC_CAM_CCU_AO_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2596 #define CAM_CCU_AO_RTFF_SAVE_LSB BIT(24) /* 1b */ 2597 #define CAM_CCU_AO_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2598 #define CAM_CCU_AO_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2599 #define SC_CAM_CCU_AO_PWR_ACK_LSB BIT(30) /* 1b */ 2600 #define SC_CAM_CCU_AO_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2601 /* MDP0_PWR_CON (0x1C001000+0xE68) */ 2602 #define MDP0_PWR_RST_B_LSB BIT(0) /* 1b */ 2603 #define MDP0_PWR_ISO_LSB BIT(1) /* 1b */ 2604 #define MDP0_PWR_ON_LSB BIT(2) /* 1b */ 2605 #define MDP0_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2606 #define MDP0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2607 #define MDP0_SRAM_PDN_LSB BIT(8) /* 1b */ 2608 #define SC_MDP0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2609 #define MDP0_RTFF_SAVE_LSB BIT(24) /* 1b */ 2610 #define MDP0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2611 #define MDP0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2612 #define SC_MDP0_PWR_ACK_LSB BIT(30) /* 1b */ 2613 #define SC_MDP0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2614 /* MDP1_PWR_CON (0x1C001000+0xE6C) */ 2615 #define MDP1_PWR_RST_B_LSB BIT(0) /* 1b */ 2616 #define MDP1_PWR_ISO_LSB BIT(1) /* 1b */ 2617 #define MDP1_PWR_ON_LSB BIT(2) /* 1b */ 2618 #define MDP1_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2619 #define MDP1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2620 #define MDP1_SRAM_PDN_LSB BIT(8) /* 1b */ 2621 #define SC_MDP1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2622 #define MDP1_RTFF_SAVE_LSB BIT(24) /* 1b */ 2623 #define MDP1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2624 #define MDP1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2625 #define SC_MDP1_PWR_ACK_LSB BIT(30) /* 1b */ 2626 #define SC_MDP1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2627 /* DIS0_PWR_CON (0x1C001000+0xE70) */ 2628 #define DIS0_PWR_RST_B_LSB BIT(0) /* 1b */ 2629 #define DIS0_PWR_ISO_LSB BIT(1) /* 1b */ 2630 #define DIS0_PWR_ON_LSB BIT(2) /* 1b */ 2631 #define DIS0_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2632 #define DIS0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2633 #define DIS0_SRAM_CKISO_LSB BIT(5) /* 1b */ 2634 #define DIS0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2635 #define DIS0_SRAM_PDN_LSB BIT(8) /* 1b */ 2636 #define DIS0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2637 #define SC_DIS0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2638 #define SC_DIS0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2639 #define DIS0_RTFF_SAVE_LSB BIT(24) /* 1b */ 2640 #define DIS0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2641 #define DIS0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2642 #define SC_DIS0_PWR_ACK_LSB BIT(30) /* 1b */ 2643 #define SC_DIS0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2644 /* DIS1_PWR_CON (0x1C001000+0xE74) */ 2645 #define DIS1_PWR_RST_B_LSB BIT(0) /* 1b */ 2646 #define DIS1_PWR_ISO_LSB BIT(1) /* 1b */ 2647 #define DIS1_PWR_ON_LSB BIT(2) /* 1b */ 2648 #define DIS1_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2649 #define DIS1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2650 #define DIS1_SRAM_PDN_LSB BIT(8) /* 1b */ 2651 #define SC_DIS1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2652 #define DIS1_RTFF_SAVE_LSB BIT(24) /* 1b */ 2653 #define DIS1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2654 #define DIS1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2655 #define SC_DIS1_PWR_ACK_LSB BIT(30) /* 1b */ 2656 #define SC_DIS1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2657 /* MM_INFRA_PWR_CON (0x1C001000+0xE78) */ 2658 #define MM_INFRA_PWR_RST_B_LSB BIT(0) /* 1b */ 2659 #define MM_INFRA_PWR_ISO_LSB BIT(1) /* 1b */ 2660 #define MM_INFRA_PWR_ON_LSB BIT(2) /* 1b */ 2661 #define MM_INFRA_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2662 #define MM_INFRA_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2663 #define MM_INFRA_SRAM_CKISO_LSB BIT(5) /* 1b */ 2664 #define MM_INFRA_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2665 #define MM_INFRA_SRAM_PDN_LSB BIT(8) /* 1b */ 2666 #define MM_INFRA_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2667 #define SC_MM_INFRA_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2668 #define SC_MM_INFRA_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2669 #define MM_INFRA_RTFF_SAVE_LSB BIT(24) /* 1b */ 2670 #define MM_INFRA_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2671 #define MM_INFRA_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2672 #define SC_MM_INFRA_PWR_ACK_LSB BIT(30) /* 1b */ 2673 #define SC_MM_INFRA_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2674 /* MM_PROC_PWR_CON (0x1C001000+0xE7C) */ 2675 #define MM_PROC_PWR_RST_B_LSB BIT(0) /* 1b */ 2676 #define MM_PROC_PWR_ISO_LSB BIT(1) /* 1b */ 2677 #define MM_PROC_PWR_ON_LSB BIT(2) /* 1b */ 2678 #define MM_PROC_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2679 #define MM_PROC_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2680 #define MM_PROC_SRAM_CKISO_LSB BIT(5) /* 1b */ 2681 #define MM_PROC_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2682 #define MM_PROC_SRAM_PDN_LSB BIT(8) /* 1b */ 2683 #define MM_PROC_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2684 #define SC_MM_PROC_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2685 #define SC_MM_PROC_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2686 #define MM_PROC_RTFF_SAVE_LSB BIT(24) /* 1b */ 2687 #define MM_PROC_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2688 #define MM_PROC_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2689 #define SC_MM_PROC_PWR_ACK_LSB BIT(30) /* 1b */ 2690 #define SC_MM_PROC_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2691 /* DP_TX_PWR_CON (0x1C001000+0xE80) */ 2692 #define DP_TX_PWR_RST_B_LSB BIT(0) /* 1b */ 2693 #define DP_TX_PWR_ISO_LSB BIT(1) /* 1b */ 2694 #define DP_TX_PWR_ON_LSB BIT(2) /* 1b */ 2695 #define DP_TX_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2696 #define DP_TX_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2697 #define DP_TX_SRAM_PDN_LSB BIT(8) /* 1b */ 2698 #define SC_DP_TX_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2699 #define DP_TX_RTFF_SAVE_LSB BIT(24) /* 1b */ 2700 #define DP_TX_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2701 #define DP_TX_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2702 #define SC_DP_TX_PWR_ACK_LSB BIT(30) /* 1b */ 2703 #define SC_DP_TX_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2704 /* SCP_CORE_PWR_CON (0x1C001000+0xE84) */ 2705 #define SCP_CORE_PWR_RST_B_LSB BIT(0) /* 1b */ 2706 #define SCP_CORE_PWR_ISO_LSB BIT(1) /* 1b */ 2707 #define SCP_CORE_PWR_ON_LSB BIT(2) /* 1b */ 2708 #define SCP_CORE_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2709 #define SCP_CORE_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2710 #define SCP_CORE_SRAM_CKISO_LSB BIT(5) /* 1b */ 2711 #define SCP_CORE_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2712 #define SCP_CORE_SRAM_PDN_LSB BIT(8) /* 1b */ 2713 #define SCP_CORE_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2714 #define SC_SCP_CORE_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2715 #define SC_SCP_CORE_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2716 #define SCP_CORE_RTFF_SAVE_LSB BIT(24) /* 1b */ 2717 #define SCP_CORE_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2718 #define SCP_CORE_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2719 #define SC_SCP_CORE_PWR_ACK_LSB BIT(30) /* 1b */ 2720 #define SC_SCP_CORE_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2721 /* SCP_PERI_PWR_CON (0x1C001000+0xE88) */ 2722 #define SCP_PERI_PWR_RST_B_LSB BIT(0) /* 1b */ 2723 #define SCP_PERI_PWR_ISO_LSB BIT(1) /* 1b */ 2724 #define SCP_PERI_PWR_ON_LSB BIT(2) /* 1b */ 2725 #define SCP_PERI_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2726 #define SCP_PERI_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2727 #define SCP_PERI_SRAM_CKISO_LSB BIT(5) /* 1b */ 2728 #define SCP_PERI_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2729 #define SCP_PERI_SRAM_PDN_LSB BIT(8) /* 1b */ 2730 #define SCP_PERI_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2731 #define SC_SCP_PERI_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2732 #define SC_SCP_PERI_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2733 #define SCP_PERI_RTFF_SAVE_LSB BIT(24) /* 1b */ 2734 #define SCP_PERI_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2735 #define SCP_PERI_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2736 #define SC_SCP_PERI_PWR_ACK_LSB BIT(30) /* 1b */ 2737 #define SC_SCP_PERI_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2738 /* DPM0_PWR_CON (0x1C001000+0xE8C) */ 2739 #define DPM0_PWR_RST_B_LSB BIT(0) /* 1b */ 2740 #define DPM0_PWR_ISO_LSB BIT(1) /* 1b */ 2741 #define DPM0_PWR_ON_LSB BIT(2) /* 1b */ 2742 #define DPM0_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2743 #define DPM0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2744 #define DPM0_SRAM_CKISO_LSB BIT(5) /* 1b */ 2745 #define DPM0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2746 #define DPM0_SRAM_PDN_LSB BIT(8) /* 1b */ 2747 #define DPM0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2748 #define SC_DPM0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2749 #define SC_DPM0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2750 #define DPM0_RTFF_SAVE_LSB BIT(24) /* 1b */ 2751 #define DPM0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2752 #define DPM0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2753 #define SC_DPM0_PWR_ACK_LSB BIT(30) /* 1b */ 2754 #define SC_DPM0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2755 /* DPM1_PWR_CON (0x1C001000+0xE90) */ 2756 #define DPM1_PWR_RST_B_LSB BIT(0) /* 1b */ 2757 #define DPM1_PWR_ISO_LSB BIT(1) /* 1b */ 2758 #define DPM1_PWR_ON_LSB BIT(2) /* 1b */ 2759 #define DPM1_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2760 #define DPM1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2761 #define DPM1_SRAM_CKISO_LSB BIT(5) /* 1b */ 2762 #define DPM1_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2763 #define DPM1_SRAM_PDN_LSB BIT(8) /* 1b */ 2764 #define DPM1_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2765 #define SC_DPM1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2766 #define SC_DPM1_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2767 #define DPM1_RTFF_SAVE_LSB BIT(24) /* 1b */ 2768 #define DPM1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2769 #define DPM1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2770 #define SC_DPM1_PWR_ACK_LSB BIT(30) /* 1b */ 2771 #define SC_DPM1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2772 /* EMI0_PWR_CON (0x1C001000+0xE94) */ 2773 #define EMI0_PWR_RST_B_LSB BIT(0) /* 1b */ 2774 #define EMI0_PWR_ISO_LSB BIT(1) /* 1b */ 2775 #define EMI0_PWR_ON_LSB BIT(2) /* 1b */ 2776 #define EMI0_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2777 #define EMI0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2778 #define EMI0_SRAM_CKISO_LSB BIT(5) /* 1b */ 2779 #define EMI0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2780 #define EMI0_SRAM_PDN_LSB BIT(8) /* 1b */ 2781 #define EMI0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2782 #define SC_EMI0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2783 #define SC_EMI0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2784 #define EMI0_RTFF_SAVE_LSB BIT(24) /* 1b */ 2785 #define EMI0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2786 #define EMI0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2787 #define SC_EMI0_PWR_ACK_LSB BIT(30) /* 1b */ 2788 #define SC_EMI0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2789 /* EMI1_PWR_CON (0x1C001000+0xE98) */ 2790 #define EMI1_PWR_RST_B_LSB BIT(0) /* 1b */ 2791 #define EMI1_PWR_ISO_LSB BIT(1) /* 1b */ 2792 #define EMI1_PWR_ON_LSB BIT(2) /* 1b */ 2793 #define EMI1_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2794 #define EMI1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2795 #define EMI1_SRAM_CKISO_LSB BIT(5) /* 1b */ 2796 #define EMI1_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2797 #define EMI1_SRAM_PDN_LSB BIT(8) /* 1b */ 2798 #define EMI1_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2799 #define SC_EMI1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2800 #define SC_EMI1_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2801 #define EMI1_RTFF_SAVE_LSB BIT(24) /* 1b */ 2802 #define EMI1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2803 #define EMI1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2804 #define SC_EMI1_PWR_ACK_LSB BIT(30) /* 1b */ 2805 #define SC_EMI1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2806 /* CSI_RX_PWR_CON (0x1C001000+0xE9C) */ 2807 #define CSI_RX_PWR_RST_B_LSB BIT(0) /* 1b */ 2808 #define CSI_RX_PWR_ISO_LSB BIT(1) /* 1b */ 2809 #define CSI_RX_PWR_ON_LSB BIT(2) /* 1b */ 2810 #define CSI_RX_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2811 #define CSI_RX_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2812 #define CSI_RX_SRAM_PDN_LSB BIT(8) /* 1b */ 2813 #define SC_CSI_RX_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2814 #define CSI_RX_RTFF_SAVE_LSB BIT(24) /* 1b */ 2815 #define CSI_RX_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2816 #define CSI_RX_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2817 #define SC_CSI_RX_PWR_ACK_LSB BIT(30) /* 1b */ 2818 #define SC_CSI_RX_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2819 /* SSRSYS_PWR_CON (0x1C001000+0xEA0) */ 2820 #define SSRSYS_PWR_RST_B_LSB BIT(0) /* 1b */ 2821 #define SSRSYS_PWR_ISO_LSB BIT(1) /* 1b */ 2822 #define SSRSYS_PWR_ON_LSB BIT(2) /* 1b */ 2823 #define SSRSYS_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2824 #define SSRSYS_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2825 #define SSRSYS_SRAM_CKISO_LSB BIT(5) /* 1b */ 2826 #define SSRSYS_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2827 #define SSRSYS_SRAM_PDN_LSB BIT(8) /* 1b */ 2828 #define SSRSYS_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2829 #define SC_SSRSYS_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2830 #define SC_SSRSYS_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2831 #define SSRSYS_RTFF_SAVE_LSB BIT(24) /* 1b */ 2832 #define SSRSYS_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2833 #define SSRSYS_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2834 #define SC_SSRSYS_PWR_ACK_LSB BIT(30) /* 1b */ 2835 #define SC_SSRSYS_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2836 /* SSPM_PWR_CON (0x1C001000+0xEA4) */ 2837 #define SSPM_PWR_RST_B_LSB BIT(0) /* 1b */ 2838 #define SSPM_PWR_ISO_LSB BIT(1) /* 1b */ 2839 #define SSPM_PWR_ON_LSB BIT(2) /* 1b */ 2840 #define SSPM_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2841 #define SSPM_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2842 #define SSPM_RTFF_SAVE_LSB BIT(24) /* 1b */ 2843 #define SSPM_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2844 #define SSPM_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2845 #define SC_SSPM_PWR_ACK_LSB BIT(30) /* 1b */ 2846 #define SC_SSPM_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2847 /* SSUSB_PWR_CON (0x1C001000+0xEA8) */ 2848 #define SSUSB_PWR_RST_B_LSB BIT(0) /* 1b */ 2849 #define SSUSB_PWR_ISO_LSB BIT(1) /* 1b */ 2850 #define SSUSB_PWR_ON_LSB BIT(2) /* 1b */ 2851 #define SSUSB_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2852 #define SSUSB_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2853 #define SSUSB_SRAM_PDN_LSB BIT(8) /* 1b */ 2854 #define SC_SSUSB_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2855 #define SSUSB_RTFF_SAVE_LSB BIT(24) /* 1b */ 2856 #define SSUSB_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2857 #define SSUSB_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2858 #define SC_SSUSB_PWR_ACK_LSB BIT(30) /* 1b */ 2859 #define SC_SSUSB_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2860 /* SSUSB_PHY_PWR_CON (0x1C001000+0xEAC) */ 2861 #define SSUSB_PHY_PWR_RST_B_LSB BIT(0) /* 1b */ 2862 #define SSUSB_PHY_PWR_ISO_LSB BIT(1) /* 1b */ 2863 #define SSUSB_PHY_PWR_ON_LSB BIT(2) /* 1b */ 2864 #define SSUSB_PHY_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2865 #define SSUSB_PHY_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2866 #define SSUSB_PHY_RTFF_SAVE_LSB BIT(24) /* 1b */ 2867 #define SSUSB_PHY_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2868 #define SSUSB_PHY_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2869 #define SC_SSUSB_PHY_PWR_ACK_LSB BIT(30) /* 1b */ 2870 #define SC_SSUSB_PHY_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2871 /* CPUEB_PWR_CON (0x1C001000+0xEB0) */ 2872 #define CPUEB_PWR_RST_B_LSB BIT(0) /* 1b */ 2873 #define CPUEB_PWR_ISO_LSB BIT(1) /* 1b */ 2874 #define CPUEB_PWR_ON_LSB BIT(2) /* 1b */ 2875 #define CPUEB_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2876 #define CPUEB_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2877 #define CPUEB_SRAM_CKISO_LSB BIT(5) /* 1b */ 2878 #define CPUEB_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2879 #define CPUEB_SRAM_PDN_LSB BIT(8) /* 1b */ 2880 #define CPUEB_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2881 #define SC_CPUEB_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2882 #define SC_CPUEB_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2883 #define CPUEB_RTFF_SAVE_LSB BIT(24) /* 1b */ 2884 #define CPUEB_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2885 #define CPUEB_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2886 #define SC_CPUEB_PWR_ACK_LSB BIT(30) /* 1b */ 2887 #define SC_CPUEB_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2888 /* MFG0_PWR_CON (0x1C001000+0xEB4) */ 2889 #define MFG0_PWR_RST_B_LSB BIT(0) /* 1b */ 2890 #define MFG0_PWR_ISO_LSB BIT(1) /* 1b */ 2891 #define MFG0_PWR_ON_LSB BIT(2) /* 1b */ 2892 #define MFG0_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2893 #define MFG0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2894 #define MFG0_SRAM_CKISO_LSB BIT(5) /* 1b */ 2895 #define MFG0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ 2896 #define MFG0_SRAM_PDN_LSB BIT(8) /* 1b */ 2897 #define MFG0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ 2898 #define SC_MFG0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2899 #define SC_MFG0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ 2900 #define MFG0_RTFF_SAVE_LSB BIT(24) /* 1b */ 2901 #define MFG0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2902 #define MFG0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2903 #define SC_MFG0_PWR_ACK_LSB BIT(30) /* 1b */ 2904 #define SC_MFG0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2905 /* MFG1_PWR_CON (0x1C001000+0xEB8) */ 2906 #define MFG1_PWR_RST_B_LSB BIT(0) /* 1b */ 2907 #define MFG1_PWR_ISO_LSB BIT(1) /* 1b */ 2908 #define MFG1_PWR_ON_LSB BIT(2) /* 1b */ 2909 #define MFG1_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2910 #define MFG1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2911 #define MFG1_SRAM_PDN_LSB BIT(8) /* 1b */ 2912 #define SC_MFG1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2913 #define MFG1_RTFF_SAVE_LSB BIT(24) /* 1b */ 2914 #define MFG1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2915 #define MFG1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2916 #define SC_MFG1_PWR_ACK_LSB BIT(30) /* 1b */ 2917 #define SC_MFG1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2918 /* MFG2_PWR_CON (0x1C001000+0xEBC) */ 2919 #define MFG2_PWR_RST_B_LSB BIT(0) /* 1b */ 2920 #define MFG2_PWR_ISO_LSB BIT(1) /* 1b */ 2921 #define MFG2_PWR_ON_LSB BIT(2) /* 1b */ 2922 #define MFG2_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2923 #define MFG2_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2924 #define MFG2_SRAM_PDN_LSB BIT(8) /* 1b */ 2925 #define SC_MFG2_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2926 #define MFG2_RTFF_SAVE_LSB BIT(24) /* 1b */ 2927 #define MFG2_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2928 #define MFG2_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2929 #define SC_MFG2_PWR_ACK_LSB BIT(30) /* 1b */ 2930 #define SC_MFG2_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2931 /* MFG3_PWR_CON (0x1C001000+0xEC0) */ 2932 #define MFG3_PWR_RST_B_LSB BIT(0) /* 1b */ 2933 #define MFG3_PWR_ISO_LSB BIT(1) /* 1b */ 2934 #define MFG3_PWR_ON_LSB BIT(2) /* 1b */ 2935 #define MFG3_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2936 #define MFG3_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2937 #define MFG3_SRAM_PDN_LSB BIT(8) /* 1b */ 2938 #define SC_MFG3_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2939 #define MFG3_RTFF_SAVE_LSB BIT(24) /* 1b */ 2940 #define MFG3_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2941 #define MFG3_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2942 #define SC_MFG3_PWR_ACK_LSB BIT(30) /* 1b */ 2943 #define SC_MFG3_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2944 /* MFG4_PWR_CON (0x1C001000+0xEC4) */ 2945 #define MFG4_PWR_RST_B_LSB BIT(0) /* 1b */ 2946 #define MFG4_PWR_ISO_LSB BIT(1) /* 1b */ 2947 #define MFG4_PWR_ON_LSB BIT(2) /* 1b */ 2948 #define MFG4_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2949 #define MFG4_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2950 #define MFG4_SRAM_PDN_LSB BIT(8) /* 1b */ 2951 #define SC_MFG4_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2952 #define MFG4_RTFF_SAVE_LSB BIT(24) /* 1b */ 2953 #define MFG4_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2954 #define MFG4_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2955 #define SC_MFG4_PWR_ACK_LSB BIT(30) /* 1b */ 2956 #define SC_MFG4_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2957 /* MFG5_PWR_CON (0x1C001000+0xEC8) */ 2958 #define MFG5_PWR_RST_B_LSB BIT(0) /* 1b */ 2959 #define MFG5_PWR_ISO_LSB BIT(1) /* 1b */ 2960 #define MFG5_PWR_ON_LSB BIT(2) /* 1b */ 2961 #define MFG5_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2962 #define MFG5_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2963 #define MFG5_SRAM_PDN_LSB BIT(8) /* 1b */ 2964 #define SC_MFG5_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2965 #define MFG5_RTFF_SAVE_LSB BIT(24) /* 1b */ 2966 #define MFG5_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2967 #define MFG5_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2968 #define SC_MFG5_PWR_ACK_LSB BIT(30) /* 1b */ 2969 #define SC_MFG5_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2970 /* MFG6_PWR_CON (0x1C001000+0xECC) */ 2971 #define MFG6_PWR_RST_B_LSB BIT(0) /* 1b */ 2972 #define MFG6_PWR_ISO_LSB BIT(1) /* 1b */ 2973 #define MFG6_PWR_ON_LSB BIT(2) /* 1b */ 2974 #define MFG6_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2975 #define MFG6_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2976 #define MFG6_SRAM_PDN_LSB BIT(8) /* 1b */ 2977 #define SC_MFG6_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2978 #define MFG6_RTFF_SAVE_LSB BIT(24) /* 1b */ 2979 #define MFG6_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2980 #define MFG6_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2981 #define SC_MFG6_PWR_ACK_LSB BIT(30) /* 1b */ 2982 #define SC_MFG6_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2983 /* MFG7_PWR_CON (0x1C001000+0xED0) */ 2984 #define MFG7_PWR_RST_B_LSB BIT(0) /* 1b */ 2985 #define MFG7_PWR_ISO_LSB BIT(1) /* 1b */ 2986 #define MFG7_PWR_ON_LSB BIT(2) /* 1b */ 2987 #define MFG7_PWR_ON_2ND_LSB BIT(3) /* 1b */ 2988 #define MFG7_PWR_CLK_DIS_LSB BIT(4) /* 1b */ 2989 #define MFG7_SRAM_PDN_LSB BIT(8) /* 1b */ 2990 #define SC_MFG7_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 2991 #define MFG7_RTFF_SAVE_LSB BIT(24) /* 1b */ 2992 #define MFG7_RTFF_NRESTORE_LSB BIT(25) /* 1b */ 2993 #define MFG7_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ 2994 #define SC_MFG7_PWR_ACK_LSB BIT(30) /* 1b */ 2995 #define SC_MFG7_PWR_ACK_2ND_LSB BIT(31) /* 1b */ 2996 /* ADSP_HRE_SRAM_CON (0x1C001000+0xED4) */ 2997 #define ADSP_HRE_SRAM_CKISO_LSB BIT(0) /* 1b */ 2998 #define ADSP_HRE_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ 2999 #define ADSP_HRE_SRAM_SLEEP_B_LSB BIT(4) /* 1b */ 3000 #define ADSP_HRE_SRAM_PDN_LSB BIT(16) /* 1b */ 3001 /* CCU_SLEEP_SRAM_CON (0x1C001000+0xED8) */ 3002 #define CCU_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */ 3003 #define CCU_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ 3004 #define CCU_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 1b */ 3005 #define CCU_SLEEP_SRAM_PDN_LSB BIT(8) /* 1b */ 3006 #define SC_CCU_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 1b */ 3007 #define SC_CCU_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(17) /* 1b */ 3008 /* EFUSE_SRAM_CON (0x1C001000+0xEDC) */ 3009 #define EFUSE_SRAM_CKISO_LSB BIT(0) /* 1b */ 3010 #define EFUSE_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ 3011 #define EFUSE_SRAM_SLEEP_B_LSB BIT(4) /* 1b */ 3012 #define EFUSE_SRAM_PDN_LSB BIT(16) /* 1b */ 3013 /* EMI_HRE_SRAM_CON (0x1C001000+0xEE0) */ 3014 #define EMI_HRE_SRAM_CKISO_LSB BIT(0) /* 1b */ 3015 #define EMI_HRE_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ 3016 #define EMI_HRE_SRAM_SLEEP_B_LSB BIT(4) /* 8b */ 3017 #define EMI_HRE_SRAM_PDN_LSB BIT(16) /* 8b */ 3018 /* EMI_SLB_SRAM_CON (0x1C001000+0xEE4) */ 3019 #define EMI_SLB_SRAM_PDN_LSB BIT(0) /* 12b */ 3020 #define SC_EMI_SLB_SRAM_PDN_ACK_LSB BIT(16) /* 12b */ 3021 /* INFRA_HRE_SRAM_CON (0x1C001000+0xEE8) */ 3022 #define INFRA_HRE_SRAM_CKISO_LSB BIT(0) /* 1b */ 3023 #define INFRA_HRE_SRAM_ISOINT_B_LSB BIT(1) /* 2b */ 3024 #define INFRA_HRE_SRAM_SLEEP_B_LSB BIT(4) /* 6b */ 3025 #define INFRA_HRE_SRAM_PDN_LSB BIT(16) /* 6b */ 3026 /* INFRA_SLEEP_SRAM_CON (0x1C001000+0xEEC) */ 3027 #define INFRA_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */ 3028 #define INFRA_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 2b */ 3029 #define INFRA_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 2b */ 3030 #define INFRA_SLEEP_SRAM_PDN_LSB BIT(8) /* 2b */ 3031 #define SC_INFRA_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 2b */ 3032 #define SC_INFRA_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(18) /* 2b */ 3033 /* MM_HRE_SRAM_CON (0x1C001000+0xEF0) */ 3034 #define MM_HRE_SRAM_CKISO_LSB BIT(0) /* 1b */ 3035 #define MM_HRE_SRAM_ISOINT_B_LSB BIT(1) /* 3b */ 3036 #define MM_HRE_SRAM_SLEEP_B_LSB BIT(4) /* 3b */ 3037 #define MM_HRE_SRAM_PDN_LSB BIT(16) /* 3b */ 3038 /* NTH_EMI_SLB_SRAM_CON (0x1C001000+0xEF4) */ 3039 #define NTH_EMI_SLB_SRAM_SLEEP_B_LSB BIT(0) /* 16b */ 3040 #define NTH_EMI_SLB_SRAM_PDN_LSB BIT(16) /* 16b */ 3041 /* NTH_EMI_SLB_SRAM_ACK (0x1C001000+0xEF8) */ 3042 #define SC_NTH_EMI_SLB_SRAM_SLEEP_B_ACK_LSB BIT(0) /* 16b */ 3043 #define SC_NTH_EMI_SLB_SRAM_PDN_ACK_LSB BIT(16) /* 16b */ 3044 /* PERI_SLEEP_SRAM_CON (0x1C001000+0xEFC) */ 3045 #define PERI_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */ 3046 #define PERI_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ 3047 #define PERI_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 1b */ 3048 #define PERI_SLEEP_SRAM_PDN_LSB BIT(8) /* 1b */ 3049 #define SC_PERI_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 1b */ 3050 #define SC_PERI_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(17) /* 1b */ 3051 /* SPM_SRAM_CON (0x1C001000+0xF00) */ 3052 #define SPM_SRAM_CKISO_LSB BIT(0) /* 1b */ 3053 #define REG_SPM_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ 3054 #define REG_SPM_SRAM_SLEEP_B_LSB BIT(4) /* 4b */ 3055 #define SPM_SRAM_PDN_LSB BIT(16) /* 4b */ 3056 /* SSPM_SRAM_CON (0x1C001000+0xF04) */ 3057 #define SSPM_SRAM_CKISO_LSB BIT(0) /* 1b */ 3058 #define SSPM_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ 3059 #define SSPM_SRAM_SLEEP_B_LSB BIT(4) /* 1b */ 3060 #define SSPM_SRAM_PDN_LSB BIT(16) /* 1b */ 3061 /* SSR_SLEEP_SRAM_CON (0x1C001000+0xF08) */ 3062 #define SSR_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */ 3063 #define SSR_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ 3064 #define SSR_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 1b */ 3065 #define SSR_SLEEP_SRAM_PDN_LSB BIT(8) /* 1b */ 3066 #define SC_SSR_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 1b */ 3067 #define SC_SSR_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(17) /* 1b */ 3068 /* STH_EMI_SLB_SRAM_CON (0x1C001000+0xF0C) */ 3069 #define STH_EMI_SLB_SRAM_SLEEP_B_LSB BIT(0) /* 16b */ 3070 #define STH_EMI_SLB_SRAM_PDN_LSB BIT(16) /* 16b */ 3071 /* STH_EMI_SLB_SRAM_ACK (0x1C001000+0xF10) */ 3072 #define SC_STH_EMI_SLB_SRAM_SLEEP_B_ACK_LSB BIT(0) /* 16b */ 3073 #define SC_STH_EMI_SLB_SRAM_PDN_ACK_LSB BIT(16) /* 16b */ 3074 /* UFS_PDN_SRAM_CON (0x1C001000+0xF14) */ 3075 #define UFS_PDN_SRAM_PDN_LSB BIT(0) /* 1b */ 3076 #define SC_UFS_PDN_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ 3077 /* UFS_SLEEP_SRAM_CON (0x1C001000+0xF18) */ 3078 #define UFS_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */ 3079 #define UFS_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ 3080 #define UFS_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 1b */ 3081 #define UFS_SLEEP_SRAM_PDN_LSB BIT(8) /* 1b */ 3082 #define SC_UFS_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 1b */ 3083 #define SC_UFS_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(17) /* 1b */ 3084 /* UNIPRO_PDN_SRAM_CON (0x1C001000+0xF1C) */ 3085 #define UNIPRO_PDN_SRAM_PDN_LSB BIT(0) /* 1b */ 3086 #define SC_UNIPRO_PDN_SRAM_PDN_ACK_LSB BIT(8) /* 1b */ 3087 /* CPU_BUCK_ISO_CON (0x1C001000+0xF20) */ 3088 #define MCUSYS_VPROC_EXT_OFF_LSB BIT(0) /* 1b */ 3089 #define MP0_VPROC_EXT_OFF_LSB BIT(1) /* 1b */ 3090 #define MP0_VPROC_EXT_OFF_CPU0_LSB BIT(2) /* 1b */ 3091 #define MP0_VPROC_EXT_OFF_CPU1_LSB BIT(3) /* 1b */ 3092 #define MP0_VPROC_EXT_OFF_CPU2_LSB BIT(4) /* 1b */ 3093 #define MP0_VPROC_EXT_OFF_CPU3_LSB BIT(5) /* 1b */ 3094 #define MP0_VPROC_EXT_OFF_CPU4_LSB BIT(6) /* 1b */ 3095 #define MP0_VPROC_EXT_OFF_CPU5_LSB BIT(7) /* 1b */ 3096 #define MP0_VPROC_EXT_OFF_CPU6_LSB BIT(8) /* 1b */ 3097 #define MP0_VPROC_EXT_OFF_CPU7_LSB BIT(9) /* 1b */ 3098 #define MP0_VSRAM_EXT_OFF_LSB BIT(10) /* 1b */ 3099 /* MD_BUCK_ISO_CON (0x1C001000+0xF24) */ 3100 #define VMD_EXT_BUCK_ISO_LSB BIT(0) /* 1b */ 3101 #define AOC_VMD_SRAM_ISO_DIN_LSB BIT(1) /* 1b */ 3102 #define AOC_VMD_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */ 3103 #define AOC_VMD_ANA_ISO_LSB BIT(3) /* 1b */ 3104 #define VMODEM_EXT_BUCK_ISO_LSB BIT(4) /* 1b */ 3105 #define AOC_VMODEM_SRAM_ISO_DIN_LSB BIT(5) /* 1b */ 3106 #define AOC_VMODEM_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */ 3107 #define AOC_VMODEM_ANA_ISO_LSB BIT(7) /* 1b */ 3108 /* SOC_BUCK_ISO_CON (0x1C001000+0xF28) */ 3109 #define SCP_EXT_BUCK_ISO_LSB BIT(0) /* 1b */ 3110 #define AOC_SCP_SRAM_ISO_DIN_LSB BIT(1) /* 1b */ 3111 #define AOC_SCP_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */ 3112 #define AOC_SCP_ANA_ISO_LSB BIT(3) /* 1b */ 3113 #define VADSP_EXT_BUCK_ISO_LSB BIT(4) /* 1b */ 3114 #define AOC_VADSP_SRAM_ISO_DIN_LSB BIT(5) /* 1b */ 3115 #define AOC_VADSP_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */ 3116 #define AOC_VADSP_ANA_ISO_LSB BIT(7) /* 1b */ 3117 #define VAPU_EXT_BUCK_ISO_LSB BIT(8) /* 1b */ 3118 #define AOC_VAPU_SRAM_ISO_DIN_LSB BIT(9) /* 1b */ 3119 #define AOC_VAPU_SRAM_LATCH_ENB_LSB BIT(10) /* 1b */ 3120 #define AOC_VAPU_ANA_ISO_LSB BIT(11) /* 1b */ 3121 #define VDISP_EXT_BUCK_ISO_LSB BIT(12) /* 1b */ 3122 #define AOC_VDISP_SRAM_ISO_DIN_LSB BIT(13) /* 1b */ 3123 #define AOC_VDISP_SRAM_LATCH_ENB_LSB BIT(14) /* 1b */ 3124 #define AOC_VDISP_ANA_ISO_LSB BIT(15) /* 1b */ 3125 #define VGPU_EXT_BUCK_ISO_LSB BIT(16) /* 1b */ 3126 #define AOC_VGPU_SRAM_ISO_DIN_LSB BIT(17) /* 1b */ 3127 #define AOC_VGPU_SRAM_LATCH_ENB_LSB BIT(18) /* 1b */ 3128 #define AOC_VGPU_ANA_ISO_LSB BIT(19) /* 1b */ 3129 #define VGPUTOP_EXT_BUCK_ISO_LSB BIT(20) /* 1b */ 3130 #define AOC_VGPUTOP_SRAM_ISO_DIN_LSB BIT(21) /* 1b */ 3131 #define AOC_VGPUTOP_SRAM_LATCH_ENB_LSB BIT(22) /* 1b */ 3132 #define AOC_VGPUTOP_ANA_ISO_LSB BIT(23) /* 1b */ 3133 #define VMM_EXT_BUCK_ISO_LSB BIT(24) /* 1b */ 3134 #define AOC_VMM_SRAM_ISO_DIN_LSB BIT(25) /* 1b */ 3135 #define AOC_VMM_SRAM_LATCH_ENB_LSB BIT(26) /* 1b */ 3136 #define AOC_VMM_ANA_ISO_LSB BIT(27) /* 1b */ 3137 #define VBSSR_EXT_BUCK_ISO_LSB BIT(28) /* 1b */ 3138 #define AOC_VBSSR_SRAM_ISO_DIN_LSB BIT(29) /* 1b */ 3139 #define AOC_VBSSR_SRAM_LATCH_ENB_LSB BIT(30) /* 1b */ 3140 #define AOC_VBSSR_ANA_ISO_LSB BIT(31) /* 1b */ 3141 /* SOC_BUCK_ISO_CON_SET (0x1C001000+0xF2C) */ 3142 #define SOC_BUCK_ISO_CON_SET_SCP_EXT_BUCK_ISO_LSB BIT(0) /* 1b */ 3143 #define SOC_BUCK_ISO_CON_SET_AOC_SCP_SRAM_ISO_DIN_LSB BIT(1) /* 1b */ 3144 #define SOC_BUCK_ISO_CON_SET_AOC_SCP_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */ 3145 #define SOC_BUCK_ISO_CON_SET_AOC_SCP_ANA_ISO_LSB BIT(3) /* 1b */ 3146 #define SOC_BUCK_ISO_CON_SET_VADSP_EXT_BUCK_ISO_LSB BIT(4) /* 1b */ 3147 #define SOC_BUCK_ISO_CON_SET_AOC_VADSP_SRAM_ISO_DIN_LSB BIT(5) /* 1b */ 3148 #define SOC_BUCK_ISO_CON_SET_AOC_VADSP_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */ 3149 #define SOC_BUCK_ISO_CON_SET_AOC_VADSP_ANA_ISO_LSB BIT(7) /* 1b */ 3150 #define SOC_BUCK_ISO_CON_SET_VAPU_EXT_BUCK_ISO_LSB BIT(8) /* 1b */ 3151 #define SOC_BUCK_ISO_CON_SET_AOC_VAPU_SRAM_ISO_DIN_LSB BIT(9) /* 1b */ 3152 #define SOC_BUCK_ISO_CON_SET_AOC_VAPU_SRAM_LATCH_ENB_LSB BIT(10) /* 1b */ 3153 #define SOC_BUCK_ISO_CON_SET_AOC_VAPU_ANA_ISO_LSB BIT(11) /* 1b */ 3154 #define SOC_BUCK_ISO_CON_SET_VDISP_EXT_BUCK_ISO_LSB BIT(12) /* 1b */ 3155 #define SOC_BUCK_ISO_CON_SET_AOC_VDISP_SRAM_ISO_DIN_LSB BIT(13) /* 1b */ 3156 #define SOC_BUCK_ISO_CON_SET_AOC_VDISP_SRAM_LATCH_ENB_LSB BIT(14) /* 1b */ 3157 #define SOC_BUCK_ISO_CON_SET_AOC_VDISP_ANA_ISO_LSB BIT(15) /* 1b */ 3158 #define SOC_BUCK_ISO_CON_SET_VGPU_EXT_BUCK_ISO_LSB BIT(16) /* 1b */ 3159 #define SOC_BUCK_ISO_CON_SET_AOC_VGPU_SRAM_ISO_DIN_LSB BIT(17) /* 1b */ 3160 #define SOC_BUCK_ISO_CON_SET_AOC_VGPU_SRAM_LATCH_ENB_LSB BIT(18) /* 1b */ 3161 #define SOC_BUCK_ISO_CON_SET_AOC_VGPU_ANA_ISO_LSB BIT(19) /* 1b */ 3162 #define SOC_BUCK_ISO_CON_SET_VGPUTOP_EXT_BUCK_ISO_LSB BIT(20) /* 1b */ 3163 #define SOC_BUCK_ISO_CON_SET_AOC_VGPUTOP_SRAM_ISO_DIN_LSB BIT(21) /* 1b */ 3164 #define SOC_BUCK_ISO_CON_SET_AOC_VGPUTOP_SRAM_LATCH_ENB_LSB BIT(22) /* 1b */ 3165 #define SOC_BUCK_ISO_CON_SET_AOC_VGPUTOP_ANA_ISO_LSB BIT(23) /* 1b */ 3166 #define SOC_BUCK_ISO_CON_SET_VMM_EXT_BUCK_ISO_LSB BIT(24) /* 1b */ 3167 #define SOC_BUCK_ISO_CON_SET_AOC_VMM_SRAM_ISO_DIN_LSB BIT(25) /* 1b */ 3168 #define SOC_BUCK_ISO_CON_SET_AOC_VMM_SRAM_LATCH_ENB_LSB BIT(26) /* 1b */ 3169 #define SOC_BUCK_ISO_CON_SET_AOC_VMM_ANA_ISO_LSB BIT(27) /* 1b */ 3170 #define SOC_BUCK_ISO_CON_SET_VBSSR_EXT_BUCK_ISO_LSB BIT(28) /* 1b */ 3171 #define SOC_BUCK_ISO_CON_SET_AOC_VBSSR_SRAM_ISO_DIN_LSB BIT(29) /* 1b */ 3172 #define SOC_BUCK_ISO_CON_SET_AOC_VBSSR_SRAM_LATCH_ENB_LSB BIT(30) /* 1b */ 3173 #define SOC_BUCK_ISO_CON_SET_AOC_VBSSR_ANA_ISO_LSB BIT(31) /* 1b */ 3174 /* SOC_BUCK_ISO_CON_CLR (0x1C001000+0xF30) */ 3175 #define SOC_BUCK_ISO_CON_CLR_SCP_EXT_BUCK_ISO_LSB BIT(0) /* 1b */ 3176 #define SOC_BUCK_ISO_CON_CLR_AOC_SCP_SRAM_ISO_DIN_LSB BIT(1) /* 1b */ 3177 #define SOC_BUCK_ISO_CON_CLR_AOC_SCP_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */ 3178 #define SOC_BUCK_ISO_CON_CLR_AOC_SCP_ANA_ISO_LSB BIT(3) /* 1b */ 3179 #define SOC_BUCK_ISO_CON_CLR_VADSP_EXT_BUCK_ISO_LSB BIT(4) /* 1b */ 3180 #define SOC_BUCK_ISO_CON_CLR_AOC_VADSP_SRAM_ISO_DIN_LSB BIT(5) /* 1b */ 3181 #define SOC_BUCK_ISO_CON_CLR_AOC_VADSP_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */ 3182 #define SOC_BUCK_ISO_CON_CLR_AOC_VADSP_ANA_ISO_LSB BIT(7) /* 1b */ 3183 #define SOC_BUCK_ISO_CON_CLR_VAPU_EXT_BUCK_ISO_LSB BIT(8) /* 1b */ 3184 #define SOC_BUCK_ISO_CON_CLR_AOC_VAPU_SRAM_ISO_DIN_LSB BIT(9) /* 1b */ 3185 #define SOC_BUCK_ISO_CON_CLR_AOC_VAPU_SRAM_LATCH_ENB_LSB BIT(10) /* 1b */ 3186 #define SOC_BUCK_ISO_CON_CLR_AOC_VAPU_ANA_ISO_LSB BIT(11) /* 1b */ 3187 #define SOC_BUCK_ISO_CON_CLR_VDISP_EXT_BUCK_ISO_LSB BIT(12) /* 1b */ 3188 #define SOC_BUCK_ISO_CON_CLR_AOC_VDISP_SRAM_ISO_DIN_LSB BIT(13) /* 1b */ 3189 #define SOC_BUCK_ISO_CON_CLR_AOC_VDISP_SRAM_LATCH_ENB_LSB BIT(14) /* 1b */ 3190 #define SOC_BUCK_ISO_CON_CLR_AOC_VDISP_ANA_ISO_LSB BIT(15) /* 1b */ 3191 #define SOC_BUCK_ISO_CON_CLR_VGPU_EXT_BUCK_ISO_LSB BIT(16) /* 1b */ 3192 #define SOC_BUCK_ISO_CON_CLR_AOC_VGPU_SRAM_ISO_DIN_LSB BIT(17) /* 1b */ 3193 #define SOC_BUCK_ISO_CON_CLR_AOC_VGPU_SRAM_LATCH_ENB_LSB BIT(18) /* 1b */ 3194 #define SOC_BUCK_ISO_CON_CLR_AOC_VGPU_ANA_ISO_LSB BIT(19) /* 1b */ 3195 #define SOC_BUCK_ISO_CON_CLR_VGPUTOP_EXT_BUCK_ISO_LSB BIT(20) /* 1b */ 3196 #define SOC_BUCK_ISO_CON_CLR_AOC_VGPUTOP_SRAM_ISO_DIN_LSB BIT(21) /* 1b */ 3197 #define SOC_BUCK_ISO_CON_CLR_AOC_VGPUTOP_SRAM_LATCH_ENB_LSB BIT(22) /* 1b */ 3198 #define SOC_BUCK_ISO_CON_CLR_AOC_VGPUTOP_ANA_ISO_LSB BIT(23) /* 1b */ 3199 #define SOC_BUCK_ISO_CON_CLR_VMM_EXT_BUCK_ISO_LSB BIT(24) /* 1b */ 3200 #define SOC_BUCK_ISO_CON_CLR_AOC_VMM_SRAM_ISO_DIN_LSB BIT(25) /* 1b */ 3201 #define SOC_BUCK_ISO_CON_CLR_AOC_VMM_SRAM_LATCH_ENB_LSB BIT(26) /* 1b */ 3202 #define SOC_BUCK_ISO_CON_CLR_AOC_VMM_ANA_ISO_LSB BIT(27) /* 1b */ 3203 #define SOC_BUCK_ISO_CON_CLR_VBSSR_EXT_BUCK_ISO_LSB BIT(28) /* 1b */ 3204 #define SOC_BUCK_ISO_CON_CLR_AOC_VBSSR_SRAM_ISO_DIN_LSB BIT(29) /* 1b */ 3205 #define SOC_BUCK_ISO_CON_CLR_AOC_VBSSR_SRAM_LATCH_ENB_LSB BIT(30) /* 1b */ 3206 #define SOC_BUCK_ISO_CON_CLR_AOC_VBSSR_ANA_ISO_LSB BIT(31) /* 1b */ 3207 /* SOC_BUCK_ISO_CON_2 (0x1C001000+0xF34) */ 3208 #define VSTACK2_EXT_BUCK_ISO_LSB BIT(0) /* 1b */ 3209 #define AOC_VSTACK2_SRAM_ISO_DIN_LSB BIT(1) /* 1b */ 3210 #define AOC_VSTACK2_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */ 3211 #define AOC_VSTACK2_ANA_ISO_LSB BIT(3) /* 1b */ 3212 #define VSTACK_EXT_BUCK_ISO_LSB BIT(4) /* 1b */ 3213 #define AOC_VSTACK_SRAM_ISO_DIN_LSB BIT(5) /* 1b */ 3214 #define AOC_VSTACK_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */ 3215 #define AOC_VSTACK_ANA_ISO_LSB BIT(7) /* 1b */ 3216 /* SOC_BUCK_ISO_CON_2_SET (0x1C001000+0xF38) */ 3217 #define SOC_BUCK_ISO_CON_2_SET_VSTACK2_EXT_BUCK_ISO_LSB BIT(0) /* 1b */ 3218 #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK2_SRAM_ISO_DIN_LSB BIT(1) /* 1b */ 3219 #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK2_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */ 3220 #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK2_ANA_ISO_LSB BIT(3) /* 1b */ 3221 #define SOC_BUCK_ISO_CON_2_SET_VSTACK_EXT_BUCK_ISO_LSB BIT(4) /* 1b */ 3222 #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK_SRAM_ISO_DIN_LSB BIT(5) /* 1b */ 3223 #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */ 3224 #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK_ANA_ISO_LSB BIT(7) /* 1b */ 3225 /* SOC_BUCK_ISO_CON_2_CLR (0x1C001000+0xF3C) */ 3226 #define SOC_BUCK_ISO_CON_2_CLR_VSTACK2_EXT_BUCK_ISO_LSB BIT(0) /* 1b */ 3227 #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK2_SRAM_ISO_DIN_LSB BIT(1) /* 1b */ 3228 #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK2_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */ 3229 #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK2_ANA_ISO_LSB BIT(3) /* 1b */ 3230 #define SOC_BUCK_ISO_CON_2_CLR_VSTACK_EXT_BUCK_ISO_LSB BIT(4) /* 1b */ 3231 #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK_SRAM_ISO_DIN_LSB BIT(5) /* 1b */ 3232 #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */ 3233 #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK_ANA_ISO_LSB BIT(7) /* 1b */ 3234 /* PWR_STATUS (0x1C001000+0xF40) */ 3235 #define PWR_STATUS_LSB BIT(0) /* 32b */ 3236 /* PWR_STATUS_2ND (0x1C001000+0xF44) */ 3237 #define PWR_STATUS_2ND_LSB BIT(0) /* 32b */ 3238 /* PWR_STATUS_MSB (0x1C001000+0xF48) */ 3239 #define PWR_STATUS_MSB_LSB BIT(0) /* 32b */ 3240 /* PWR_STATUS_MSB_2ND (0x1C001000+0xF4C) */ 3241 #define PWR_STATUS_MSB_2ND_LSB BIT(0) /* 32b */ 3242 /* XPU_PWR_STATUS (0x1C001000+0xF50) */ 3243 #define XPU_PWR_STATUS_LSB BIT(0) /* 32b */ 3244 /* XPU_PWR_STATUS_2ND (0x1C001000+0xF54) */ 3245 #define XPU_PWR_STATUS_2ND_LSB BIT(0) /* 32b */ 3246 /* DFD_SOC_PWR_LATCH (0x1C001000+0xF58) */ 3247 #define DFD_SOC_PWR_LATCH_LSB BIT(0) /* 32b */ 3248 /* SUBSYS_PM_BYPASS (0x1C001000+0xF5C) */ 3249 #define PM_BYPASS_MODE_LSB BIT(0) /* 16b */ 3250 /* SPM_TWAM_CON (0x1C001000+0xF80) */ 3251 #define REG_TWAM_ENABLE_LSB BIT(0) /* 1b */ 3252 #define REG_TWAM_SPEED_MODE_EN_LSB BIT(1) /* 1b */ 3253 #define SPM_TWAM_EVENT_CLEAR_LSB BIT(2) /* 1b */ 3254 #define REG_TWAM_IRQ_MASK_LSB BIT(3) /* 1b */ 3255 #define REG_TWAM_MON_TYPE_0_LSB BIT(4) /* 2b */ 3256 #define REG_TWAM_MON_TYPE_1_LSB BIT(6) /* 2b */ 3257 #define REG_TWAM_MON_TYPE_2_LSB BIT(8) /* 2b */ 3258 #define REG_TWAM_MON_TYPE_3_LSB BIT(10) /* 2b */ 3259 #define REG_TWAM_IRQ_CLEAR_LSB BIT(16) /* 1b */ 3260 #define TWAM_IRQ_LSB BIT(24) /* 1b */ 3261 /* SPM_TWAM_WINDOW_LEN (0x1C001000+0xF84) */ 3262 #define REG_TWAM_WINDOW_LEN_LSB BIT(0) /* 32b */ 3263 /* SPM_TWAM_IDLE_SEL (0x1C001000+0xF88) */ 3264 #define REG_TWAM_SIG_SEL_0_LSB BIT(0) /* 7b */ 3265 #define REG_TWAM_SIG_SEL_1_LSB BIT(8) /* 7b */ 3266 #define REG_TWAM_SIG_SEL_2_LSB BIT(16) /* 7b */ 3267 #define REG_TWAM_SIG_SEL_3_LSB BIT(24) /* 7b */ 3268 /* SPM_TWAM_LAST_STA_0 (0x1C001000+0xF8C) */ 3269 #define TWAM_LAST_IDLE_CNT_0_LSB BIT(0) /* 32b */ 3270 /* SPM_TWAM_LAST_STA_1 (0x1C001000+0xF90) */ 3271 #define TWAM_LAST_IDLE_CNT_1_LSB BIT(0) /* 32b */ 3272 /* SPM_TWAM_LAST_STA_2 (0x1C001000+0xF94) */ 3273 #define TWAM_LAST_IDLE_CNT_2_LSB BIT(0) /* 32b */ 3274 /* SPM_TWAM_LAST_STA_3 (0x1C001000+0xF98) */ 3275 #define TWAM_LAST_IDLE_CNT_3_LSB BIT(0) /* 32b */ 3276 /* SPM_TWAM_CURR_STA_0 (0x1C001000+0xF9C) */ 3277 #define TWAM_CURRENT_IDLE_CNT_0_LSB BIT(0) /* 32b */ 3278 /* SPM_TWAM_CURR_STA_1 (0x1C001000+0xFA0) */ 3279 #define TWAM_CURRENT_IDLE_CNT_1_LSB BIT(0) /* 32b */ 3280 /* SPM_TWAM_CURR_STA_2 (0x1C001000+0xFA4) */ 3281 #define TWAM_CURRENT_IDLE_CNT_2_LSB BIT(0) /* 32b */ 3282 /* SPM_TWAM_CURR_STA_3 (0x1C001000+0xFA8) */ 3283 #define TWAM_CURRENT_IDLE_CNT_3_LSB BIT(0) /* 32b */ 3284 /* SPM_TWAM_TIMER_OUT (0x1C001000+0xFAC) */ 3285 #define TWAM_TIMER_LSB BIT(0) /* 32b */ 3286 3287 #define SPM_PROJECT_CODE 0xb16 3288 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) 3289 3290 #endif 3291