1 /* 2 * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <cdefs.h> 9 #include <errno.h> 10 #include <stdint.h> 11 12 #include <common/debug.h> 13 #include <common/desc_image_load.h> 14 #include <drivers/clk.h> 15 #include <drivers/mmc.h> 16 #include <drivers/st/regulator_fixed.h> 17 #include <drivers/st/stm32_rng.h> 18 #include <drivers/st/stm32mp2_ddr_helpers.h> 19 #include <drivers/st/stm32mp2_ram.h> 20 #include <drivers/st/stm32mp2_risaf.h> 21 #include <drivers/st/stm32mp_pmic2.h> 22 #include <drivers/st/stm32mp_risab_regs.h> 23 #include <lib/fconf/fconf.h> 24 #include <lib/fconf/fconf_dyn_cfg_getter.h> 25 #include <lib/mmio.h> 26 #include <lib/optee_utils.h> 27 #include <lib/xlat_tables/xlat_tables_v2.h> 28 #include <plat/common/platform.h> 29 30 #include <platform_def.h> 31 #include <stm32mp_common.h> 32 #include <stm32mp_dt.h> 33 34 #define BOOT_CTX_ADDR 0x0e000020UL 35 36 static void print_reset_reason(void) 37 { 38 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR); 39 const char *reason_str = "Unidentified"; 40 41 #if !STM32MP21 42 if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) { 43 INFO("CA35 processor core 1 reset\n"); 44 } 45 #endif /* !STM32MP21 */ 46 47 if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) { 48 if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) { 49 reason_str = "System exits from Standby for CA35"; 50 } else if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) { 51 reason_str = "D1 domain exits from DStandby"; 52 } else if ((rstsr & RCC_C1BOOTRSTSCLRR_VCPURSTF) != 0U) { 53 reason_str = "System reset from VCPU monitor"; 54 } else if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) { 55 reason_str = "CA35 reset by CM33 (C1RST)"; 56 } else { 57 reason_str = "Unidentified"; 58 } 59 } else { 60 if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) { 61 reason_str = "Power-on reset (por_rstn)"; 62 } else if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) { 63 reason_str = "Brownout reset (bor_rstn)"; 64 } else if ((rstsr & (RCC_C1BOOTRSTSSETR_SYSC2RSTF | 65 RCC_C1BOOTRSTSSETR_SYSC1RSTF)) != 0U) { 66 reason_str = "System reset (SYSRST)"; 67 } else if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) { 68 reason_str = "Clock failure on HSE"; 69 } else if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF) != 0U) { 70 reason_str = "IWDG system reset (iwdgX_out_rst)"; 71 } else if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) { 72 reason_str = "Pin reset from NRST"; 73 } else { 74 reason_str = "Unidentified"; 75 } 76 } 77 78 INFO("Reset reason: %s (0x%x)\n", reason_str, rstsr); 79 } 80 81 void bl2_el3_early_platform_setup(u_register_t arg0 __unused, 82 u_register_t arg1 __unused, 83 u_register_t arg2 __unused, 84 u_register_t arg3 __unused) 85 { 86 stm32mp_save_boot_ctx_address(BOOT_CTX_ADDR); 87 } 88 89 void bl2_platform_setup(void) 90 { 91 int ret; 92 93 ret = stm32mp2_ddr_probe(); 94 if (ret != 0) { 95 ERROR("DDR probe: error %d\n", ret); 96 panic(); 97 } 98 99 if (stm32mp2_risaf_init() < 0) { 100 panic(); 101 } 102 103 /* Map DDR for binary load, now with cacheable attribute */ 104 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 105 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); 106 if (ret < 0) { 107 ERROR("DDR mapping: error %d\n", ret); 108 panic(); 109 } 110 } 111 112 static void reset_backup_domain(void) 113 { 114 uintptr_t pwr_base = stm32mp_pwr_base(); 115 uintptr_t rcc_base = stm32mp_rcc_base(); 116 117 /* 118 * Disable the backup domain write protection. 119 * The protection is enable at each reset by hardware 120 * and must be disabled by software. 121 */ 122 #if STM32MP21 123 mmio_setbits_32(pwr_base + PWR_BDCR, PWR_BDCR_DBP); 124 125 while ((mmio_read_32(pwr_base + PWR_BDCR) & PWR_BDCR_DBP) == 0U) { 126 ; 127 } 128 #else /* STM32MP21 */ 129 mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P); 130 131 while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) { 132 ; 133 } 134 #endif /* STM32MP21 */ 135 136 /* Reset backup domain on cold boot cases */ 137 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) { 138 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 139 140 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) { 141 ; 142 } 143 144 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 145 } 146 } 147 148 void bl2_el3_plat_arch_setup(void) 149 { 150 const char *board_model; 151 boot_api_context_t *boot_context = 152 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 153 154 if (stm32_otp_probe() != 0U) { 155 EARLY_ERROR("OTP probe failed\n"); 156 panic(); 157 } 158 159 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 160 BL_CODE_END - BL_CODE_BASE, 161 MT_CODE | MT_SECURE); 162 163 configure_mmu(); 164 165 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 166 panic(); 167 } 168 169 reset_backup_domain(); 170 171 /* 172 * Initialize DDR sub-system clock. This needs to be done before enabling DDR PLL (PLL2), 173 * and so before stm32mp2_clk_init(). 174 */ 175 ddr_sub_system_clk_init(); 176 177 if (stm32mp2_clk_init() < 0) { 178 panic(); 179 } 180 181 #if STM32MP_DDR_FIP_IO_STORAGE 182 /* 183 * RISAB3 setup (dedicated for SRAM1) 184 * 185 * Allow secure read/writes data accesses to non-secure 186 * blocks or pages, all RISAB registers are writable. 187 * DDR firmwares are saved there before being loaded in DDRPHY memory. 188 */ 189 mmio_write_32(RISAB3_BASE + RISAB_CR, RISAB_CR_SRWIAD); 190 #endif 191 192 stm32_save_boot_info(boot_context); 193 194 if (stm32mp_uart_console_setup() != 0) { 195 goto skip_console_init; 196 } 197 198 stm32mp_print_cpuinfo(); 199 200 board_model = dt_get_board_model(); 201 if (board_model != NULL) { 202 NOTICE("Model: %s\n", board_model); 203 } 204 205 stm32mp_print_boardinfo(); 206 207 print_reset_reason(); 208 209 skip_console_init: 210 if (stm32_rng_init() != 0) { 211 panic(); 212 } 213 214 if (fixed_regulator_register() != 0) { 215 panic(); 216 } 217 218 if (dt_pmic_status() > 0) { 219 initialize_pmic(); 220 } 221 222 fconf_populate("TB_FW", STM32MP_DTB_BASE); 223 224 /* 225 * RISAB5 setup (dedicated for RETRAM) 226 * 227 * Allow secure read/writes data accesses to non-secure 228 * blocks or pages, all RISAB registers are writable. 229 * DDR retention registers are saved there and restored 230 * when exiting standby low power state. 231 */ 232 mmio_write_32(RISAB5_BASE + RISAB_CR, RISAB_CR_SRWIAD); 233 234 stm32mp_io_setup(); 235 } 236 237 static void prepare_encryption(void) 238 { 239 uint8_t mkey[RISAF_KEY_SIZE_IN_BYTES]; 240 241 /* Generate RISAF encryption key from RNG */ 242 if (stm32_rng_read(mkey, RISAF_KEY_SIZE_IN_BYTES) != 0) { 243 panic(); 244 } 245 246 if (stm32mp2_risaf_write_encryption_key(RISAF4_INST, mkey) != 0) { 247 panic(); 248 } 249 } 250 251 /******************************************************************************* 252 * This function can be used by the platforms to update/use image 253 * information for given `image_id`. 254 ******************************************************************************/ 255 int bl2_plat_handle_post_image_load(unsigned int image_id) 256 { 257 int err = 0; 258 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 259 bl_mem_params_node_t *pager_mem_params; 260 const struct dyn_cfg_dtb_info_t *config_info; 261 unsigned int i; 262 const unsigned int image_ids[] = { 263 BL31_IMAGE_ID, 264 SOC_FW_CONFIG_ID, 265 BL32_IMAGE_ID, 266 BL33_IMAGE_ID, 267 HW_CONFIG_ID, 268 }; 269 270 assert(bl_mem_params != NULL); 271 272 #if STM32MP_SDMMC || STM32MP_EMMC 273 /* 274 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 275 * We take the worst case which is 2 MMC blocks. 276 */ 277 if ((image_id != FW_CONFIG_ID) && 278 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 279 inv_dcache_range(bl_mem_params->image_info.image_base + 280 bl_mem_params->image_info.image_size, 281 2U * MMC_BLOCK_SIZE); 282 } 283 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 284 285 switch (image_id) { 286 case FW_CONFIG_ID: 287 if ((stm32mp_check_closed_device() == STM32MP_CHIP_SEC_CLOSED) || 288 stm32mp_is_auth_supported()) { 289 prepare_encryption(); 290 } 291 292 /* Set global DTB info for fixed fw_config information */ 293 set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE, 294 FW_CONFIG_ID); 295 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); 296 297 /* Iterate through all the fw config IDs */ 298 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { 299 bl_mem_params = get_bl_mem_params_node(image_ids[i]); 300 assert(bl_mem_params != NULL); 301 302 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); 303 if (config_info == NULL) { 304 continue; 305 } 306 307 bl_mem_params->image_info.image_base = config_info->config_addr; 308 bl_mem_params->image_info.image_max_size = config_info->config_max_size; 309 310 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; 311 312 switch (image_ids[i]) { 313 case BL31_IMAGE_ID: 314 bl_mem_params->ep_info.pc = config_info->config_addr; 315 break; 316 317 case BL32_IMAGE_ID: 318 bl_mem_params->ep_info.pc = config_info->config_addr; 319 320 /* In case of OPTEE, initialize address space with tos_fw addr */ 321 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 322 if (pager_mem_params != NULL) { 323 pager_mem_params->image_info.image_base = 324 config_info->config_addr; 325 pager_mem_params->image_info.image_max_size = 326 config_info->config_max_size; 327 } 328 break; 329 330 case BL33_IMAGE_ID: 331 bl_mem_params->ep_info.pc = config_info->config_addr; 332 break; 333 334 case HW_CONFIG_ID: 335 case SOC_FW_CONFIG_ID: 336 break; 337 338 default: 339 return -EINVAL; 340 } 341 } 342 343 /* 344 * After this step, the BL2 device tree area will be overwritten 345 * with BL31 binary, no other data should be read from BL2 DT. 346 */ 347 348 break; 349 350 case BL32_IMAGE_ID: 351 if ((bl_mem_params->image_info.image_base != 0UL) && 352 (optee_header_is_valid(bl_mem_params->image_info.image_base))) { 353 /* BL32 is OP-TEE header */ 354 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 355 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 356 assert(pager_mem_params != NULL); 357 358 err = parse_optee_header(&bl_mem_params->ep_info, 359 &pager_mem_params->image_info, 360 NULL); 361 if (err != 0) { 362 ERROR("OPTEE header parse error.\n"); 363 panic(); 364 } 365 366 /* Set optee boot info from parsed header data */ 367 bl_mem_params->ep_info.args.arg0 = 0U; /* Unused */ 368 bl_mem_params->ep_info.args.arg1 = 0U; /* Unused */ 369 bl_mem_params->ep_info.args.arg2 = 0U; /* No DT supported */ 370 } 371 break; 372 373 case BL33_IMAGE_ID: 374 #if PSA_FWU_SUPPORT 375 stm32_fwu_set_boot_idx(); 376 #endif /* PSA_FWU_SUPPORT */ 377 break; 378 379 default: 380 /* Do nothing in default case */ 381 break; 382 } 383 384 return err; 385 } 386