1 /* 2 * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <common/debug.h> 11 #include <common/runtime_svc.h> 12 #include <drivers/delay_timer.h> 13 #include <lib/mmio.h> 14 #include <tools_share/uuid.h> 15 16 #include "lib/utils/alignment_utils.h" 17 #include "socfpga_fcs.h" 18 #include "socfpga_mailbox.h" 19 #include "socfpga_plat_def.h" 20 #include "socfpga_reset_manager.h" 21 #include "socfpga_sip_svc.h" 22 #include "socfpga_system_manager.h" 23 24 /* Total buffer the driver can hold */ 25 #define FPGA_CONFIG_BUFFER_SIZE 4 26 27 static config_type request_type = NO_REQUEST; 28 static int current_block, current_buffer; 29 static int read_block, max_blocks; 30 static uint32_t send_id, rcv_id; 31 static uint32_t bytes_per_block, blocks_submitted; 32 static bool bridge_disable; 33 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 34 static uint32_t g_remapper_bypass; 35 #endif 36 37 /* RSU static variables */ 38 static uint32_t rsu_dcmf_ver[4] = {0}; 39 static uint16_t rsu_dcmf_stat[4] = {0}; 40 static uint32_t rsu_max_retry; 41 42 /* SiP Service UUID */ 43 DEFINE_SVC_UUID2(intl_svc_uid, 44 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 45 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 46 47 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 48 uint64_t x1, 49 uint64_t x2, 50 uint64_t x3, 51 uint64_t x4, 52 void *cookie, 53 void *handle, 54 uint64_t flags) 55 { 56 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 57 SMC_RET1(handle, SMC_UNK); 58 } 59 60 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 61 62 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 63 { 64 uint32_t args[3]; 65 66 while (max_blocks > 0 && buffer->size > buffer->size_written) { 67 args[0] = (1<<8); 68 args[1] = buffer->addr + buffer->size_written; 69 if (buffer->size - buffer->size_written <= bytes_per_block) { 70 args[2] = buffer->size - buffer->size_written; 71 current_buffer++; 72 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 73 } else { 74 args[2] = bytes_per_block; 75 } 76 77 buffer->size_written += args[2]; 78 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 79 3U, CMD_INDIRECT); 80 81 buffer->subblocks_sent++; 82 max_blocks--; 83 } 84 85 return !max_blocks; 86 } 87 88 static int intel_fpga_sdm_write_all(void) 89 { 90 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 91 if (intel_fpga_sdm_write_buffer( 92 &fpga_config_buffers[current_buffer])) { 93 break; 94 } 95 } 96 return 0; 97 } 98 99 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t *err_states) 100 { 101 uint32_t ret; 102 103 if (err_states == NULL) 104 return INTEL_SIP_SMC_STATUS_REJECTED; 105 106 switch (request_type) { 107 case RECONFIGURATION: 108 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 109 true, err_states); 110 break; 111 case BITSTREAM_AUTH: 112 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 113 false, err_states); 114 break; 115 default: 116 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 117 false, err_states); 118 break; 119 } 120 121 if (ret != 0U) { 122 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 123 return INTEL_SIP_SMC_STATUS_BUSY; 124 } else { 125 request_type = NO_REQUEST; 126 return INTEL_SIP_SMC_STATUS_ERROR; 127 } 128 } 129 130 if (bridge_disable != 0U) { 131 socfpga_bridges_enable(~0); /* Enable bridge */ 132 bridge_disable = false; 133 } 134 request_type = NO_REQUEST; 135 136 return INTEL_SIP_SMC_STATUS_OK; 137 } 138 139 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 140 { 141 int i; 142 143 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 144 if (fpga_config_buffers[i].block_number == current_block) { 145 fpga_config_buffers[i].subblocks_sent--; 146 if (fpga_config_buffers[i].subblocks_sent == 0 147 && fpga_config_buffers[i].size <= 148 fpga_config_buffers[i].size_written) { 149 fpga_config_buffers[i].write_requested = 0; 150 current_block++; 151 *buffer_addr_completed = 152 fpga_config_buffers[i].addr; 153 return 0; 154 } 155 } 156 } 157 158 return -1; 159 } 160 161 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 162 uint32_t *count, uint32_t *job_id) 163 { 164 uint32_t resp[5]; 165 unsigned int resp_len = ARRAY_SIZE(resp); 166 int status = INTEL_SIP_SMC_STATUS_OK; 167 int all_completed = 1; 168 *count = 0; 169 170 while (*count < 3) { 171 172 status = mailbox_read_response(job_id, 173 resp, &resp_len); 174 175 if (status < 0) { 176 break; 177 } 178 179 max_blocks++; 180 181 if (mark_last_buffer_xfer_completed( 182 &completed_addr[*count]) == 0) { 183 *count = *count + 1; 184 } else { 185 break; 186 } 187 } 188 189 if (*count <= 0) { 190 if (status != MBOX_NO_RESPONSE && 191 status != MBOX_TIMEOUT && resp_len != 0) { 192 mailbox_clear_response(); 193 request_type = NO_REQUEST; 194 return INTEL_SIP_SMC_STATUS_ERROR; 195 } 196 197 *count = 0; 198 } 199 200 intel_fpga_sdm_write_all(); 201 202 if (*count > 0) { 203 status = INTEL_SIP_SMC_STATUS_OK; 204 } else if (*count == 0) { 205 status = INTEL_SIP_SMC_STATUS_BUSY; 206 } 207 208 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 209 if (fpga_config_buffers[i].write_requested != 0) { 210 all_completed = 0; 211 break; 212 } 213 } 214 215 if (all_completed == 1) { 216 return INTEL_SIP_SMC_STATUS_OK; 217 } 218 219 return status; 220 } 221 222 static int intel_fpga_config_start(uint32_t flag) 223 { 224 uint32_t argument = 0x1; 225 uint32_t response[3]; 226 int status = 0; 227 unsigned int size = 0; 228 unsigned int resp_len = ARRAY_SIZE(response); 229 230 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 231 /* 232 * To trigger isolation 233 * FPGA configuration complete signal should be de-asserted 234 */ 235 INFO("SOCFPGA: Request SDM to trigger isolation\n"); 236 status = mailbox_send_fpga_config_comp(); 237 238 if (status < 0) { 239 INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n"); 240 } 241 #endif 242 243 request_type = RECONFIGURATION; 244 245 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 246 bridge_disable = true; 247 } 248 249 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 250 size = 1; 251 bridge_disable = false; 252 request_type = BITSTREAM_AUTH; 253 } 254 255 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 256 intel_smmu_hps_remapper_init(0U); 257 #endif 258 259 mailbox_clear_response(); 260 261 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 262 CMD_CASUAL, NULL, NULL); 263 264 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 265 CMD_CASUAL, response, &resp_len); 266 267 if (status < 0) { 268 bridge_disable = false; 269 request_type = NO_REQUEST; 270 return INTEL_SIP_SMC_STATUS_ERROR; 271 } 272 273 max_blocks = response[0]; 274 bytes_per_block = response[1]; 275 276 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 277 fpga_config_buffers[i].size = 0; 278 fpga_config_buffers[i].size_written = 0; 279 fpga_config_buffers[i].addr = 0; 280 fpga_config_buffers[i].write_requested = 0; 281 fpga_config_buffers[i].block_number = 0; 282 fpga_config_buffers[i].subblocks_sent = 0; 283 } 284 285 blocks_submitted = 0; 286 current_block = 0; 287 read_block = 0; 288 current_buffer = 0; 289 290 /* Disable bridge on full reconfiguration */ 291 if (bridge_disable) { 292 socfpga_bridges_disable(~0); 293 } 294 295 return INTEL_SIP_SMC_STATUS_OK; 296 } 297 298 static bool is_fpga_config_buffer_full(void) 299 { 300 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 301 if (!fpga_config_buffers[i].write_requested) { 302 return false; 303 } 304 } 305 return true; 306 } 307 308 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 309 { 310 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 311 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 312 313 if (!addr && !size) { 314 return true; 315 } 316 if (size > (UINT64_MAX - addr)) { 317 return false; 318 } 319 if (addr < BL31_LIMIT) { 320 return false; 321 } 322 if (dram_region_end > dram_max_sz) { 323 return false; 324 } 325 326 return true; 327 } 328 329 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 330 { 331 int i; 332 333 intel_fpga_sdm_write_all(); 334 335 if (!is_address_in_ddr_range(mem, size) || 336 is_fpga_config_buffer_full()) { 337 return INTEL_SIP_SMC_STATUS_REJECTED; 338 } 339 340 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 341 intel_smmu_hps_remapper_init(&mem); 342 #endif 343 344 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 345 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 346 347 if (!fpga_config_buffers[j].write_requested) { 348 fpga_config_buffers[j].addr = mem; 349 fpga_config_buffers[j].size = size; 350 fpga_config_buffers[j].size_written = 0; 351 fpga_config_buffers[j].write_requested = 1; 352 fpga_config_buffers[j].block_number = 353 blocks_submitted++; 354 fpga_config_buffers[j].subblocks_sent = 0; 355 break; 356 } 357 } 358 359 if (is_fpga_config_buffer_full()) { 360 return INTEL_SIP_SMC_STATUS_BUSY; 361 } 362 363 return INTEL_SIP_SMC_STATUS_OK; 364 } 365 366 static int is_out_of_sec_range(uint64_t reg_addr) 367 { 368 #if DEBUG 369 return 0; 370 #endif 371 372 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 373 switch (reg_addr) { 374 case(0xF8011100): /* ECCCTRL1 */ 375 case(0xF8011104): /* ECCCTRL2 */ 376 case(0xF8011110): /* ERRINTEN */ 377 case(0xF8011114): /* ERRINTENS */ 378 case(0xF8011118): /* ERRINTENR */ 379 case(0xF801111C): /* INTMODE */ 380 case(0xF8011120): /* INTSTAT */ 381 case(0xF8011124): /* DIAGINTTEST */ 382 case(0xF801112C): /* DERRADDRA */ 383 case(0xFA000000): /* SMMU SCR0 */ 384 case(0xFA000004): /* SMMU SCR1 */ 385 case(0xFA000400): /* SMMU NSCR0 */ 386 case(0xFA004000): /* SMMU SSD0_REG */ 387 case(0xFA000820): /* SMMU SMR8 */ 388 case(0xFA000c20): /* SMMU SCR8 */ 389 case(0xFA028000): /* SMMU CB8_SCTRL */ 390 case(0xFA001020): /* SMMU CBAR8 */ 391 case(0xFA028030): /* SMMU TCR_LPAE */ 392 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 393 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 394 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 395 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 396 case(0xFA028010): /* SMMU_CB8)TCR2 */ 397 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 398 case(0xFA001820): /* SMMU_CBA2R8 */ 399 case(0xFA000074): /* SMMU_STLBGSTATUS */ 400 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 401 case(0xFA000060): /* SMMU_STLBIALL */ 402 case(0xFA000070): /* SMMU_STLBGSYNC */ 403 case(0xFA028618): /* CB8_TLBALL */ 404 case(0xFA0287F0): /* CB8_TLBSYNC */ 405 case(0xFFD12028): /* SDMMCGRP_CTRL */ 406 case(0xFFD12044): /* EMAC0 */ 407 case(0xFFD12048): /* EMAC1 */ 408 case(0xFFD1204C): /* EMAC2 */ 409 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 410 case(0xFFD12094): /* ECC_INT_MASK_SET */ 411 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 412 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 413 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 414 case(0xFFD120C0): /* NOC_TIMEOUT */ 415 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 416 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 417 case(0xFFD120D0): /* NOC_IDLEACK */ 418 case(0xFFD120D4): /* NOC_IDLESTATUS */ 419 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 420 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 421 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 422 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 423 return 0; 424 #else 425 switch (reg_addr) { 426 427 case(0xF8011104): /* ECCCTRL2 */ 428 case(0xFFD12028): /* SDMMCGRP_CTRL */ 429 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 430 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 431 case(0xFFD120D0): /* NOC_IDLEACK */ 432 433 434 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 435 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 436 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 437 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 438 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 439 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 440 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 441 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 442 443 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */ 444 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 445 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 446 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 447 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 448 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 449 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 450 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 451 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 452 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 453 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 454 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 455 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 456 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 457 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 458 #endif 459 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 460 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 461 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 462 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 463 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 464 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 465 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 466 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 467 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 468 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 469 return 0; 470 471 default: 472 break; 473 } 474 475 return -1; 476 } 477 478 /* Secure register access */ 479 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 480 { 481 if (is_out_of_sec_range(reg_addr)) { 482 return INTEL_SIP_SMC_STATUS_ERROR; 483 } 484 485 *retval = mmio_read_32(reg_addr); 486 487 return INTEL_SIP_SMC_STATUS_OK; 488 } 489 490 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 491 uint32_t *retval) 492 { 493 if (is_out_of_sec_range(reg_addr)) { 494 return INTEL_SIP_SMC_STATUS_ERROR; 495 } 496 497 switch (reg_addr) { 498 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 499 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 500 mmio_write_16(reg_addr, val); 501 break; 502 default: 503 mmio_write_32(reg_addr, val); 504 break; 505 } 506 507 return intel_secure_reg_read(reg_addr, retval); 508 } 509 510 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 511 uint32_t val, uint32_t *retval) 512 { 513 if (!intel_secure_reg_read(reg_addr, retval)) { 514 *retval &= ~mask; 515 *retval |= val & mask; 516 return intel_secure_reg_write(reg_addr, *retval, retval); 517 } 518 519 return INTEL_SIP_SMC_STATUS_ERROR; 520 } 521 522 /* Intel Remote System Update (RSU) services */ 523 uint64_t intel_rsu_update_address; 524 525 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 526 { 527 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 528 return INTEL_SIP_SMC_RSU_ERROR; 529 } 530 531 return INTEL_SIP_SMC_STATUS_OK; 532 } 533 534 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf, 535 unsigned int respbuf_sz) 536 { 537 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) { 538 return INTEL_SIP_SMC_RSU_ERROR; 539 } 540 541 return INTEL_SIP_SMC_STATUS_OK; 542 } 543 544 uint32_t intel_rsu_update(uint64_t update_address) 545 { 546 if (update_address > SIZE_MAX) { 547 return INTEL_SIP_SMC_STATUS_REJECTED; 548 } 549 550 intel_rsu_update_address = update_address; 551 return INTEL_SIP_SMC_STATUS_OK; 552 } 553 554 static uint32_t intel_rsu_notify(uint32_t execution_stage) 555 { 556 if (mailbox_hps_stage_notify(execution_stage) < 0) { 557 return INTEL_SIP_SMC_RSU_ERROR; 558 } 559 560 return INTEL_SIP_SMC_STATUS_OK; 561 } 562 563 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 564 uint32_t *ret_stat) 565 { 566 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 567 return INTEL_SIP_SMC_RSU_ERROR; 568 } 569 570 *ret_stat = respbuf[8]; 571 return INTEL_SIP_SMC_STATUS_OK; 572 } 573 574 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 575 uint64_t dcmf_ver_3_2) 576 { 577 rsu_dcmf_ver[0] = dcmf_ver_1_0; 578 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 579 rsu_dcmf_ver[2] = dcmf_ver_3_2; 580 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 581 582 return INTEL_SIP_SMC_STATUS_OK; 583 } 584 585 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 586 { 587 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 588 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 589 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 590 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 591 592 return INTEL_SIP_SMC_STATUS_OK; 593 } 594 595 /* Intel HWMON services */ 596 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 597 { 598 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 599 return INTEL_SIP_SMC_STATUS_ERROR; 600 } 601 602 return INTEL_SIP_SMC_STATUS_OK; 603 } 604 605 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 606 { 607 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 608 return INTEL_SIP_SMC_STATUS_ERROR; 609 } 610 611 return INTEL_SIP_SMC_STATUS_OK; 612 } 613 614 /* Mailbox services */ 615 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 616 { 617 int status; 618 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 619 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 620 621 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 622 CMD_CASUAL, resp_data, &resp_len); 623 624 if (status < 0) { 625 return INTEL_SIP_SMC_STATUS_ERROR; 626 } 627 628 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 629 return INTEL_SIP_SMC_STATUS_ERROR; 630 } 631 632 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 633 634 return INTEL_SIP_SMC_STATUS_OK; 635 } 636 637 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 638 unsigned int len, uint32_t urgent, uint64_t response, 639 unsigned int resp_len, int *mbox_status, 640 unsigned int *len_in_resp) 641 { 642 *len_in_resp = 0; 643 *mbox_status = GENERIC_RESPONSE_ERROR; 644 645 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 646 return INTEL_SIP_SMC_STATUS_REJECTED; 647 } 648 649 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 650 (uint32_t *) response, &resp_len); 651 652 if (status < 0) { 653 *mbox_status = -status; 654 return INTEL_SIP_SMC_STATUS_ERROR; 655 } 656 657 *mbox_status = 0; 658 *len_in_resp = resp_len; 659 660 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 661 662 return INTEL_SIP_SMC_STATUS_OK; 663 } 664 665 static int intel_smc_get_usercode(uint32_t *user_code) 666 { 667 int status; 668 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 669 670 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 671 0U, CMD_CASUAL, user_code, &resp_len); 672 673 if (status < 0) { 674 return INTEL_SIP_SMC_STATUS_ERROR; 675 } 676 677 return INTEL_SIP_SMC_STATUS_OK; 678 } 679 680 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 681 uint32_t mode, uint32_t *job_id, 682 uint32_t *ret_size, uint32_t *mbox_error) 683 { 684 int status = 0; 685 uint32_t resp_len = size / MBOX_WORD_BYTE; 686 687 if (resp_len > MBOX_DATA_MAX_LEN) { 688 return INTEL_SIP_SMC_STATUS_REJECTED; 689 } 690 691 if (!is_address_in_ddr_range(addr, size)) { 692 return INTEL_SIP_SMC_STATUS_REJECTED; 693 } 694 695 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 696 status = mailbox_read_response_async(job_id, 697 NULL, (uint32_t *) addr, &resp_len, 0); 698 } else { 699 status = mailbox_read_response(job_id, 700 (uint32_t *) addr, &resp_len); 701 702 if (status == MBOX_NO_RESPONSE) { 703 status = MBOX_BUSY; 704 } 705 } 706 707 if (status == MBOX_NO_RESPONSE) { 708 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 709 } 710 711 if (status == MBOX_BUSY) { 712 return INTEL_SIP_SMC_STATUS_BUSY; 713 } 714 715 *ret_size = resp_len * MBOX_WORD_BYTE; 716 flush_dcache_range(addr, *ret_size); 717 718 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 719 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 720 *mbox_error = -status; 721 } else if (status != MBOX_RET_OK) { 722 *mbox_error = -status; 723 return INTEL_SIP_SMC_STATUS_ERROR; 724 } 725 726 return INTEL_SIP_SMC_STATUS_OK; 727 } 728 729 /* Miscellaneous HPS services */ 730 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 731 { 732 int status = 0; 733 734 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 735 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 736 status = socfpga_bridges_enable((uint32_t)mask); 737 } else { 738 status = socfpga_bridges_enable(~0); 739 } 740 } else { 741 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 742 status = socfpga_bridges_disable((uint32_t)mask); 743 } else { 744 status = socfpga_bridges_disable(~0); 745 } 746 } 747 748 if (status < 0) { 749 return INTEL_SIP_SMC_STATUS_ERROR; 750 } 751 752 return INTEL_SIP_SMC_STATUS_OK; 753 } 754 755 /* SDM SEU Error services */ 756 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 757 { 758 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 759 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 760 } 761 762 return INTEL_SIP_SMC_STATUS_OK; 763 } 764 765 /* SDM SAFE SEU Error inject services */ 766 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 767 { 768 if (mailbox_safe_inject_seu_err(command, len) < 0) { 769 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 770 } 771 772 return INTEL_SIP_SMC_STATUS_OK; 773 } 774 775 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 776 /* SMMU HPS Remapper */ 777 void intel_smmu_hps_remapper_init(uint64_t *mem) 778 { 779 /* Read out Bit 1 value */ 780 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 781 782 if ((remap == 0x00) && (g_remapper_bypass == 0x00)) { 783 /* Update DRAM Base address for SDM SMMU */ 784 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 785 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 786 *mem = *mem - DRAM_BASE; 787 } else { 788 *mem = *mem - DRAM_BASE; 789 } 790 } 791 792 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass) 793 { 794 /* Read out the JTAG-ID from boot scratch register */ 795 if (is_agilex5_A5F0() || is_agilex5_A5F4()) { 796 if (remapper_bypass == 0x01) { 797 g_remapper_bypass = remapper_bypass; 798 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0); 799 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0); 800 } 801 } 802 return INTEL_SIP_SMC_STATUS_OK; 803 } 804 805 static void intel_inject_io96b_ecc_err(const uint32_t *syndrome, const uint32_t command) 806 { 807 volatile uint64_t atf_ddr_buffer; 808 volatile uint64_t val; 809 810 mmio_write_32(IOSSM_CMD_PARAM, *syndrome); 811 mmio_write_32(IOSSM_CMD_TRIG_OP, command); 812 udelay(IOSSM_ECC_ERR_INJ_DELAY_USECS); 813 atf_ddr_buffer = 0xCAFEBABEFEEDFACE; /* Write data */ 814 memcpy_s((void *)&val, sizeof(val), 815 (void *)&atf_ddr_buffer, sizeof(atf_ddr_buffer)); 816 817 /* Clear response_ready BIT0 of status_register before sending next command. */ 818 mmio_clrbits_32(IOSSM_CMD_RESP_STATUS, IOSSM_CMD_STATUS_RESP_READY); 819 } 820 #endif 821 822 #if SIP_SVC_V3 823 uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 824 { 825 uint8_t ret_args_len = 0U; 826 sdm_response_t *resp = (sdm_response_t *)resp_desc; 827 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 828 829 (void)cmd; 830 /* Returns 3 SMC arguments for SMC_RET3 */ 831 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 832 ret_args[ret_args_len++] = resp->err_code; 833 834 return ret_args_len; 835 } 836 837 uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 838 { 839 uint8_t ret_args_len = 0U; 840 sdm_response_t *resp = (sdm_response_t *)resp_desc; 841 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 842 843 (void)cmd; 844 /* Returns 3 SMC arguments for SMC_RET3 */ 845 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 846 ret_args[ret_args_len++] = resp->err_code; 847 ret_args[ret_args_len++] = resp->resp_data[0]; 848 849 return ret_args_len; 850 } 851 852 uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 853 { 854 uint8_t ret_args_len = 0U; 855 sdm_response_t *resp = (sdm_response_t *)resp_desc; 856 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 857 858 (void)cmd; 859 INFO("MBOX: %s: mailbox_err 0%x, nbytes_ret %d\n", 860 __func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE); 861 862 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 863 ret_args[ret_args_len++] = resp->err_code; 864 ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE; 865 866 return ret_args_len; 867 } 868 869 uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 870 { 871 uint8_t ret_args_len = 0U; 872 sdm_response_t *resp = (sdm_response_t *)resp_desc; 873 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 874 875 (void)cmd; 876 INFO("MBOX: %s: mailbox_err 0%x, data[0] 0x%x, data[1] 0x%x\n", 877 __func__, resp->err_code, resp->resp_data[0], resp->resp_data[1]); 878 879 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 880 ret_args[ret_args_len++] = resp->err_code; 881 ret_args[ret_args_len++] = resp->resp_data[0]; 882 ret_args[ret_args_len++] = resp->resp_data[1]; 883 884 return ret_args_len; 885 } 886 887 uint8_t sip_smc_cmd_cb_rsu_status(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 888 { 889 uint8_t ret_args_len = 0U; 890 uint32_t retry_counter = ~0U; 891 uint32_t failure_source = 0U; 892 sdm_response_t *resp = (sdm_response_t *)resp_desc; 893 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 894 895 (void)cmd; 896 /* Get the failure source and current image retry counter value from the response. */ 897 failure_source = resp->resp_data[5] & RSU_VERSION_ACMF_MASK; 898 retry_counter = resp->resp_data[8]; 899 900 if ((retry_counter != ~0U) && (failure_source == 0U)) 901 resp->resp_data[5] |= RSU_VERSION_ACMF; 902 903 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 904 ret_args[ret_args_len++] = resp->err_code; 905 /* Current CMF */ 906 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[1], resp->resp_data[0]); 907 /* Last Failing CMF Address */ 908 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[3], resp->resp_data[2]); 909 /* Config State */ 910 ret_args[ret_args_len++] = resp->resp_data[4]; 911 /* Version */ 912 ret_args[ret_args_len++] = (GENMASK(16, 0) & resp->resp_data[5]); 913 /* Failure Source */ 914 ret_args[ret_args_len++] = ((GENMASK(32, 17) & resp->resp_data[5]) >> 16); 915 /* Error location */ 916 ret_args[ret_args_len++] = resp->resp_data[6]; 917 /* Error details */ 918 ret_args[ret_args_len++] = resp->resp_data[7]; 919 /* Current image retry counter */ 920 ret_args[ret_args_len++] = resp->resp_data[8]; 921 922 return ret_args_len; 923 } 924 925 uint8_t sip_smc_cmd_cb_rsu_spt(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 926 { 927 uint8_t ret_args_len = 0U; 928 sdm_response_t *resp = (sdm_response_t *)resp_desc; 929 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 930 931 (void)cmd; 932 933 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 934 ret_args[ret_args_len++] = resp->err_code; 935 /* Sub Partition Table (SPT) 0 address */ 936 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[0], resp->resp_data[1]); 937 /* Sub Partition Table (SPT) 1 address */ 938 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[2], resp->resp_data[3]); 939 940 return ret_args_len; 941 } 942 943 static uintptr_t smc_ret(void *handle, uint64_t *ret_args, uint32_t ret_args_len) 944 { 945 946 switch (ret_args_len) { 947 case SMC_RET_ARGS_ONE: 948 VERBOSE("SVC V3: %s: x0 0x%lx\n", __func__, ret_args[0]); 949 SMC_RET1(handle, ret_args[0]); 950 break; 951 952 case SMC_RET_ARGS_TWO: 953 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx\n", __func__, ret_args[0], ret_args[1]); 954 SMC_RET2(handle, ret_args[0], ret_args[1]); 955 break; 956 957 case SMC_RET_ARGS_THREE: 958 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx\n", 959 __func__, ret_args[0], ret_args[1], ret_args[2]); 960 SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]); 961 break; 962 963 case SMC_RET_ARGS_FOUR: 964 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx\n", 965 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 966 SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 967 break; 968 969 case SMC_RET_ARGS_FIVE: 970 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx\n", 971 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 972 SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 973 break; 974 975 case SMC_RET_ARGS_SIX: 976 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx x3 0x%lx, x4 0x%lx x5 0x%lx\n", 977 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 978 ret_args[5]); 979 SMC_RET6(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 980 ret_args[5]); 981 break; 982 983 case SMC_RET_ARGS_SEVEN: 984 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 985 "x6 0x%lx\n", 986 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 987 ret_args[5], ret_args[6]); 988 SMC_RET7(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 989 ret_args[5], ret_args[6]); 990 break; 991 992 case SMC_RET_ARGS_EIGHT: 993 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 994 "x6 0x%lx, x7 0x%lx\n", 995 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 996 ret_args[5], ret_args[6], ret_args[7]); 997 SMC_RET8(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 998 ret_args[5], ret_args[6], ret_args[7]); 999 break; 1000 1001 case SMC_RET_ARGS_NINE: 1002 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 1003 "x6 0x%lx, x7 0x%lx, x8 0x%lx\n", 1004 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1005 ret_args[5], ret_args[6], ret_args[7], ret_args[8]); 1006 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1007 ret_args[5], ret_args[6], ret_args[7], ret_args[8], 1008 0, 0, 0, 0, 0, 0, 0, 0, 0); 1009 break; 1010 1011 case SMC_RET_ARGS_TEN: 1012 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 1013 "x6 0x%lx, x7 0x%lx x8 0x%lx, x9 0x%lx, x10 0x%lx\n", 1014 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], 1015 ret_args[4], ret_args[5], ret_args[6], ret_args[7], ret_args[8], 1016 ret_args[9], ret_args[10]); 1017 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1018 ret_args[5], ret_args[6], ret_args[7], ret_args[8], ret_args[9], 1019 0, 0, 0, 0, 0, 0, 0, 0); 1020 break; 1021 1022 default: 1023 VERBOSE("SVC V3: %s ret_args_len is wrong, please check %d\n ", 1024 __func__, ret_args_len); 1025 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 1026 break; 1027 } 1028 } 1029 1030 static inline bool is_gen_mbox_cmd_allowed(uint32_t cmd) 1031 { 1032 /* Check if the command is allowed to be executed in generic mbox format */ 1033 bool is_cmd_allowed = false; 1034 1035 switch (cmd) { 1036 case MBOX_FCS_OPEN_CS_SESSION: 1037 case MBOX_FCS_CLOSE_CS_SESSION: 1038 case MBOX_FCS_IMPORT_CS_KEY: 1039 case MBOX_FCS_EXPORT_CS_KEY: 1040 case MBOX_FCS_REMOVE_CS_KEY: 1041 case MBOX_FCS_GET_CS_KEY_INFO: 1042 case MBOX_FCS_CREATE_CS_KEY: 1043 case MBOX_FCS_GET_DIGEST_REQ: 1044 case MBOX_FCS_MAC_VERIFY_REQ: 1045 case MBOX_FCS_ECDSA_HASH_SIGN_REQ: 1046 case MBOX_FCS_GET_PROVISION: 1047 case MBOX_FCS_CNTR_SET_PREAUTH: 1048 case MBOX_FCS_ENCRYPT_REQ: 1049 case MBOX_FCS_DECRYPT_REQ: 1050 case MBOX_FCS_RANDOM_GEN: 1051 case MBOX_FCS_AES_CRYPT_REQ: 1052 case MBOX_FCS_ECDSA_SHA2_DATA_SIGN_REQ: 1053 case MBOX_FCS_ECDSA_HASH_SIG_VERIFY: 1054 case MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY: 1055 case MBOX_FCS_ECDSA_GET_PUBKEY: 1056 case MBOX_FCS_ECDH_REQUEST: 1057 case MBOX_FCS_HKDF_REQUEST: 1058 /* These mailbox commands are not supported in the generic mailbox format. */ 1059 break; 1060 1061 default: 1062 is_cmd_allowed = true; 1063 break; 1064 } /* switch */ 1065 1066 return is_cmd_allowed; 1067 } 1068 1069 /* 1070 * This function is responsible for handling all SiP SVC V3 calls from the 1071 * non-secure world. 1072 */ 1073 static uintptr_t sip_smc_handler_v3(uint32_t smc_fid, 1074 u_register_t x1, 1075 u_register_t x2, 1076 u_register_t x3, 1077 u_register_t x4, 1078 void *cookie, 1079 void *handle, 1080 u_register_t flags) 1081 { 1082 int status = 0; 1083 uint32_t mbox_error = 0U; 1084 u_register_t x5, x6, x7, x8, x9, x10, x11; 1085 1086 /* Get all the SMC call arguments */ 1087 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1088 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1089 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1090 x8 = SMC_GET_GP(handle, CTX_GPREG_X8); 1091 x9 = SMC_GET_GP(handle, CTX_GPREG_X9); 1092 x10 = SMC_GET_GP(handle, CTX_GPREG_X10); 1093 x11 = SMC_GET_GP(handle, CTX_GPREG_X11); 1094 1095 INFO("MBOX: SVC_V3: x0 0x%x, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\n", 1096 smc_fid, x1, x2, x3, x4, x5); 1097 INFO("MBOX: SVC_V3: x6 0x%lx, x7 0x%lx, x8 0x%lx, x9 0x%lx, x10 0x%lx x11 0x%lx\n", 1098 x6, x7, x8, x9, x10, x11); 1099 1100 switch (smc_fid) { 1101 case ALTERA_SIP_SMC_ASYNC_RESP_POLL: 1102 { 1103 uint64_t ret_args[16] = {0}; 1104 uint32_t ret_args_len = 0; 1105 1106 status = mailbox_response_poll_v3(GET_CLIENT_ID(x1), 1107 GET_JOB_ID(x1), 1108 ret_args, 1109 &ret_args_len); 1110 /* Always reserve [0] index for command status. */ 1111 ret_args[0] = status; 1112 1113 /* Return SMC call based on the number of return arguments */ 1114 return smc_ret(handle, ret_args, ret_args_len); 1115 } 1116 1117 case ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR: 1118 { 1119 /* TBD: Here now we don't need these CID and JID?? */ 1120 uint8_t client_id = 0U; 1121 uint8_t job_id = 0U; 1122 uint64_t trans_id_bitmap[4] = {0U}; 1123 1124 status = mailbox_response_poll_on_intr_v3(&client_id, 1125 &job_id, 1126 trans_id_bitmap); 1127 1128 SMC_RET5(handle, status, trans_id_bitmap[0], trans_id_bitmap[1], 1129 trans_id_bitmap[2], trans_id_bitmap[3]); 1130 break; 1131 } 1132 1133 case ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY: 1134 { 1135 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1136 GET_JOB_ID(x1), 1137 MBOX_CMD_GET_DEVICEID, 1138 NULL, 1139 0U, 1140 MBOX_CMD_FLAG_CASUAL, 1141 sip_smc_ret_nbytes_cb, 1142 (uint32_t *)x2, 1143 2); 1144 1145 SMC_RET1(handle, status); 1146 } 1147 1148 case ALTERA_SIP_SMC_ASYNC_GET_IDCODE: 1149 { 1150 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1151 GET_JOB_ID(x1), 1152 MBOX_CMD_GET_IDCODE, 1153 NULL, 1154 0U, 1155 MBOX_CMD_FLAG_CASUAL, 1156 sip_smc_cmd_cb_ret3, 1157 NULL, 1158 0); 1159 1160 SMC_RET1(handle, status); 1161 } 1162 1163 case ALTERA_SIP_SMC_ASYNC_QSPI_OPEN: 1164 { 1165 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1166 GET_JOB_ID(x1), 1167 MBOX_CMD_QSPI_OPEN, 1168 NULL, 1169 0U, 1170 MBOX_CMD_FLAG_CASUAL, 1171 sip_smc_cmd_cb_ret2, 1172 NULL, 1173 0U); 1174 1175 SMC_RET1(handle, status); 1176 } 1177 1178 case ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE: 1179 { 1180 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1181 GET_JOB_ID(x1), 1182 MBOX_CMD_QSPI_CLOSE, 1183 NULL, 1184 0U, 1185 MBOX_CMD_FLAG_CASUAL, 1186 sip_smc_cmd_cb_ret2, 1187 NULL, 1188 0U); 1189 1190 SMC_RET1(handle, status); 1191 } 1192 1193 case ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS: 1194 { 1195 uint32_t cmd_data = 0U; 1196 uint32_t chip_sel = (uint32_t)x2; 1197 uint32_t comb_addr_mode = (uint32_t)x3; 1198 uint32_t ext_dec_mode = (uint32_t)x4; 1199 1200 cmd_data = (chip_sel << MBOX_QSPI_SET_CS_OFFSET) | 1201 (comb_addr_mode << MBOX_QSPI_SET_CS_CA_OFFSET) | 1202 (ext_dec_mode << MBOX_QSPI_SET_CS_MODE_OFFSET); 1203 1204 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1205 GET_JOB_ID(x1), 1206 MBOX_CMD_QSPI_SET_CS, 1207 &cmd_data, 1208 1U, 1209 MBOX_CMD_FLAG_CASUAL, 1210 sip_smc_cmd_cb_ret2, 1211 NULL, 1212 0U); 1213 1214 SMC_RET1(handle, status); 1215 } 1216 1217 case ALTERA_SIP_SMC_ASYNC_QSPI_ERASE: 1218 { 1219 uint32_t qspi_addr = (uint32_t)x2; 1220 uint32_t qspi_nwords = (uint32_t)x3; 1221 1222 /* QSPI address offset to start erase, must be 4K aligned */ 1223 if (MBOX_IS_4K_ALIGNED(qspi_addr)) { 1224 ERROR("MBOX: 0x%x: QSPI address not 4K aligned\n", 1225 smc_fid); 1226 status = INTEL_SIP_SMC_STATUS_REJECTED; 1227 SMC_RET1(handle, status); 1228 } 1229 1230 /* Number of words to erase, multiples of 0x400 or 4K */ 1231 if (qspi_nwords % MBOX_QSPI_ERASE_SIZE_GRAN) { 1232 ERROR("MBOX: 0x%x: Given words not in multiples of 4K\n", 1233 smc_fid); 1234 status = INTEL_SIP_SMC_STATUS_REJECTED; 1235 SMC_RET1(handle, status); 1236 } 1237 1238 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1239 1240 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1241 GET_JOB_ID(x1), 1242 MBOX_CMD_QSPI_ERASE, 1243 cmd_data, 1244 sizeof(cmd_data) / MBOX_WORD_BYTE, 1245 MBOX_CMD_FLAG_CASUAL, 1246 sip_smc_cmd_cb_ret2, 1247 NULL, 1248 0U); 1249 1250 SMC_RET1(handle, status); 1251 } 1252 1253 case ALTERA_SIP_SMC_ASYNC_QSPI_WRITE: 1254 { 1255 uint32_t *qspi_payload = (uint32_t *)x2; 1256 uint32_t qspi_total_nwords = (((uint32_t)x3) / MBOX_WORD_BYTE); 1257 uint32_t qspi_addr = qspi_payload[0]; 1258 uint32_t qspi_nwords = qspi_payload[1]; 1259 1260 if (!MBOX_IS_WORD_ALIGNED(qspi_addr)) { 1261 ERROR("MBOX: 0x%x: Given address is not WORD aligned\n", 1262 smc_fid); 1263 status = INTEL_SIP_SMC_STATUS_REJECTED; 1264 SMC_RET1(handle, status); 1265 } 1266 1267 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1268 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1269 smc_fid); 1270 status = INTEL_SIP_SMC_STATUS_REJECTED; 1271 SMC_RET1(handle, status); 1272 } 1273 1274 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1275 GET_JOB_ID(x1), 1276 MBOX_CMD_QSPI_WRITE, 1277 qspi_payload, 1278 qspi_total_nwords, 1279 MBOX_CMD_FLAG_CASUAL, 1280 sip_smc_cmd_cb_ret2, 1281 NULL, 1282 0U); 1283 1284 SMC_RET1(handle, status); 1285 } 1286 1287 case ALTERA_SIP_SMC_ASYNC_QSPI_READ: 1288 { 1289 uint32_t qspi_addr = (uint32_t)x2; 1290 uint32_t qspi_nwords = (((uint32_t)x4) / MBOX_WORD_BYTE); 1291 1292 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1293 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1294 smc_fid); 1295 status = INTEL_SIP_SMC_STATUS_REJECTED; 1296 SMC_RET1(handle, status); 1297 } 1298 1299 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1300 1301 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1302 GET_JOB_ID(x1), 1303 MBOX_CMD_QSPI_READ, 1304 cmd_data, 1305 sizeof(cmd_data) / MBOX_WORD_BYTE, 1306 MBOX_CMD_FLAG_CASUAL, 1307 sip_smc_ret_nbytes_cb, 1308 (uint32_t *)x3, 1309 2); 1310 1311 SMC_RET1(handle, status); 1312 } 1313 1314 case ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO: 1315 { 1316 uint32_t *dst_addr = (uint32_t *)x2; 1317 1318 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1319 GET_JOB_ID(x1), 1320 MBOX_CMD_QSPI_GET_DEV_INFO, 1321 NULL, 1322 0U, 1323 MBOX_CMD_FLAG_CASUAL, 1324 sip_smc_ret_nbytes_cb, 1325 (uint32_t *)dst_addr, 1326 2); 1327 1328 SMC_RET1(handle, status); 1329 } 1330 1331 case ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT: 1332 case ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP: 1333 { 1334 uint32_t channel = (uint32_t)x2; 1335 uint32_t mbox_cmd = ((smc_fid == ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT) ? 1336 MBOX_HWMON_READVOLT : MBOX_HWMON_READTEMP); 1337 1338 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1339 GET_JOB_ID(x1), 1340 mbox_cmd, 1341 &channel, 1342 1U, 1343 MBOX_CMD_FLAG_CASUAL, 1344 sip_smc_cmd_cb_ret3, 1345 NULL, 1346 0); 1347 1348 SMC_RET1(handle, status); 1349 } 1350 1351 case ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT: 1352 { 1353 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1354 GET_JOB_ID(x1), 1355 MBOX_GET_SUBPARTITION_TABLE, 1356 NULL, 1357 0, 1358 MBOX_CMD_FLAG_CASUAL, 1359 sip_smc_cmd_cb_rsu_spt, 1360 NULL, 1361 0); 1362 1363 SMC_RET1(handle, status); 1364 } 1365 1366 case ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS: 1367 { 1368 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1369 GET_JOB_ID(x1), 1370 MBOX_RSU_STATUS, 1371 NULL, 1372 0, 1373 MBOX_CMD_FLAG_CASUAL, 1374 sip_smc_cmd_cb_rsu_status, 1375 NULL, 1376 0); 1377 1378 SMC_RET1(handle, status); 1379 } 1380 1381 case ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY: 1382 { 1383 uint32_t notify_code = (uint32_t)x2; 1384 1385 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1386 GET_JOB_ID(x1), 1387 MBOX_HPS_STAGE_NOTIFY, 1388 ¬ify_code, 1389 1U, 1390 MBOX_CMD_FLAG_CASUAL, 1391 sip_smc_cmd_cb_ret2, 1392 NULL, 1393 0); 1394 1395 SMC_RET1(handle, status); 1396 } 1397 1398 case ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD: 1399 { 1400 /* Collect all the args passed in, and send the mailbox command. */ 1401 uint32_t mbox_cmd = (uint32_t)x2; 1402 uint32_t *cmd_payload_addr = NULL; 1403 uint32_t cmd_payload_len = (uint32_t)x4 / MBOX_WORD_BYTE; 1404 uint32_t *resp_payload_addr = NULL; 1405 uint32_t resp_payload_len = (uint32_t)x6 / MBOX_WORD_BYTE; 1406 1407 /* Filter the required commands here. */ 1408 if (!is_gen_mbox_cmd_allowed(mbox_cmd)) { 1409 status = INTEL_SIP_SMC_STATUS_REJECTED; 1410 SMC_RET1(handle, status); 1411 } 1412 1413 if ((cmd_payload_len > MBOX_GEN_CMD_MAX_WORDS) || 1414 (resp_payload_len > MBOX_GEN_CMD_MAX_WORDS)) { 1415 ERROR("MBOX: 0x%x: Command/Response payload length exceeds max limit\n", 1416 smc_fid); 1417 status = INTEL_SIP_SMC_STATUS_REJECTED; 1418 SMC_RET1(handle, status); 1419 } 1420 1421 /* Make sure we have valid command payload length and buffer */ 1422 if (cmd_payload_len != 0U) { 1423 cmd_payload_addr = (uint32_t *)x3; 1424 if (cmd_payload_addr == NULL) { 1425 ERROR("MBOX: 0x%x: Command payload address is NULL\n", 1426 smc_fid); 1427 status = INTEL_SIP_SMC_STATUS_REJECTED; 1428 SMC_RET1(handle, status); 1429 } 1430 } 1431 1432 /* Make sure we have valid response payload length and buffer */ 1433 if (resp_payload_len != 0U) { 1434 resp_payload_addr = (uint32_t *)x5; 1435 if (resp_payload_addr == NULL) { 1436 ERROR("MBOX: 0x%x: Response payload address is NULL\n", 1437 smc_fid); 1438 status = INTEL_SIP_SMC_STATUS_REJECTED; 1439 SMC_RET1(handle, status); 1440 } 1441 } 1442 1443 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1444 GET_JOB_ID(x1), 1445 mbox_cmd, 1446 (uint32_t *)cmd_payload_addr, 1447 cmd_payload_len, 1448 MBOX_CMD_FLAG_CASUAL, 1449 sip_smc_ret_nbytes_cb, 1450 (uint32_t *)resp_payload_addr, 1451 resp_payload_len); 1452 1453 SMC_RET1(handle, status); 1454 } 1455 1456 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT: 1457 { 1458 uint32_t session_id = (uint32_t)x2; 1459 uint32_t context_id = (uint32_t)x3; 1460 uint64_t ret_random_addr = (uint64_t)x4; 1461 uint32_t random_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1462 uint32_t crypto_header = 0U; 1463 1464 if ((random_len > (FCS_RANDOM_EXT_MAX_WORD_SIZE * MBOX_WORD_BYTE)) || 1465 (random_len == 0U) || 1466 (!is_size_4_bytes_aligned(random_len))) { 1467 ERROR("MBOX: 0x%x is rejected\n", smc_fid); 1468 status = INTEL_SIP_SMC_STATUS_REJECTED; 1469 SMC_RET1(handle, status); 1470 } 1471 1472 crypto_header = ((FCS_CS_FIELD_FLAG_INIT | FCS_CS_FIELD_FLAG_FINALIZE) << 1473 FCS_CS_FIELD_FLAG_OFFSET); 1474 fcs_rng_payload payload = {session_id, context_id, 1475 crypto_header, random_len}; 1476 1477 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1478 GET_JOB_ID(x1), 1479 MBOX_FCS_RANDOM_GEN, 1480 (uint32_t *)&payload, 1481 sizeof(payload) / MBOX_WORD_BYTE, 1482 MBOX_CMD_FLAG_CASUAL, 1483 sip_smc_ret_nbytes_cb, 1484 (uint32_t *)ret_random_addr, 1485 2); 1486 SMC_RET1(handle, status); 1487 } 1488 1489 case ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA: 1490 { 1491 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1492 GET_JOB_ID(x1), 1493 MBOX_FCS_GET_PROVISION, 1494 NULL, 1495 0U, 1496 MBOX_CMD_FLAG_CASUAL, 1497 sip_smc_ret_nbytes_cb, 1498 (uint32_t *)x2, 1499 2); 1500 SMC_RET1(handle, status); 1501 } 1502 1503 case ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH: 1504 { 1505 status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3, 1506 x4, &mbox_error); 1507 SMC_RET1(handle, status); 1508 } 1509 1510 case ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID: 1511 { 1512 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1513 GET_JOB_ID(x1), 1514 MBOX_CMD_GET_CHIPID, 1515 NULL, 1516 0U, 1517 MBOX_CMD_FLAG_CASUAL, 1518 sip_smc_get_chipid_cb, 1519 NULL, 1520 0); 1521 SMC_RET1(handle, status); 1522 } 1523 1524 case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT: 1525 { 1526 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3, 1527 (uint32_t *) &x4, &mbox_error); 1528 SMC_RET1(handle, status); 1529 } 1530 1531 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD: 1532 { 1533 status = intel_fcs_create_cert_on_reload(smc_fid, x1, 1534 x2, &mbox_error); 1535 SMC_RET1(handle, status); 1536 } 1537 1538 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT: 1539 { 1540 if (x4 == FCS_MODE_ENCRYPT) { 1541 status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3, 1542 x5, x6, x7, (uint32_t *) &x8, 1543 &mbox_error, x10, x11); 1544 } else if (x4 == FCS_MODE_DECRYPT) { 1545 status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3, 1546 x5, x6, x7, (uint32_t *) &x8, 1547 &mbox_error, x9, x10, x11); 1548 } else { 1549 ERROR("MBOX: 0x%x: Wrong crypto mode\n", smc_fid); 1550 status = INTEL_SIP_SMC_STATUS_REJECTED; 1551 } 1552 SMC_RET1(handle, status); 1553 } 1554 1555 case ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE: 1556 { 1557 status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error); 1558 SMC_RET1(handle, status); 1559 } 1560 1561 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION: 1562 { 1563 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1564 GET_JOB_ID(x1), 1565 MBOX_FCS_OPEN_CS_SESSION, 1566 NULL, 1567 0U, 1568 MBOX_CMD_FLAG_CASUAL, 1569 sip_smc_cmd_cb_ret3, 1570 NULL, 1571 0); 1572 SMC_RET1(handle, status); 1573 } 1574 1575 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION: 1576 { 1577 uint32_t session_id = (uint32_t)x2; 1578 1579 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1580 GET_JOB_ID(x1), 1581 MBOX_FCS_CLOSE_CS_SESSION, 1582 &session_id, 1583 1U, 1584 MBOX_CMD_FLAG_CASUAL, 1585 sip_smc_cmd_cb_ret2, 1586 NULL, 1587 0); 1588 SMC_RET1(handle, status); 1589 } 1590 1591 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY: 1592 { 1593 uint64_t key_addr = x2; 1594 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1595 1596 if ((key_len_words > FCS_CS_KEY_OBJ_MAX_WORD_SIZE) || 1597 (!is_address_in_ddr_range(key_addr, key_len_words * 4))) { 1598 ERROR("MBOX: 0x%x: Addr not in DDR range or key len exceeds\n", 1599 smc_fid); 1600 status = INTEL_SIP_SMC_STATUS_REJECTED; 1601 SMC_RET1(handle, status); 1602 } 1603 1604 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1605 GET_JOB_ID(x1), 1606 MBOX_FCS_IMPORT_CS_KEY, 1607 (uint32_t *)key_addr, 1608 key_len_words, 1609 MBOX_CMD_FLAG_CASUAL, 1610 sip_smc_cmd_cb_ret3, 1611 NULL, 1612 0); 1613 SMC_RET1(handle, status); 1614 } 1615 1616 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY: 1617 { 1618 uint64_t key_addr = x2; 1619 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1620 1621 if (!is_address_in_ddr_range(key_addr, key_len_words * 4)) { 1622 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1623 status = INTEL_SIP_SMC_STATUS_REJECTED; 1624 SMC_RET1(handle, status); 1625 } 1626 1627 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1628 GET_JOB_ID(x1), 1629 MBOX_FCS_CREATE_CS_KEY, 1630 (uint32_t *)key_addr, 1631 key_len_words, 1632 MBOX_CMD_FLAG_CASUAL, 1633 sip_smc_cmd_cb_ret3, 1634 NULL, 1635 0); 1636 SMC_RET1(handle, status); 1637 } 1638 1639 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY: 1640 { 1641 uint32_t session_id = (uint32_t)x2; 1642 uint32_t key_uid = (uint32_t)x3; 1643 uint64_t ret_key_addr = (uint64_t)x4; 1644 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1645 1646 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1647 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1648 status = INTEL_SIP_SMC_STATUS_REJECTED; 1649 SMC_RET1(handle, status); 1650 } 1651 1652 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1653 RESERVED_AS_ZERO, key_uid}; 1654 1655 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1656 GET_JOB_ID(x1), 1657 MBOX_FCS_EXPORT_CS_KEY, 1658 (uint32_t *)&payload, 1659 sizeof(payload) / MBOX_WORD_BYTE, 1660 MBOX_CMD_FLAG_CASUAL, 1661 sip_smc_ret_nbytes_cb, 1662 (uint32_t *)ret_key_addr, 1663 2); 1664 SMC_RET1(handle, status); 1665 } 1666 1667 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY: 1668 { 1669 uint32_t session_id = (uint32_t)x2; 1670 uint32_t key_uid = (uint32_t)x3; 1671 1672 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1673 RESERVED_AS_ZERO, key_uid}; 1674 1675 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1676 GET_JOB_ID(x1), 1677 MBOX_FCS_REMOVE_CS_KEY, 1678 (uint32_t *)&payload, 1679 sizeof(payload) / MBOX_WORD_BYTE, 1680 MBOX_CMD_FLAG_CASUAL, 1681 sip_smc_cmd_cb_ret3, 1682 NULL, 1683 0); 1684 SMC_RET1(handle, status); 1685 } 1686 1687 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO: 1688 { 1689 uint32_t session_id = (uint32_t)x2; 1690 uint32_t key_uid = (uint32_t)x3; 1691 uint64_t ret_key_addr = (uint64_t)x4; 1692 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1693 1694 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1695 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1696 status = INTEL_SIP_SMC_STATUS_REJECTED; 1697 SMC_RET1(handle, status); 1698 } 1699 1700 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1701 RESERVED_AS_ZERO, key_uid}; 1702 1703 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1704 GET_JOB_ID(x1), 1705 MBOX_FCS_GET_CS_KEY_INFO, 1706 (uint32_t *)&payload, 1707 sizeof(payload) / MBOX_WORD_BYTE, 1708 MBOX_CMD_FLAG_CASUAL, 1709 sip_smc_ret_nbytes_cb, 1710 (uint32_t *)ret_key_addr, 1711 2); 1712 SMC_RET1(handle, status); 1713 } 1714 1715 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT: 1716 { 1717 status = intel_fcs_aes_crypt_init(x2, x3, x4, x5, 1718 x6, &mbox_error); 1719 SMC_RET1(handle, status); 1720 } 1721 1722 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE: 1723 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE: 1724 { 1725 uint32_t job_id = 0U; 1726 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE) ? 1727 true : false; 1728 1729 status = intel_fcs_aes_crypt_update_finalize(smc_fid, x1, x2, 1730 x3, x4, x5, x6, x7, x8, is_final, 1731 &job_id, x9, x10); 1732 SMC_RET1(handle, status); 1733 } 1734 1735 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT: 1736 { 1737 status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6, 1738 &mbox_error); 1739 SMC_RET1(handle, status); 1740 } 1741 1742 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE: 1743 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE: 1744 { 1745 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE) ? 1746 true : false; 1747 1748 status = intel_fcs_get_digest_update_finalize(smc_fid, x1, x2, 1749 x3, x4, x5, x6, (uint32_t *) &x7, 1750 is_final, &mbox_error, x8); 1751 1752 SMC_RET1(handle, status); 1753 } 1754 1755 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT: 1756 { 1757 status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6, 1758 &mbox_error); 1759 SMC_RET1(handle, status); 1760 } 1761 1762 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE: 1763 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE: 1764 { 1765 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE) ? 1766 true : false; 1767 1768 status = intel_fcs_mac_verify_update_finalize(smc_fid, x1, x2, 1769 x3, x4, x5, x6, (uint32_t *) &x7, x8, 1770 is_final, &mbox_error, x9); 1771 SMC_RET1(handle, status); 1772 } 1773 1774 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT: 1775 { 1776 status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6, 1777 &mbox_error); 1778 SMC_RET1(handle, status); 1779 } 1780 1781 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1782 { 1783 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3, 1784 x4, x5, x6, (uint32_t *) &x7, 1785 &mbox_error); 1786 SMC_RET1(handle, status); 1787 } 1788 1789 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1790 { 1791 status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6, 1792 &mbox_error); 1793 SMC_RET1(handle, status); 1794 } 1795 1796 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1797 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1798 { 1799 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE) 1800 ? true : false; 1801 1802 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 1803 x1, x2, x3, x4, x5, x6, (uint32_t *) &x7, 1804 is_final, &mbox_error, x8); 1805 SMC_RET1(handle, status); 1806 } 1807 1808 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1809 { 1810 status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5, 1811 x6, &mbox_error); 1812 SMC_RET1(handle, status); 1813 } 1814 1815 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1816 { 1817 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, x1, 1818 x2, x3, x4, x5, x6, (uint32_t *) &x7, 1819 &mbox_error); 1820 SMC_RET1(handle, status); 1821 } 1822 1823 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1824 { 1825 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4, 1826 x5, x6, &mbox_error); 1827 SMC_RET1(handle, status); 1828 } 1829 1830 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1831 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1832 { 1833 bool is_final = (smc_fid == 1834 ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE) ? 1835 true : false; 1836 1837 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1838 smc_fid, x1, x2, x3, x4, x5, x6, 1839 (uint32_t *) &x7, x8, is_final, 1840 &mbox_error, x9); 1841 SMC_RET1(handle, status); 1842 } 1843 1844 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT: 1845 { 1846 status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6, 1847 &mbox_error); 1848 SMC_RET1(handle, status); 1849 } 1850 1851 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1852 { 1853 status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3, 1854 x4, (uint32_t *) &x5, &mbox_error); 1855 SMC_RET1(handle, status); 1856 } 1857 1858 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT: 1859 { 1860 status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6, 1861 &mbox_error); 1862 SMC_RET1(handle, status); 1863 } 1864 1865 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE: 1866 { 1867 uint32_t dest_size = (uint32_t)x7; 1868 1869 NOTICE("MBOX: %s, %d: x7 0x%x, dest_size 0x%x\n", 1870 __func__, __LINE__, (uint32_t)x7, dest_size); 1871 1872 status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3, 1873 x4, x5, x6, (uint32_t *) &dest_size, 1874 &mbox_error); 1875 SMC_RET1(handle, status); 1876 } 1877 1878 case ALTERA_SIP_SMC_ASYNC_MCTP_MSG: 1879 { 1880 uint32_t *src_addr = (uint32_t *)x2; 1881 uint32_t src_size = (uint32_t)x3; 1882 uint32_t *dst_addr = (uint32_t *)x4; 1883 1884 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1885 GET_JOB_ID(x1), 1886 MBOX_CMD_MCTP_MSG, 1887 src_addr, 1888 src_size / MBOX_WORD_BYTE, 1889 MBOX_CMD_FLAG_CASUAL, 1890 sip_smc_ret_nbytes_cb, 1891 dst_addr, 1892 2); 1893 1894 SMC_RET1(handle, status); 1895 } 1896 1897 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST: 1898 { 1899 status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6, 1900 x7); 1901 SMC_RET1(handle, status); 1902 } 1903 1904 default: 1905 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1906 cookie, handle, flags); 1907 } /* switch (smc_fid) */ 1908 } 1909 #endif 1910 1911 /* 1912 * This function is responsible for handling all SiP calls from the NS world 1913 */ 1914 1915 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 1916 u_register_t x1, 1917 u_register_t x2, 1918 u_register_t x3, 1919 u_register_t x4, 1920 void *cookie, 1921 void *handle, 1922 u_register_t flags) 1923 { 1924 uint32_t retval = 0, completed_addr[3]; 1925 uint32_t retval2 = 0; 1926 uint32_t mbox_error = 0; 1927 uint32_t err_states = 0; 1928 uint64_t retval64, rsu_respbuf[9]; 1929 uint32_t seu_respbuf[3]; 1930 int status = INTEL_SIP_SMC_STATUS_OK; 1931 int mbox_status; 1932 unsigned int len_in_resp = 0; 1933 u_register_t x5, x6, x7; 1934 1935 switch (smc_fid) { 1936 case SIP_SVC_UID: 1937 /* Return UID to the caller */ 1938 SMC_UUID_RET(handle, intl_svc_uid); 1939 1940 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 1941 status = intel_mailbox_fpga_config_isdone(&err_states); 1942 SMC_RET4(handle, status, err_states, 0, 0); 1943 1944 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 1945 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1946 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 1947 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 1948 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 1949 1950 case INTEL_SIP_SMC_FPGA_CONFIG_START: 1951 status = intel_fpga_config_start(x1); 1952 SMC_RET4(handle, status, 0, 0, 0); 1953 1954 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 1955 status = intel_fpga_config_write(x1, x2); 1956 SMC_RET4(handle, status, 0, 0, 0); 1957 1958 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 1959 status = intel_fpga_config_completed_write(completed_addr, 1960 &retval, &rcv_id); 1961 switch (retval) { 1962 case 1: 1963 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1964 completed_addr[0], 0, 0); 1965 1966 case 2: 1967 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1968 completed_addr[0], 1969 completed_addr[1], 0); 1970 1971 case 3: 1972 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1973 completed_addr[0], 1974 completed_addr[1], 1975 completed_addr[2]); 1976 1977 case 0: 1978 SMC_RET4(handle, status, 0, 0, 0); 1979 1980 default: 1981 mailbox_clear_response(); 1982 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 1983 } 1984 1985 case INTEL_SIP_SMC_REG_READ: 1986 status = intel_secure_reg_read(x1, &retval); 1987 SMC_RET3(handle, status, retval, x1); 1988 1989 case INTEL_SIP_SMC_REG_WRITE: 1990 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 1991 SMC_RET3(handle, status, retval, x1); 1992 1993 case INTEL_SIP_SMC_REG_UPDATE: 1994 status = intel_secure_reg_update(x1, (uint32_t)x2, 1995 (uint32_t)x3, &retval); 1996 SMC_RET3(handle, status, retval, x1); 1997 1998 case INTEL_SIP_SMC_RSU_STATUS: 1999 status = intel_rsu_status(rsu_respbuf, 2000 ARRAY_SIZE(rsu_respbuf)); 2001 if (status) { 2002 SMC_RET1(handle, status); 2003 } else { 2004 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 2005 rsu_respbuf[2], rsu_respbuf[3]); 2006 } 2007 2008 case INTEL_SIP_SMC_RSU_UPDATE: 2009 status = intel_rsu_update(x1); 2010 SMC_RET1(handle, status); 2011 2012 case INTEL_SIP_SMC_RSU_NOTIFY: 2013 status = intel_rsu_notify(x1); 2014 SMC_RET1(handle, status); 2015 2016 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 2017 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 2018 ARRAY_SIZE(rsu_respbuf), &retval); 2019 if (status) { 2020 SMC_RET1(handle, status); 2021 } else { 2022 SMC_RET2(handle, status, retval); 2023 } 2024 2025 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 2026 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2027 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 2028 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 2029 2030 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 2031 status = intel_rsu_copy_dcmf_version(x1, x2); 2032 SMC_RET1(handle, status); 2033 2034 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO: 2035 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf, 2036 ARRAY_SIZE(rsu_respbuf)); 2037 if (status) { 2038 SMC_RET1(handle, status); 2039 } else { 2040 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1], 2041 rsu_respbuf[2], rsu_respbuf[3]); 2042 } 2043 2044 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 2045 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 2046 ((uint64_t)rsu_dcmf_stat[3] << 48) | 2047 ((uint64_t)rsu_dcmf_stat[2] << 32) | 2048 ((uint64_t)rsu_dcmf_stat[1] << 16) | 2049 rsu_dcmf_stat[0]); 2050 2051 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 2052 status = intel_rsu_copy_dcmf_status(x1); 2053 SMC_RET1(handle, status); 2054 2055 case INTEL_SIP_SMC_RSU_MAX_RETRY: 2056 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 2057 2058 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 2059 rsu_max_retry = x1; 2060 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 2061 2062 case INTEL_SIP_SMC_ECC_DBE: 2063 status = intel_ecc_dbe_notification(x1); 2064 SMC_RET1(handle, status); 2065 2066 case INTEL_SIP_SMC_SERVICE_COMPLETED: 2067 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 2068 &len_in_resp, &mbox_error); 2069 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 2070 2071 case INTEL_SIP_SMC_FIRMWARE_VERSION: 2072 status = intel_smc_fw_version(&retval); 2073 SMC_RET2(handle, status, retval); 2074 2075 case INTEL_SIP_SMC_MBOX_SEND_CMD: 2076 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2077 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2078 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 2079 &mbox_status, &len_in_resp); 2080 SMC_RET3(handle, status, mbox_status, len_in_resp); 2081 2082 case INTEL_SIP_SMC_GET_USERCODE: 2083 status = intel_smc_get_usercode(&retval); 2084 SMC_RET2(handle, status, retval); 2085 2086 case INTEL_SIP_SMC_FCS_CRYPTION: 2087 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2088 2089 if (x1 == FCS_MODE_DECRYPT) { 2090 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 2091 } else if (x1 == FCS_MODE_ENCRYPT) { 2092 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 2093 } else { 2094 status = INTEL_SIP_SMC_STATUS_REJECTED; 2095 } 2096 2097 SMC_RET3(handle, status, x4, x5); 2098 2099 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 2100 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2101 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2102 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2103 2104 if (x3 == FCS_MODE_DECRYPT) { 2105 status = intel_fcs_decryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 2106 (uint32_t *) &x7, &mbox_error, 0, 0, 0); 2107 } else if (x3 == FCS_MODE_ENCRYPT) { 2108 status = intel_fcs_encryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 2109 (uint32_t *) &x7, &mbox_error, 0, 0); 2110 } else { 2111 status = INTEL_SIP_SMC_STATUS_REJECTED; 2112 } 2113 2114 SMC_RET4(handle, status, mbox_error, x6, x7); 2115 2116 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 2117 status = intel_fcs_random_number_gen(x1, &retval64, 2118 &mbox_error); 2119 SMC_RET4(handle, status, mbox_error, x1, retval64); 2120 2121 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 2122 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 2123 &send_id); 2124 SMC_RET1(handle, status); 2125 2126 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 2127 status = intel_fcs_send_cert(smc_fid, 0, x1, x2, &send_id); 2128 SMC_RET1(handle, status); 2129 2130 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 2131 status = intel_fcs_get_provision_data(&send_id); 2132 SMC_RET1(handle, status); 2133 2134 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 2135 status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3, 2136 &mbox_error); 2137 SMC_RET2(handle, status, mbox_error); 2138 2139 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 2140 status = intel_hps_set_bridges(x1, x2); 2141 SMC_RET1(handle, status); 2142 2143 case INTEL_SIP_SMC_HWMON_READTEMP: 2144 status = intel_hwmon_readtemp(x1, &retval); 2145 SMC_RET2(handle, status, retval); 2146 2147 case INTEL_SIP_SMC_HWMON_READVOLT: 2148 status = intel_hwmon_readvolt(x1, &retval); 2149 SMC_RET2(handle, status, retval); 2150 2151 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 2152 status = intel_fcs_sigma_teardown(x1, &mbox_error); 2153 SMC_RET2(handle, status, mbox_error); 2154 2155 case INTEL_SIP_SMC_FCS_CHIP_ID: 2156 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 2157 SMC_RET4(handle, status, mbox_error, retval, retval2); 2158 2159 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 2160 status = intel_fcs_attestation_subkey(x1, x2, x3, 2161 (uint32_t *) &x4, &mbox_error); 2162 SMC_RET4(handle, status, mbox_error, x3, x4); 2163 2164 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 2165 status = intel_fcs_get_measurement(x1, x2, x3, 2166 (uint32_t *) &x4, &mbox_error); 2167 SMC_RET4(handle, status, mbox_error, x3, x4); 2168 2169 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 2170 status = intel_fcs_get_attestation_cert(smc_fid, 0, x1, x2, 2171 (uint32_t *) &x3, &mbox_error); 2172 SMC_RET4(handle, status, mbox_error, x2, x3); 2173 2174 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 2175 status = intel_fcs_create_cert_on_reload(smc_fid, 0, x1, &mbox_error); 2176 SMC_RET2(handle, status, mbox_error); 2177 2178 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 2179 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 2180 SMC_RET3(handle, status, mbox_error, retval); 2181 2182 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 2183 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 2184 SMC_RET2(handle, status, mbox_error); 2185 2186 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 2187 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 2188 SMC_RET1(handle, status); 2189 2190 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 2191 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 2192 (uint32_t *) &x4, &mbox_error); 2193 SMC_RET4(handle, status, mbox_error, x3, x4); 2194 2195 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 2196 status = intel_fcs_remove_crypto_service_key(x1, x2, 2197 &mbox_error); 2198 SMC_RET2(handle, status, mbox_error); 2199 2200 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 2201 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 2202 (uint32_t *) &x4, &mbox_error); 2203 SMC_RET4(handle, status, mbox_error, x3, x4); 2204 2205 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 2206 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2207 status = intel_fcs_get_digest_init(x1, x2, x3, 2208 x4, x5, &mbox_error); 2209 SMC_RET2(handle, status, mbox_error); 2210 2211 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 2212 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2213 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2214 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2215 x3, x4, x5, (uint32_t *) &x6, false, 2216 &mbox_error, 0); 2217 SMC_RET4(handle, status, mbox_error, x5, x6); 2218 2219 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 2220 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2221 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2222 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2223 x3, x4, x5, (uint32_t *) &x6, true, 2224 &mbox_error, 0); 2225 SMC_RET4(handle, status, mbox_error, x5, x6); 2226 2227 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 2228 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2229 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2230 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2231 x4, x5, (uint32_t *) &x6, false, 2232 &mbox_error, &send_id); 2233 SMC_RET4(handle, status, mbox_error, x5, x6); 2234 2235 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 2236 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2237 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2238 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2239 x4, x5, (uint32_t *) &x6, true, 2240 &mbox_error, &send_id); 2241 SMC_RET4(handle, status, mbox_error, x5, x6); 2242 2243 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 2244 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2245 status = intel_fcs_mac_verify_init(x1, x2, x3, 2246 x4, x5, &mbox_error); 2247 SMC_RET2(handle, status, mbox_error); 2248 2249 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 2250 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2251 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2252 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2253 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2254 x3, x4, x5, (uint32_t *) &x6, x7, false, 2255 &mbox_error, 0); 2256 SMC_RET4(handle, status, mbox_error, x5, x6); 2257 2258 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 2259 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2260 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2261 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2262 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2263 x3, x4, x5, (uint32_t *) &x6, x7, true, 2264 &mbox_error, 0); 2265 SMC_RET4(handle, status, mbox_error, x5, x6); 2266 2267 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 2268 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2269 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2270 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2271 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2272 x4, x5, (uint32_t *) &x6, x7, 2273 false, &mbox_error, &send_id); 2274 SMC_RET4(handle, status, mbox_error, x5, x6); 2275 2276 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 2277 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2278 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2279 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2280 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2281 x4, x5, (uint32_t *) &x6, x7, 2282 true, &mbox_error, &send_id); 2283 SMC_RET4(handle, status, mbox_error, x5, x6); 2284 2285 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 2286 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2287 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 2288 x4, x5, &mbox_error); 2289 SMC_RET2(handle, status, mbox_error); 2290 2291 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 2292 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2293 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2294 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2295 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2296 false, &mbox_error, 0); 2297 SMC_RET4(handle, status, mbox_error, x5, x6); 2298 2299 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 2300 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2301 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2302 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2303 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2304 true, &mbox_error, 0); 2305 SMC_RET4(handle, status, mbox_error, x5, x6); 2306 2307 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 2308 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2309 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2310 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2311 x2, x3, x4, x5, (uint32_t *) &x6, false, 2312 &mbox_error, &send_id); 2313 SMC_RET4(handle, status, mbox_error, x5, x6); 2314 2315 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 2316 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2317 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2318 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2319 x2, x3, x4, x5, (uint32_t *) &x6, true, 2320 &mbox_error, &send_id); 2321 SMC_RET4(handle, status, mbox_error, x5, x6); 2322 2323 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 2324 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2325 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 2326 x4, x5, &mbox_error); 2327 SMC_RET2(handle, status, mbox_error); 2328 2329 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 2330 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2331 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2332 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, 0, x1, x2, 2333 x3, x4, x5, (uint32_t *) &x6, 2334 &mbox_error); 2335 SMC_RET4(handle, status, mbox_error, x5, x6); 2336 2337 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 2338 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2339 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 2340 x4, x5, &mbox_error); 2341 SMC_RET2(handle, status, mbox_error); 2342 2343 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 2344 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2345 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2346 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, 0, x1, 2347 x2, x3, x4, x5, (uint32_t *) &x6, 2348 &mbox_error); 2349 SMC_RET4(handle, status, mbox_error, x5, x6); 2350 2351 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 2352 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2353 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 2354 x4, x5, &mbox_error); 2355 SMC_RET2(handle, status, mbox_error); 2356 2357 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 2358 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2359 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2360 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2361 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2362 smc_fid, 0, x1, x2, x3, x4, x5, 2363 (uint32_t *) &x6, x7, false, 2364 &mbox_error, 0); 2365 SMC_RET4(handle, status, mbox_error, x5, x6); 2366 2367 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 2368 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2369 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2370 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2371 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2372 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2373 x7, false, &mbox_error, &send_id); 2374 SMC_RET4(handle, status, mbox_error, x5, x6); 2375 2376 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 2377 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2378 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2379 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2380 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2381 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2382 x7, true, &mbox_error, &send_id); 2383 SMC_RET4(handle, status, mbox_error, x5, x6); 2384 2385 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 2386 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2387 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2388 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2389 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2390 smc_fid, 0, x1, x2, x3, x4, x5, 2391 (uint32_t *) &x6, x7, true, 2392 &mbox_error, 0); 2393 SMC_RET4(handle, status, mbox_error, x5, x6); 2394 2395 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 2396 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2397 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 2398 x4, x5, &mbox_error); 2399 SMC_RET2(handle, status, mbox_error); 2400 2401 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 2402 status = intel_fcs_ecdsa_get_pubkey_finalize( 2403 INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE, 0, 2404 x1, x2, x3, (uint32_t *) &x4, &mbox_error); 2405 SMC_RET4(handle, status, mbox_error, x3, x4); 2406 2407 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 2408 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2409 status = intel_fcs_ecdh_request_init(x1, x2, x3, 2410 x4, x5, &mbox_error); 2411 SMC_RET2(handle, status, mbox_error); 2412 2413 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 2414 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2415 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2416 status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3, 2417 x4, x5, (uint32_t *) &x6, &mbox_error); 2418 SMC_RET4(handle, status, mbox_error, x5, x6); 2419 2420 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 2421 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2422 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 2423 &mbox_error); 2424 SMC_RET2(handle, status, mbox_error); 2425 2426 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 2427 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2428 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2429 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2430 x3, x4, x5, x6, 0, false, &send_id, 0, 0); 2431 SMC_RET1(handle, status); 2432 2433 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 2434 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2435 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2436 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2437 x3, x4, x5, x6, 0, true, &send_id, 0, 0); 2438 SMC_RET1(handle, status); 2439 2440 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2441 case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG: 2442 status = intel_smmu_hps_remapper_config(x1); 2443 SMC_RET1(handle, status); 2444 #endif 2445 2446 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 2447 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 2448 &mbox_error); 2449 SMC_RET4(handle, status, mbox_error, x1, retval64); 2450 2451 case INTEL_SIP_SMC_SVC_VERSION: 2452 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2453 SIP_SVC_VERSION_MAJOR, 2454 SIP_SVC_VERSION_MINOR); 2455 2456 case INTEL_SIP_SMC_SEU_ERR_STATUS: 2457 status = intel_sdm_seu_err_read(seu_respbuf, 2458 ARRAY_SIZE(seu_respbuf)); 2459 if (status) { 2460 SMC_RET1(handle, status); 2461 } else { 2462 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 2463 } 2464 2465 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 2466 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 2467 SMC_RET1(handle, status); 2468 2469 case INTEL_SIP_SMC_ATF_BUILD_VER: 2470 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR, 2471 VERSION_MINOR, VERSION_PATCH); 2472 2473 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2474 case INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR: 2475 intel_inject_io96b_ecc_err((uint32_t *)&x1, (uint32_t)x2); 2476 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 2477 #endif 2478 2479 default: 2480 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 2481 cookie, handle, flags); 2482 } 2483 } 2484 2485 uintptr_t sip_smc_handler(uint32_t smc_fid, 2486 u_register_t x1, 2487 u_register_t x2, 2488 u_register_t x3, 2489 u_register_t x4, 2490 void *cookie, 2491 void *handle, 2492 u_register_t flags) 2493 { 2494 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 2495 2496 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 2497 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 2498 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 2499 cookie, handle, flags); 2500 } 2501 #if SIP_SVC_V3 2502 else if ((cmd >= INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN) && 2503 (cmd <= INTEL_SIP_SMC_CMD_V3_RANGE_END)) { 2504 uintptr_t ret = sip_smc_handler_v3(smc_fid, x1, x2, x3, x4, 2505 cookie, handle, flags); 2506 return ret; 2507 } 2508 #endif 2509 else { 2510 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 2511 cookie, handle, flags); 2512 } 2513 } 2514 2515 DECLARE_RT_SVC( 2516 socfpga_sip_svc, 2517 OEN_SIP_START, 2518 OEN_SIP_END, 2519 SMC_TYPE_FAST, 2520 NULL, 2521 sip_smc_handler 2522 ); 2523 2524 DECLARE_RT_SVC( 2525 socfpga_sip_svc_std, 2526 OEN_SIP_START, 2527 OEN_SIP_END, 2528 SMC_TYPE_YIELD, 2529 NULL, 2530 sip_smc_handler 2531 ); 2532