1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/clk.h> 13 #include <drivers/delay_timer.h> 14 #include <drivers/st/stm32_console.h> 15 #include <drivers/st/stm32mp_clkfunc.h> 16 #include <drivers/st/stm32mp_reset.h> 17 #include <lib/mmio.h> 18 #include <lib/smccc.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 #include <services/arm_arch_svc.h> 22 23 #include <platform_def.h> 24 25 #define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16) 26 #define RESET_TIMEOUT_US_1MS 1000U 27 28 /* Internal layout of the 32bit OTP word board_id */ 29 #define BOARD_ID_BOARD_NB_MASK GENMASK_32(31, 16) 30 #define BOARD_ID_BOARD_NB_SHIFT 16 31 #define BOARD_ID_VARCPN_MASK GENMASK_32(15, 12) 32 #define BOARD_ID_VARCPN_SHIFT 12 33 #define BOARD_ID_REVISION_MASK GENMASK_32(11, 8) 34 #define BOARD_ID_REVISION_SHIFT 8 35 #define BOARD_ID_VARFG_MASK GENMASK_32(7, 4) 36 #define BOARD_ID_VARFG_SHIFT 4 37 #define BOARD_ID_BOM_MASK GENMASK_32(3, 0) 38 39 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 40 BOARD_ID_BOARD_NB_SHIFT) 41 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ 42 BOARD_ID_VARCPN_SHIFT) 43 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 44 BOARD_ID_REVISION_SHIFT) 45 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ 46 BOARD_ID_VARFG_SHIFT) 47 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 48 49 #define BOOT_AUTH_MASK GENMASK_32(23, 20) 50 #define BOOT_AUTH_SHIFT 20 51 #define BOOT_PART_MASK GENMASK_32(19, 16) 52 #define BOOT_PART_SHIFT 16 53 #define BOOT_ITF_MASK GENMASK_32(15, 12) 54 #define BOOT_ITF_SHIFT 12 55 #define BOOT_INST_MASK GENMASK_32(11, 8) 56 #define BOOT_INST_SHIFT 8 57 58 /* Layout for fwu update information. */ 59 #define FWU_INFO_IDX_MSK GENMASK(3, 0) 60 #define FWU_INFO_IDX_OFF U(0) 61 #define FWU_INFO_CNT_MSK GENMASK(7, 4) 62 #define FWU_INFO_CNT_OFF U(4) 63 64 static console_t console; 65 66 uintptr_t plat_get_ns_image_entrypoint(void) 67 { 68 return BL33_BASE; 69 } 70 71 unsigned int plat_get_syscnt_freq2(void) 72 { 73 return read_cntfrq_el0(); 74 } 75 76 static uintptr_t boot_ctx_address; 77 static uint16_t boot_itf_selected; 78 79 void stm32mp_save_boot_ctx_address(uintptr_t address) 80 { 81 boot_api_context_t *boot_context = (boot_api_context_t *)address; 82 83 boot_ctx_address = address; 84 boot_itf_selected = boot_context->boot_interface_selected; 85 } 86 87 uintptr_t stm32mp_get_boot_ctx_address(void) 88 { 89 return boot_ctx_address; 90 } 91 92 uint16_t stm32mp_get_boot_itf_selected(void) 93 { 94 return boot_itf_selected; 95 } 96 97 uintptr_t stm32mp_ddrctrl_base(void) 98 { 99 return DDRCTRL_BASE; 100 } 101 102 uintptr_t stm32mp_ddrphyc_base(void) 103 { 104 return DDRPHYC_BASE; 105 } 106 107 uintptr_t stm32mp_pwr_base(void) 108 { 109 return PWR_BASE; 110 } 111 112 uintptr_t stm32mp_rcc_base(void) 113 { 114 return RCC_BASE; 115 } 116 117 bool stm32mp_lock_available(void) 118 { 119 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT; 120 121 /* The spinlocks are used only when MMU and data cache are enabled */ 122 #ifdef __aarch64__ 123 return (read_sctlr_el3() & c_m_bits) == c_m_bits; 124 #else 125 return (read_sctlr() & c_m_bits) == c_m_bits; 126 #endif 127 } 128 129 int stm32mp_map_ddr_non_cacheable(void) 130 { 131 return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 132 STM32MP_DDR_MAX_SIZE, 133 MT_NON_CACHEABLE | MT_RW | MT_SECURE); 134 } 135 136 int stm32mp_unmap_ddr(void) 137 { 138 return mmap_remove_dynamic_region(STM32MP_DDR_BASE, 139 STM32MP_DDR_MAX_SIZE); 140 } 141 142 int stm32_get_otp_index(const char *otp_name, uint32_t *otp_idx, 143 uint32_t *otp_len) 144 { 145 assert(otp_name != NULL); 146 assert(otp_idx != NULL); 147 148 return dt_find_otp_name(otp_name, otp_idx, otp_len); 149 } 150 151 int stm32_get_otp_value(const char *otp_name, uint32_t *otp_val) 152 { 153 uint32_t otp_idx; 154 155 assert(otp_name != NULL); 156 assert(otp_val != NULL); 157 158 if (stm32_get_otp_index(otp_name, &otp_idx, NULL) != 0) { 159 return -1; 160 } 161 162 if (stm32_get_otp_value_from_idx(otp_idx, otp_val) != 0) { 163 ERROR("BSEC: %s Read Error\n", otp_name); 164 return -1; 165 } 166 167 return 0; 168 } 169 170 int stm32_get_otp_value_from_idx(const uint32_t otp_idx, uint32_t *otp_val) 171 { 172 uint32_t ret = BSEC_NOT_SUPPORTED; 173 174 assert(otp_val != NULL); 175 176 #if defined(IMAGE_BL2) 177 ret = stm32_otp_shadow_read(otp_val, otp_idx); 178 #elif defined(IMAGE_BL31) || defined(IMAGE_BL32) 179 ret = stm32_otp_read(otp_val, otp_idx); 180 #else 181 #error "Not supported" 182 #endif 183 if (ret != BSEC_OK) { 184 ERROR("BSEC: idx=%u Read Error\n", otp_idx); 185 return -1; 186 } 187 188 return 0; 189 } 190 191 int stm32_get_uid_otp(uint32_t uid[]) 192 { 193 uint8_t i; 194 uint32_t otp; 195 uint32_t len; 196 197 if (stm32_get_otp_index(UID_OTP, &otp, &len) != 0) { 198 ERROR("BSEC: Get UID_OTP number Error\n"); 199 return -1; 200 } 201 202 if ((len / __WORD_BIT) != UID_WORD_NB) { 203 ERROR("BSEC: Get UID_OTP length Error\n"); 204 return -1; 205 } 206 207 for (i = 0U; i < UID_WORD_NB; i++) { 208 if (stm32_otp_shadow_read(&uid[i], i + otp) != BSEC_OK) { 209 ERROR("BSEC: UID%u Error\n", i); 210 return -1; 211 } 212 } 213 214 return 0; 215 } 216 217 #if defined(IMAGE_BL2) 218 static void reset_uart(uint32_t reset) 219 { 220 int ret; 221 222 ret = stm32mp_reset_assert(reset, RESET_TIMEOUT_US_1MS); 223 if (ret != 0) { 224 panic(); 225 } 226 227 udelay(2); 228 229 ret = stm32mp_reset_deassert(reset, RESET_TIMEOUT_US_1MS); 230 if (ret != 0) { 231 panic(); 232 } 233 234 mdelay(1); 235 } 236 #endif 237 238 static void set_console(uintptr_t base, uint32_t clk_rate) 239 { 240 unsigned int console_flags; 241 242 if (console_stm32_register(base, clk_rate, 243 (uint32_t)STM32MP_UART_BAUDRATE, &console) == 0) { 244 panic(); 245 } 246 247 console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH | 248 CONSOLE_FLAG_TRANSLATE_CRLF; 249 #if !defined(IMAGE_BL2) && defined(DEBUG) 250 console_flags |= CONSOLE_FLAG_RUNTIME; 251 #endif 252 253 console_set_scope(&console, console_flags); 254 } 255 256 int stm32mp_uart_console_setup(void) 257 { 258 struct dt_node_info dt_uart_info; 259 uint32_t clk_rate = 0U; 260 int result; 261 uint32_t boot_itf __unused; 262 uint32_t boot_instance __unused; 263 264 result = dt_get_stdout_uart_info(&dt_uart_info); 265 266 if ((result <= 0) || 267 (dt_uart_info.status == DT_DISABLED)) { 268 return -ENODEV; 269 } 270 271 #if defined(IMAGE_BL2) 272 if ((dt_uart_info.clock < 0) || 273 (dt_uart_info.reset < 0)) { 274 return -ENODEV; 275 } 276 #endif 277 278 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 279 stm32_get_boot_interface(&boot_itf, &boot_instance); 280 281 if ((boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) && 282 (get_uart_address(boot_instance) == dt_uart_info.base)) { 283 return -EACCES; 284 } 285 #endif 286 287 #if defined(IMAGE_BL2) 288 if (dt_set_stdout_pinctrl() != 0) { 289 return -ENODEV; 290 } 291 292 clk_enable((unsigned long)dt_uart_info.clock); 293 294 reset_uart((uint32_t)dt_uart_info.reset); 295 296 clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock); 297 #endif 298 299 set_console(dt_uart_info.base, clk_rate); 300 301 return 0; 302 } 303 304 #if EARLY_CONSOLE 305 void plat_setup_early_console(void) 306 { 307 #if defined(IMAGE_BL2) || STM32MP_RECONFIGURE_CONSOLE 308 plat_crash_console_init(); 309 #endif 310 set_console(STM32MP_DEBUG_USART_BASE, STM32MP_DEBUG_USART_CLK_FRQ); 311 NOTICE("Early console setup\n"); 312 } 313 #endif /* EARLY_CONSOLE */ 314 315 /***************************************************************************** 316 * plat_is_smccc_feature_available() - This function checks whether SMCCC 317 * feature is availabile for platform. 318 * @fid: SMCCC function id 319 * 320 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 321 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 322 *****************************************************************************/ 323 int32_t plat_is_smccc_feature_available(u_register_t fid) 324 { 325 switch (fid) { 326 case SMCCC_ARCH_SOC_ID: 327 return SMC_ARCH_CALL_SUCCESS; 328 default: 329 return SMC_ARCH_CALL_NOT_SUPPORTED; 330 } 331 } 332 333 /* Get SOC version */ 334 int32_t plat_get_soc_version(void) 335 { 336 uint32_t chip_id = stm32mp_get_chip_dev_id(); 337 uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID); 338 339 return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK)); 340 } 341 342 /* Get SOC revision */ 343 int32_t plat_get_soc_revision(void) 344 { 345 return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK); 346 } 347 348 void stm32_display_board_info(uint32_t board_id) 349 { 350 char rev[2]; 351 352 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 353 rev[1] = '\0'; 354 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", 355 BOARD_ID2NB(board_id), 356 BOARD_ID2VARCPN(board_id), 357 BOARD_ID2VARFG(board_id), 358 rev, 359 BOARD_ID2BOM(board_id)); 360 } 361 362 void stm32_save_boot_info(boot_api_context_t *boot_context) 363 { 364 uint32_t auth_status; 365 366 assert(boot_context->boot_interface_instance <= (BOOT_INST_MASK >> BOOT_INST_SHIFT)); 367 assert(boot_context->boot_interface_selected <= (BOOT_ITF_MASK >> BOOT_ITF_SHIFT)); 368 assert(boot_context->boot_partition_used_toboot <= (BOOT_PART_MASK >> BOOT_PART_SHIFT)); 369 370 switch (boot_context->auth_status) { 371 case BOOT_API_CTX_AUTH_NO: 372 auth_status = 0x0U; 373 break; 374 375 case BOOT_API_CTX_AUTH_SUCCESS: 376 auth_status = 0x2U; 377 break; 378 379 case BOOT_API_CTX_AUTH_FAILED: 380 default: 381 auth_status = 0x1U; 382 break; 383 } 384 385 clk_enable(TAMP_BKP_REG_CLK); 386 387 mmio_clrsetbits_32(stm32_get_bkpr_boot_mode_addr(), 388 BOOT_ITF_MASK | BOOT_INST_MASK | BOOT_PART_MASK | BOOT_AUTH_MASK, 389 (boot_context->boot_interface_instance << BOOT_INST_SHIFT) | 390 (boot_context->boot_interface_selected << BOOT_ITF_SHIFT) | 391 (boot_context->boot_partition_used_toboot << BOOT_PART_SHIFT) | 392 (auth_status << BOOT_AUTH_SHIFT)); 393 394 clk_disable(TAMP_BKP_REG_CLK); 395 } 396 397 void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance) 398 { 399 static uint32_t itf; 400 401 if (itf == 0U) { 402 clk_enable(TAMP_BKP_REG_CLK); 403 404 itf = mmio_read_32(stm32_get_bkpr_boot_mode_addr()) & 405 (BOOT_ITF_MASK | BOOT_INST_MASK); 406 407 clk_disable(TAMP_BKP_REG_CLK); 408 } 409 410 *interface = (itf & BOOT_ITF_MASK) >> BOOT_ITF_SHIFT; 411 *instance = (itf & BOOT_INST_MASK) >> BOOT_INST_SHIFT; 412 } 413 414 #if PSA_FWU_SUPPORT 415 void stm32_fwu_set_boot_idx(void) 416 { 417 clk_enable(TAMP_BKP_REG_CLK); 418 mmio_clrsetbits_32(stm32_get_bkpr_fwu_info_addr(), 419 FWU_INFO_IDX_MSK, 420 (plat_fwu_get_boot_idx() << FWU_INFO_IDX_OFF) & 421 FWU_INFO_IDX_MSK); 422 clk_disable(TAMP_BKP_REG_CLK); 423 } 424 425 uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void) 426 { 427 uintptr_t bkpr_fwu_cnt = stm32_get_bkpr_fwu_info_addr(); 428 uint32_t try_cnt; 429 430 clk_enable(TAMP_BKP_REG_CLK); 431 try_cnt = (mmio_read_32(bkpr_fwu_cnt) & FWU_INFO_CNT_MSK) >> FWU_INFO_CNT_OFF; 432 433 assert(try_cnt <= FWU_MAX_TRIAL_REBOOT); 434 435 if (try_cnt != 0U) { 436 mmio_clrsetbits_32(bkpr_fwu_cnt, FWU_INFO_CNT_MSK, 437 (try_cnt - 1U) << FWU_INFO_CNT_OFF); 438 } 439 clk_disable(TAMP_BKP_REG_CLK); 440 441 return try_cnt; 442 } 443 444 void stm32_set_max_fwu_trial_boot_cnt(void) 445 { 446 uintptr_t bkpr_fwu_cnt = stm32_get_bkpr_fwu_info_addr(); 447 448 clk_enable(TAMP_BKP_REG_CLK); 449 mmio_clrsetbits_32(bkpr_fwu_cnt, FWU_INFO_CNT_MSK, 450 (FWU_MAX_TRIAL_REBOOT << FWU_INFO_CNT_OFF) & FWU_INFO_CNT_MSK); 451 clk_disable(TAMP_BKP_REG_CLK); 452 } 453 454 void stm32_clear_fwu_trial_boot_cnt(void) 455 { 456 uintptr_t bkpr_fwu_cnt = stm32_get_bkpr_fwu_info_addr(); 457 458 clk_enable(TAMP_BKP_REG_CLK); 459 mmio_clrbits_32(bkpr_fwu_cnt, FWU_INFO_CNT_MSK); 460 clk_disable(TAMP_BKP_REG_CLK); 461 } 462 #endif /* PSA_FWU_SUPPORT */ 463