1 /* 2 * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. 3 * Copyright (c) 2025, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef CDN_COMBOPHY_H 9 #define CDN_COMBOPHY_H 10 11 /* SRS */ 12 #define SDMMC_CDN_SRS02 0x8 13 #define SDMMC_CDN_SRS03 0xC 14 #define SDMMC_CDN_SRS04 0x10 15 #define SDMMC_CDN_SRS05 0x14 16 #define SDMMC_CDN_SRS06 0x18 17 #define SDMMC_CDN_SRS07 0x1C 18 #define SDMMC_CDN_SRS09 0x24 19 #define SDMMC_CDN_SRS10 0x28 20 #define SDMMC_CDN_SRS11 0x2C 21 #define SDMMC_CDN_SRS12 0x30 22 #define SDMMC_CDN_SRS13 0x34 23 #define SDMMC_CDN_SRS14 0x38 24 25 /* SRS03 */ 26 /* Response Type Select 27 * Defines the expected response length. 28 */ 29 #define SDMMC_CDN_RTS 16 30 31 /* Command CRC Check Enable 32 * When set to 1, the host checks if the CRC field of the response is valid. 33 * When 0, the CRC check is disabled and the CRC field of the response is ignored. 34 */ 35 #define SDMMC_CDN_CRCCE 19 36 37 /* Command Index 38 * This field contains a command number (index) of the command to be sent. 39 */ 40 #define SDMMC_CDN_CIDX 24 41 42 /* SRS09 */ 43 /* Card Inserted 44 * Indicates if the card is inserted inside the slot. 45 */ 46 #define SDMMC_CDN_CI 16 47 48 /* SRS10 */ 49 /* Data Transfer Width 50 * Bit used to configure DAT bus width to 1 or 4. 51 */ 52 #define SDMMC_CDN_DTW 1 53 54 /* Extended Data Transfer Width 55 * This bit is to enable/disable 8-bit DAT bus width mode. 56 */ 57 #define SDMMC_CDN_EDTW 5 58 59 /* SD Bus Power for VDD1 60 * When set to 1, the VDD1 voltage is supplied to card/device. 61 */ 62 #define SDMMC_CDN_BP 8 63 64 /* SD Bus Voltage Select 65 * This field is used to configure VDD1 voltage level. 66 */ 67 #define SDMMC_CDN_BVS 9 68 69 /* SRS11 */ 70 /* Internal Clock Enable 71 * This field is designated to controls (enable/disable) external clock generator. 72 */ 73 #define SDMMC_CDN_ICE 0 74 75 /* Internal Clock Stable 76 * When 1, indicates that the clock on sdmclk pin of the host is stable. 77 * When 0, indicates that the clock is not stable . 78 */ 79 #define SDMMC_CDN_ICS 1 80 81 /* SD Clock Enable 82 * When set, SDCLK clock is enabled. 83 * When clear, SDCLK clock is stopped. 84 */ 85 #define SDMMC_CDN_SDCE 2 86 87 /* USDCLK Frequency Select 88 * This is used to calculate frequency of USDCLK clock. 89 */ 90 #define SDMMC_CDN_USDCLKFS 6 91 92 /* SDCLK Frequency Select 93 * This is used to calculate frequency of SDCLK clock. 94 */ 95 #define SDMMC_CDN_SDCLKFS 8 96 97 /* Data Timeout Counter Value 98 * This value determines the interval by which DAT line timeouts are detected 99 */ 100 #define SDMMC_CDN_DTCV 16 101 102 /* SRS12 */ 103 /* Command Complete 104 * Generated when the end bit of the response is received. 105 */ 106 #define SDMMC_CDN_CC 0 107 108 /* Transfer Complete 109 * Generated when the transfer which uses the DAT line is complete. 110 */ 111 #define SDMMC_CDN_TC 1 112 113 /* Error Interrupt 114 * The software can check for an error by reading this single bit first. 115 */ 116 #define SDMMC_CDN_EINT 15 117 118 /* SRS14 */ 119 /* Command Complete Interrupt Enable */ 120 #define SDMMC_CDN_CC_IE 0 121 122 /* Transfer Complete Interrupt Enable */ 123 #define SDMMC_CDN_TC_IE 1 124 125 /* DMA Interrupt Enable */ 126 #define SDMMC_CDN_DMAINT_IE 3 127 128 /* Combo PHY DLL registers */ 129 #define CP_DLL_REG_BASE (0x10B92000) 130 #define CP_DLL_DQ_TIMING_REG (0x00) 131 #define CP_DLL_DQS_TIMING_REG (0x04) 132 #define CP_DLL_GATE_LPBK_CTRL_REG (0x08) 133 #define CP_DLL_MASTER_CTRL_REG (0x0C) 134 #define CP_DLL_SLAVE_CTRL_REG (0x10) 135 #define CP_DLL_IE_TIMING_REG (0x14) 136 137 #define CP_DQ_TIMING_REG_SDR (0x00000002) 138 #define CP_DQS_TIMING_REG_SDR (0x00110004) 139 #define CP_GATE_LPBK_CTRL_REG_SDR (0x00680000) 140 #define CP_DLL_MASTER_CTRL_REG_SDR (0x00800000) 141 #define CP_DLL_SLAVE_CTRL_REG_SDR (0x00000000) 142 143 #define CP_DLL(_reg) (CP_DLL_REG_BASE \ 144 + (CP_DLL_##_reg)) 145 146 /* Control Timing Block registers */ 147 #define CP_CTB_REG_BASE (0x10B92080) 148 #define CP_CTB_CTRL_REG (0x00) 149 #define CP_CTB_TSEL_REG (0x04) 150 #define CP_CTB_GPIO_CTRL0 (0x08) 151 #define CP_CTB_GPIO_CTRL1 (0x0C) 152 #define CP_CTB_GPIO_STATUS0 (0x10) 153 #define CP_CTB_GPIO_STATUS1 (0x14) 154 155 #define CP_CTRL_REG_SDR (0x000040a0) 156 #define CP_TSEL_REG_SDR (0x00000000) 157 158 #define CP_CTB(_reg) (CP_CTB_REG_BASE \ 159 + (CP_CTB_##_reg)) 160 161 /* Combo PHY */ 162 #define SDMMC_CDN_REG_BASE 0x10808200 163 #define PHY_DQ_TIMING_REG 0x2000 164 #define PHY_DQS_TIMING_REG 0x2004 165 #define PHY_GATE_LPBK_CTRL_REG 0x2008 166 #define PHY_DLL_MASTER_CTRL_REG 0x200C 167 #define PHY_DLL_SLAVE_CTRL_REG 0x2010 168 #define PHY_CTRL_REG 0x2080 169 #define PHY_REG_ADDR_MASK 0xFFFF 170 #define PHY_REG_DATA_MASK 0xFFFFFFFF 171 172 /* PHY_DQS_TIMING_REG */ 173 #define CP_USE_EXT_LPBK_DQS(x) ((x) << 22) //0x1 174 #define CP_USE_LPBK_DQS(x) ((x) << 21) //0x1 175 #define CP_USE_PHONY_DQS(x) ((x) << 20) //0x1 176 #define CP_USE_PHONY_DQS_CMD(x) ((x) << 19) //0x1 177 178 /* PHY_GATE_LPBK_CTRL_REG */ 179 #define CP_SYNC_METHOD(x) ((x) << 31) //0x1 180 #define CP_SW_HALF_CYCLE_SHIFT(x) ((x) << 28) //0x1 181 #define CP_RD_DEL_SEL(x) ((x) << 19) //0x3f 182 #define CP_UNDERRUN_SUPPRESS(x) ((x) << 18) //0x1 183 #define CP_GATE_CFG_ALWAYS_ON(x) ((x) << 6) //0x1 184 185 /* PHY_DLL_MASTER_CTRL_REG */ 186 #define CP_DLL_BYPASS_MODE(x) ((x) << 23) //0x1 187 #define CP_DLL_START_POINT(x) ((x) << 0) //0xff 188 189 /* PHY_DLL_SLAVE_CTRL_REG */ 190 #define CP_READ_DQS_CMD_DELAY(x) ((x) << 24) //0xff 191 #define CP_CLK_WRDQS_DELAY(x) ((x) << 16) //0xff 192 #define CP_CLK_WR_DELAY(x) ((x) << 8) //0xff 193 #define CP_READ_DQS_DELAY(x) ((x) << 0) //0xff 194 195 /* PHY_DQ_TIMING_REG */ 196 #define CP_IO_MASK_ALWAYS_ON(x) ((x) << 31) //0x1 197 #define CP_IO_MASK_END(x) ((x) << 27) //0x7 198 #define CP_IO_MASK_START(x) ((x) << 24) //0x7 199 #define CP_DATA_SELECT_OE_END(x) ((x) << 0) //0x7 200 201 /* PHY_CTRL_REG */ 202 #define CP_PHONY_DQS_TIMING_MASK 0x3F 203 #define CP_PHONY_DQS_TIMING_SHIFT 4 204 205 /* Shared Macros */ 206 #define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ 207 (SDMMC_CDN_##_reg)) 208 209 struct cdns_sdmmc_combo_phy { 210 uint32_t cp_clk_wr_delay; 211 uint32_t cp_clk_wrdqs_delay; 212 uint32_t cp_data_select_oe_end; 213 uint32_t cp_dll_bypass_mode; 214 uint32_t cp_dll_locked_mode; 215 uint32_t cp_dll_start_point; 216 uint32_t cp_gate_cfg_always_on; 217 uint32_t cp_io_mask_always_on; 218 uint32_t cp_io_mask_end; 219 uint32_t cp_io_mask_start; 220 uint32_t cp_rd_del_sel; 221 uint32_t cp_read_dqs_cmd_delay; 222 uint32_t cp_read_dqs_delay; 223 uint32_t cp_sw_half_cycle_shift; 224 uint32_t cp_sync_method; 225 uint32_t cp_underrun_suppress; 226 uint32_t cp_use_ext_lpbk_dqs; 227 uint32_t cp_use_lpbk_dqs; 228 uint32_t cp_use_phony_dqs; 229 uint32_t cp_use_phony_dqs_cmd; 230 }; 231 232 /* Function Prototype */ 233 234 int cdns_sdmmc_write_phy_reg(uint32_t phy_reg_addr, uint32_t phy_reg_addr_value, 235 uint32_t phy_reg_data, uint32_t phy_reg_data_value); 236 int cdns_sd_card_detect(void); 237 int cdns_emmc_card_reset(void); 238 239 #endif