| dee99f10 | 15-Mar-2023 |
Yann Gautier <yann.gautier@st.com> |
refactor(auth)!: unify REGISTER_CRYPTO_LIB
Have only one definition for REGISTER_CRYPTO_LIB macro, with all the possible fields. Worst case adds 4 u64 to crypto_lib_desc. While at it, correct some M
refactor(auth)!: unify REGISTER_CRYPTO_LIB
Have only one definition for REGISTER_CRYPTO_LIB macro, with all the possible fields. Worst case adds 4 u64 to crypto_lib_desc. While at it, correct some MISRA violations: MC3R1.R12.1: (advisory) The precedence of operators within expressions should be made explicit.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I1342a20e6eef2354753182c2a81ff959e03e5c81
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| 2d541cbc | 02-Sep-2022 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
fix(nxp-ddr): fix coverity issue
Fixed coverity issue for "shifting by a negtive value", returned before go to the next shifting code.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I001
fix(nxp-ddr): fix coverity issue
Fixed coverity issue for "shifting by a negtive value", returned before go to the next shifting code.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I00171b057b8948cb9e9ec5d9405b2e32aba568fb
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| 87612eae | 16-Aug-2022 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
fix(nxp-ddr): fix underrun coverity issue
Coverity Issue detail:
underrun-local: Underrunning array bin[i].cl[k].caslat at element index -1 (byte offset -1) using in
fix(nxp-ddr): fix underrun coverity issue
Coverity Issue detail:
underrun-local: Underrunning array bin[i].cl[k].caslat at element index -1 (byte offset -1) using index j (which evaluates to -1).
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I1ec4833bbd5db1ac51436eac606484eefc4338ee
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| 334badb5 | 18-May-2022 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
fix(nxp-crypto): fix secure boot assert inclusion
plat-ls: fix for assert inclusion done for secure boot.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nx
fix(nxp-crypto): fix secure boot assert inclusion
plat-ls: fix for assert inclusion done for secure boot.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Iac8314e5b1c2f0a22fa2ff3ffbccc53ed778ddd9
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| e4922991 | 17-May-2022 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
fix(nxp-crypto): fix coverity issue
In function "desc_length", LSB byte of the first word of the descriptor will be anded with 0x7F, to get the number of words constructing the descriptor.
LSB byte
fix(nxp-crypto): fix coverity issue
In function "desc_length", LSB byte of the first word of the descriptor will be anded with 0x7F, to get the number of words constructing the descriptor.
LSB byte of the first word of the descriptor is auto-incremented with each add_word used while constructing the descriptor.
But if function "desc_add_word" is called more than MAX_DESC_SIZE_WORDS times, then only the function "desc_length", can return number of words greater than MAX_DESC_SIZE_WORDS.
This is the condition when core can overwrite the out of bound memory.
Hence, the following fix is needed: - Before adding any new word to the descriptor, a check for max word length needs to be added, into these functions: "desc_add_word" & "desc_add_ptr".
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: If896cd2e02ecde72fb09c5147119dec4f2f84bc3
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| 5199b3b9 | 13-May-2022 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
fix(nxp-drivers): fix fspi coverity issue
Fixed the following coverity issues: Using uninitialized value cmd_id1, cmd_id2.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I8cd430ec015fc61
fix(nxp-drivers): fix fspi coverity issue
Fixed the following coverity issues: Using uninitialized value cmd_id1, cmd_id2.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I8cd430ec015fc617521db455a6ffe16b33f42b78
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| 00bb8c37 | 31-Jan-2022 |
Maninder Singh <maninder.singh_1@nxp.com> |
fix(nxp-ddr): apply Max CDD values for warm boot
Timing CFG 0 and Timing CFG 4 are ddr controller registers that have been affected by 1d phy training during cold boot. They are needed to be stored
fix(nxp-ddr): apply Max CDD values for warm boot
Timing CFG 0 and Timing CFG 4 are ddr controller registers that have been affected by 1d phy training during cold boot. They are needed to be stored and restored along with phy training values.
Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I29c55256e74456515aaeb098e2e0e3475697a466
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