Merge "feat(s32g274ardb): use DDR reset deassertion" into integration

Merge changes from topic "upstream_ddr_training" into integration

* changes:
feat(s32g274ardb): add DDR post training setup
feat(s32g274ardb): add training for 1D and 2D
feat(s32g274ardb): add

Merge changes from topic "upstream_ddr_training" into integration

* changes:
feat(s32g274ardb): add DDR post training setup
feat(s32g274ardb): add training for 1D and 2D
feat(s32g274ardb): add DDR training stubs

show more ...

feat(s32g274ardb): add DDR post training setup

Add the final configuration step after PHY
training, including CSR storage, memory
initialization and DDRC adjustments.

The post training setup is now

feat(s32g274ardb): add DDR post training setup

Add the final configuration step after PHY
training, including CSR storage, memory
initialization and DDRC adjustments.

The post training setup is now integrated into
the DDR initialization flow.

Change-Id: I457d1f58479b282607c9d42773d6f922f563b2fb
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

show more ...

feat(s32g274ardb): add training for 1D and 2D

Extend the logic for executing the training stage
to include 1D and 2D PHY training.

Change-Id: If3445125d868e67cfcd81eaeeb20b2283731a4ea
Signed-off-by

feat(s32g274ardb): add training for 1D and 2D

Extend the logic for executing the training stage
to include 1D and 2D PHY training.

Change-Id: If3445125d868e67cfcd81eaeeb20b2283731a4ea
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

show more ...

feat(s32g274ardb): add DDR training stubs

Introduce logic to load DDR firmware configuration
data from memory into internal structures.

Introduce the components required to initialize
the DDR contr

feat(s32g274ardb): add DDR training stubs

Introduce logic to load DDR firmware configuration
data from memory into internal structures.

Introduce the components required to initialize
the DDR controller and prepare for PHY training.
It includes controller setup and the training
orchestration function.

Change-Id: Icd8649516d9bad1a6d72616a774b8b60c6bae067
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

show more ...

refactor(s32g274ardb): add MC RGM DDR periph macro

Replace value with MC_RGM_DDR_PERIPH macro
to clearly identify the DDR peripheral ID
used in MC_RGM register operations.

Change-Id: I43756e5df068f

refactor(s32g274ardb): add MC RGM DDR periph macro

Replace value with MC_RGM_DDR_PERIPH macro
to clearly identify the DDR peripheral ID
used in MC_RGM register operations.

Change-Id: I43756e5df068fb4f523b37a9db3a4a9ce8be836a
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

show more ...

feat(s32g274ardb): use DDR reset deassertion

The DDR reset must be deasserted after
configuring AXI parity to guarantee the DDRC
registers are accessible for configuration
and PHY training.

Change-

feat(s32g274ardb): use DDR reset deassertion

The DDR reset must be deasserted after
configuring AXI parity to guarantee the DDRC
registers are accessible for configuration
and PHY training.

Change-Id: I80b8df9a7f0058941083893d4e7bb728768ae236
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

show more ...

Merge changes from topic "upstream_ddr_reg_accesories" into integration

* changes:
feat(s32g274ardb): add DDR register accessories
feat(s32g274ardb): add DDR PHY mailbox support

fix(nxp-ddr): fix improper disable of first DDRC

Fixes an issue where the first DDRC is disabled improperly
when two DDRCs are present and only the second DDRC slot is
populated with a DIMM.

Change

fix(nxp-ddr): fix improper disable of first DDRC

Fixes an issue where the first DDRC is disabled improperly
when two DDRCs are present and only the second DDRC slot is
populated with a DIMM.

Change-Id: Ia4f71c5e79fa318a81a291080494f25e76fd987f
Signed-off-by: Roman Meier <romameie@outlook.com>

show more ...

feat(s32g274ardb): add DDR register accessories

Introduce a set of helper functions that
simplify register reads, bitfield updates,
AXI parity configuration and extraction
of training values.

These

feat(s32g274ardb): add DDR register accessories

Introduce a set of helper functions that
simplify register reads, bitfield updates,
AXI parity configuration and extraction
of training values.

These utilities encapsulate register access
patterns and are used for delay calibration,
Vref averaging, memory type detection and PLL
source selection.

Change-Id: I5415a650f6430578a8cca13ff7e144b471c61466
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

show more ...

feat(s32g274ardb): add DDR PHY mailbox support

Introduce mailbox handling between the DDR
controller and the PHY firmware, providing
mechanisms for message exchange, acknowledgments,
and execution s

feat(s32g274ardb): add DDR PHY mailbox support

Introduce mailbox handling between the DDR
controller and the PHY firmware, providing
mechanisms for message exchange, acknowledgments,
and execution status monitoring.

This enables reliable tracking of firmware
progress during DDR initialization and training,

Change-Id: I4fdd582fcc9a88c09c820ce9e59fe14ec3c043a8
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

show more ...

feat(s32g274ardb): add DDR clock source support

Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.

These utilities are required before
i

feat(s32g274ardb): add DDR clock source support

Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.

These utilities are required before
initializing the DDR subsystem.

Change-Id: I48cc984f73fca5cde1b81e9075488fd5bed420d6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

show more ...

feat(s32g274ardb): add mc_rgm_release_periph func

Add `mc_rgm_release_periph` function to
allow callers to specify which particular
peripheral should be released from reset.

Update the existing `mc

feat(s32g274ardb): add mc_rgm_release_periph func

Add `mc_rgm_release_periph` function to
allow callers to specify which particular
peripheral should be released from reset.

Update the existing `mc_rgm_release_part`
to make use of `mc_rgm_release_periph` function.

Change-Id: Ia2e049ac461f823379ddce34b1406eea0a0a86e9
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

show more ...

Merge "fix(nxp-ddr): add missing macro define for Errata A009663" into integration

feat(imx9): add full system power control option

Add an optional build-time configuration to enable full system
shutdown and reset control through SCMI.

By default, only logical machine (cluster-le

feat(imx9): add full system power control option

Add an optional build-time configuration to enable full system
shutdown and reset control through SCMI.

By default, only logical machine (cluster-level) power-off and
reset are performed. When the SYS_PWR_FULL_CTRL option is set,
the PSCI implementation uses the full system power control
commands instead, allowing a complete system shutdown and reset.

Tested on iMX95 based modules.

Change-Id: I56b31f9b91def31784857f5a299c69f68db706a4
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>

show more ...

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assist

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assisted coherency by default, so compiling empty
definitions is unnecessary.

This refactor removes those empty functions for Arm CSS platforms.

Change-Id: I102ead46960e9da2d8b968f60cbfd3e5e5da1096
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

show more ...

feat(scmi): add i.MX9 SCMI vendor CPU protocol

Add i.MX9 SCMI vendor specific CPU protocol

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.c

feat(scmi): add i.MX9 SCMI vendor CPU protocol

Add i.MX9 SCMI vendor specific CPU protocol

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Icc81bf9f4a32c08e4a3c358b1cf561ca4345a431

show more ...

fix(nxp-ddr): add missing macro define for Errata A009663

Even though platform support was added in commit 3b0de9182
("feat(plat/nxp/ls1043a): add ls1043a soc support"), the workaround
for errata A0

fix(nxp-ddr): add missing macro define for Errata A009663

Even though platform support was added in commit 3b0de9182
("feat(plat/nxp/ls1043a): add ls1043a soc support"), the workaround
for errata A009663 was not applied due to missing define.

Change-Id: I4f3669adf02dea487f89f81d2fc7344bb65f830d
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

show more ...

Merge "fix(nxp-crypto): restricts generating nxp_mkvb via ns-world" into integration

Merge changes Iea4c11de,Icae1fb08 into integration

* changes:
fix(lx2160): add DDRC missing DIMMs
fix(nxp): driver crypto caam

fix(nxp-crypto): restricts generating nxp_mkvb via ns-world

Master-key-verification-blob (MKVB) value generated on request from
the secure world, is same to the MKVB value generated on request from

fix(nxp-crypto): restricts generating nxp_mkvb via ns-world

Master-key-verification-blob (MKVB) value generated on request from
the secure world, is same to the MKVB value generated on request from
Normal world. Leading to the leak og MKVB to non-secure world.

Fix to prevent MKVB generation for requests originating from non-secure
world.
- For non-secure world, this SMC is return failure.

Additional fix for bound-check before continuing to generate the MKVB.

Change-Id: I9940b4dfe33289c2d57595a2a08acff29a12c974
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>

show more ...

fix(nxp): driver crypto caam

Fix based on code review. Then, it was checked with NXP Flexbuild and
their fix has been imported.

Change-Id: Icae1fb08b07bca5d4f6771e92b48d9e2071da0ee
Signed-off-by: V

fix(nxp): driver crypto caam

Fix based on code review. Then, it was checked with NXP Flexbuild and
their fix has been imported.

Change-Id: Icae1fb08b07bca5d4f6771e92b48d9e2071da0ee
Signed-off-by: Vincent Jardin <vjardin@free.fr>

show more ...

feat(auth): extend REGISTER_CRYPTO_LIB calls

Extend REGISTER_CRYPTO_LIB calls with NULL to allow for
the addition of the cryto_mod_finish() function.

Signed-off-by: Lauren Wehrmeister <lauren.wehrm

feat(auth): extend REGISTER_CRYPTO_LIB calls

Extend REGISTER_CRYPTO_LIB calls with NULL to allow for
the addition of the cryto_mod_finish() function.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: If41ed1be50e1d98b42b266c7905269f142bb67c7

show more ...

fix(s32g274a): reduce the uSDHC clock to 200MHz

Reduce the uSDHC clock to 200 MHz to ensure compatibility with the uSDHC
driver and alignment with the S32G274A data sheet.

Change-Id: Ic67c750561890

fix(s32g274a): reduce the uSDHC clock to 200MHz

Reduce the uSDHC clock to 200 MHz to ensure compatibility with the uSDHC
driver and alignment with the S32G274A data sheet.

Change-Id: Ic67c75056189075b1ba260e32426421e1e79a2e7
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...

feat(s32g274a): enable sdhc clock

The uSDHC module clock must be enabled to use the SD/eMMC storage from
where the BL2 is expected to load images for the next boot stages.

Change-Id: Ib1cc7d5dda7a4

feat(s32g274a): enable sdhc clock

The uSDHC module clock must be enabled to use the SD/eMMC storage from
where the BL2 is expected to load images for the next boot stages.

Change-Id: Ib1cc7d5dda7a4283a29716f5b3d776048bd5b7ba
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...