feat(s32g274ardb): add DDR clock source support

Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.

These utilities are required before
i

feat(s32g274ardb): add DDR clock source support

Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.

These utilities are required before
initializing the DDR subsystem.

Change-Id: I48cc984f73fca5cde1b81e9075488fd5bed420d6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(s32g274ardb): add mc_rgm_release_periph func

Add `mc_rgm_release_periph` function to
allow callers to specify which particular
peripheral should be released from reset.

Update the existing `mc

feat(s32g274ardb): add mc_rgm_release_periph func

Add `mc_rgm_release_periph` function to
allow callers to specify which particular
peripheral should be released from reset.

Update the existing `mc_rgm_release_part`
to make use of `mc_rgm_release_periph` function.

Change-Id: Ia2e049ac461f823379ddce34b1406eea0a0a86e9
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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Merge "fix(nxp-ddr): add missing macro define for Errata A009663" into integration

feat(imx9): add full system power control option

Add an optional build-time configuration to enable full system
shutdown and reset control through SCMI.

By default, only logical machine (cluster-le

feat(imx9): add full system power control option

Add an optional build-time configuration to enable full system
shutdown and reset control through SCMI.

By default, only logical machine (cluster-level) power-off and
reset are performed. When the SYS_PWR_FULL_CTRL option is set,
the PSCI implementation uses the full system power control
commands instead, allowing a complete system shutdown and reset.

Tested on iMX95 based modules.

Change-Id: I56b31f9b91def31784857f5a299c69f68db706a4
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>

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refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assist

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assisted coherency by default, so compiling empty
definitions is unnecessary.

This refactor removes those empty functions for Arm CSS platforms.

Change-Id: I102ead46960e9da2d8b968f60cbfd3e5e5da1096
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(scmi): add i.MX9 SCMI vendor CPU protocol

Add i.MX9 SCMI vendor specific CPU protocol

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.c

feat(scmi): add i.MX9 SCMI vendor CPU protocol

Add i.MX9 SCMI vendor specific CPU protocol

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Icc81bf9f4a32c08e4a3c358b1cf561ca4345a431

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fix(nxp-ddr): add missing macro define for Errata A009663

Even though platform support was added in commit 3b0de9182
("feat(plat/nxp/ls1043a): add ls1043a soc support"), the workaround
for errata A0

fix(nxp-ddr): add missing macro define for Errata A009663

Even though platform support was added in commit 3b0de9182
("feat(plat/nxp/ls1043a): add ls1043a soc support"), the workaround
for errata A009663 was not applied due to missing define.

Change-Id: I4f3669adf02dea487f89f81d2fc7344bb65f830d
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

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Merge "fix(nxp-crypto): restricts generating nxp_mkvb via ns-world" into integration

Merge changes Iea4c11de,Icae1fb08 into integration

* changes:
fix(lx2160): add DDRC missing DIMMs
fix(nxp): driver crypto caam

fix(nxp-crypto): restricts generating nxp_mkvb via ns-world

Master-key-verification-blob (MKVB) value generated on request from
the secure world, is same to the MKVB value generated on request from

fix(nxp-crypto): restricts generating nxp_mkvb via ns-world

Master-key-verification-blob (MKVB) value generated on request from
the secure world, is same to the MKVB value generated on request from
Normal world. Leading to the leak og MKVB to non-secure world.

Fix to prevent MKVB generation for requests originating from non-secure
world.
- For non-secure world, this SMC is return failure.

Additional fix for bound-check before continuing to generate the MKVB.

Change-Id: I9940b4dfe33289c2d57595a2a08acff29a12c974
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>

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fix(nxp): driver crypto caam

Fix based on code review. Then, it was checked with NXP Flexbuild and
their fix has been imported.

Change-Id: Icae1fb08b07bca5d4f6771e92b48d9e2071da0ee
Signed-off-by: V

fix(nxp): driver crypto caam

Fix based on code review. Then, it was checked with NXP Flexbuild and
their fix has been imported.

Change-Id: Icae1fb08b07bca5d4f6771e92b48d9e2071da0ee
Signed-off-by: Vincent Jardin <vjardin@free.fr>

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feat(auth): extend REGISTER_CRYPTO_LIB calls

Extend REGISTER_CRYPTO_LIB calls with NULL to allow for
the addition of the cryto_mod_finish() function.

Signed-off-by: Lauren Wehrmeister <lauren.wehrm

feat(auth): extend REGISTER_CRYPTO_LIB calls

Extend REGISTER_CRYPTO_LIB calls with NULL to allow for
the addition of the cryto_mod_finish() function.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: If41ed1be50e1d98b42b266c7905269f142bb67c7

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fix(s32g274a): reduce the uSDHC clock to 200MHz

Reduce the uSDHC clock to 200 MHz to ensure compatibility with the uSDHC
driver and alignment with the S32G274A data sheet.

Change-Id: Ic67c750561890

fix(s32g274a): reduce the uSDHC clock to 200MHz

Reduce the uSDHC clock to 200 MHz to ensure compatibility with the uSDHC
driver and alignment with the S32G274A data sheet.

Change-Id: Ic67c75056189075b1ba260e32426421e1e79a2e7
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): enable sdhc clock

The uSDHC module clock must be enabled to use the SD/eMMC storage from
where the BL2 is expected to load images for the next boot stages.

Change-Id: Ib1cc7d5dda7a4

feat(s32g274a): enable sdhc clock

The uSDHC module clock must be enabled to use the SD/eMMC storage from
where the BL2 is expected to load images for the next boot stages.

Change-Id: Ib1cc7d5dda7a4283a29716f5b3d776048bd5b7ba
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add clock modules for uSDHC

One of the uSDHC module's clock lines is attached to the CGM_MUX 14
divider, which is connected to PERIPH_DFS3. The other one is attached
to XBAR_DIV3.

feat(nxp-clk): add clock modules for uSDHC

One of the uSDHC module's clock lines is attached to the CGM_MUX 14
divider, which is connected to PERIPH_DFS3. The other one is attached
to XBAR_DIV3.

Change-Id: I23f468a3e5f7daa832c0841b55211a048284a7f0
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get MC_CGM divider's parent

The parent of the MC_CGM divider will always be the MC_CGM mux
identified based on s32cc_cgm_div.parent.

Change-Id: Ie13b16e0ee56f35d61374efbe158f166b9996

feat(nxp-clk): get MC_CGM divider's parent

The parent of the MC_CGM divider will always be the MC_CGM mux
identified based on s32cc_cgm_div.parent.

Change-Id: Ie13b16e0ee56f35d61374efbe158f166b99960b7
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get MC_CGM divider's rate

The MC_CGM divider's frequency is obtained based on the state of the
settings found in its registers. If the divider is disabled, the
intended rate (s32cc_cg

feat(nxp-clk): get MC_CGM divider's rate

The MC_CGM divider's frequency is obtained based on the state of the
settings found in its registers. If the divider is disabled, the
intended rate (s32cc_cgm_div.freq) will be returned.

Change-Id: I41698990952b530021de26eb51f74aca50176575
Co-developed-by: Florin Buica <florin.buica@nxp.com>
Signed-off-by: Florin Buica <florin.buica@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set MC_CGM divider's rate

The MC_CGM divider's frequency is saved as part of the object metadata.
No checks are performed on the requested frequency. It will be validated
during the e

feat(nxp-clk): set MC_CGM divider's rate

The MC_CGM divider's frequency is saved as part of the object metadata.
No checks are performed on the requested frequency. It will be validated
during the enablement process.

Change-Id: Ide9c8c64be16a66b66f129735cebfc4d1f1772c5
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): enable MC_CGM dividers

Add the enablement mechanism for the MC_CGM dividers. The division
factor is established by dividing the parent's rate by the rate of the
divider's output.

Cha

feat(nxp-clk): enable MC_CGM dividers

Add the enablement mechanism for the MC_CGM dividers. The division
factor is established by dividing the parent's rate by the rate of the
divider's output.

Change-Id: Iadb84f4f47531a67b0b1509b94e1f2b962631a77
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get parent for the fixed dividers

Fixed dividers contribute to the Linflex and QSPI clocks.

Change-Id: Idb4e6fe883e117b2bb9260b6eeb6e15d75ce887e
Signed-off-by: Ghennadi Procopciuc <g

feat(nxp-clk): get parent for the fixed dividers

Fixed dividers contribute to the Linflex and QSPI clocks.

Change-Id: Idb4e6fe883e117b2bb9260b6eeb6e15d75ce887e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set the rate for partition objects

Only the partition block link can set the frequency, while the other two
should not be able to because none of them participate in the clock
generat

feat(nxp-clk): set the rate for partition objects

Only the partition block link can set the frequency, while the other two
should not be able to because none of them participate in the clock
generation. In the first case, the request will be propagated to the
parent object of the partition link.

Change-Id: Ic237972008eb51c62e92f03f657698a8a1ca4b0e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add clock objects for CGM dividers

The CGM dividers are controllable dividers attached to a CGM mux. Its
divison factor can be controlled through the MC_CGM's registers.

Change-Id: I

feat(nxp-clk): add clock objects for CGM dividers

The CGM dividers are controllable dividers attached to a CGM mux. Its
divison factor can be controlled through the MC_CGM's registers.

Change-Id: Id2786a46c5a1d389ca32a4839c7158949aec3b0a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add base address for PERIPH_DFS

The PERIPH_DFS module is used to clock the SD and QSPI modules.

Change-Id: I440fd806d71acab641f0003a7f2a5ce720b469c6
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): add base address for PERIPH_DFS

The PERIPH_DFS module is used to clock the SD and QSPI modules.

Change-Id: I440fd806d71acab641f0003a7f2a5ce720b469c6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): restore pll output dividers rate

Reconfiguration of the PLL may be requested while some output dividers
are already enabled. To prevent setting a different frequency for these
enabled

feat(nxp-clk): restore pll output dividers rate

Reconfiguration of the PLL may be requested while some output dividers
are already enabled. To prevent setting a different frequency for these
enabled dividers, the driver will attempt to adjust the division factor
to achieve the initially requested rate.

Change-Id: I7800c05b2f21bbdeda243db865942b647983687d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get pll rate using get_module_rate

The DFS can use the get_module_rate instead of assuming its parent
object is a PLL. It also has the advantage that the frequency will be
returned ba

feat(nxp-clk): get pll rate using get_module_rate

The DFS can use the get_module_rate instead of assuming its parent
object is a PLL. It also has the advantage that the frequency will be
returned based on the hardware state of the PLL module.

Change-Id: I3a270cbc92622ae82606382df1301597dc29782a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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