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Searched refs:regs (Results 1 – 25 of 69) sorted by relevance

123

/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu541.c375 static void setup_vepu541_normal(Vepu541H264eRegSet *regs, RK_U32 is_vepu540) in setup_vepu541_normal() argument
381 regs->reg001.lkt_num = 0; in setup_vepu541_normal()
382 regs->reg001.rkvenc_cmd = 1; in setup_vepu541_normal()
383 regs->reg001.clk_gate_en = 1; in setup_vepu541_normal()
384 regs->reg001.resetn_hw_en = 0; in setup_vepu541_normal()
385 regs->reg001.enc_done_tmvp_en = 1; in setup_vepu541_normal()
388 regs->reg002.safe_clr = 0; in setup_vepu541_normal()
389 regs->reg002.force_clr = 0; in setup_vepu541_normal()
392 regs->reg003.lkt_addr = 0; in setup_vepu541_normal()
395 regs->reg004.enc_done_en = 1; in setup_vepu541_normal()
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H A Dhal_h264e_vepu580.c645 static void setup_vepu580_normal(HalVepu580RegSet *regs) in setup_vepu580_normal() argument
650 regs->reg_ctl.enc_strt.lkt_num = 0; in setup_vepu580_normal()
651 regs->reg_ctl.enc_strt.vepu_cmd = 1; in setup_vepu580_normal()
652 regs->reg_ctl.func_en.cke = 1; in setup_vepu580_normal()
653 regs->reg_ctl.func_en.resetn_hw_en = 1; in setup_vepu580_normal()
654 regs->reg_ctl.func_en.enc_done_tmvp_en = 1; in setup_vepu580_normal()
657 regs->reg_ctl.enc_clr.safe_clr = 0; in setup_vepu580_normal()
658 regs->reg_ctl.enc_clr.force_clr = 0; in setup_vepu580_normal()
661 regs->reg_ctl.int_en.enc_done_en = 1; in setup_vepu580_normal()
662 regs->reg_ctl.int_en.lkt_node_done_en = 1; in setup_vepu580_normal()
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H A Dhal_h264e_vepu540c.c378 static void setup_vepu540c_normal(HalVepu540cRegSet *regs) in setup_vepu540c_normal() argument
384 regs->reg_ctl.enc_strt.lkt_num = 0; in setup_vepu540c_normal()
385 regs->reg_ctl.enc_strt.vepu_cmd = 1; in setup_vepu540c_normal()
387 regs->reg_ctl.func_en.cke = 1; in setup_vepu540c_normal()
388 regs->reg_ctl.func_en.resetn_hw_en = 1; in setup_vepu540c_normal()
389 regs->reg_ctl.func_en.enc_done_tmvp_en = 1; in setup_vepu540c_normal()
392 regs->reg_ctl.enc_clr.safe_clr = 0; in setup_vepu540c_normal()
393 regs->reg_ctl.enc_clr.force_clr = 0; in setup_vepu540c_normal()
399 regs->reg_ctl.int_en.enc_done_en = 1; in setup_vepu540c_normal()
400 regs->reg_ctl.int_en.lkt_node_done_en = 1; in setup_vepu540c_normal()
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H A Dhal_h264e_vepu580_tune.c124 HalVepu580RegSet *regs = ctx->regs_set; in vepu580_h264e_tune_reg_patch() local
139 memcpy(&regs->reg_rc_klut.klut_wgt0, src, CHROMA_KLUT_TAB_SIZE); in vepu580_h264e_tune_reg_patch()
142 regs->reg_rc_klut.md_sad_thd.md_sad_thd0 = 4; in vepu580_h264e_tune_reg_patch()
143 regs->reg_rc_klut.md_sad_thd.md_sad_thd1 = 9; in vepu580_h264e_tune_reg_patch()
144 regs->reg_rc_klut.md_sad_thd.md_sad_thd2 = 15; in vepu580_h264e_tune_reg_patch()
145 regs->reg_rc_klut.madi_thd.madi_thd0 = 4; in vepu580_h264e_tune_reg_patch()
146 regs->reg_rc_klut.madi_thd.madi_thd1 = 9; in vepu580_h264e_tune_reg_patch()
147 regs->reg_rc_klut.madi_thd.madi_thd2 = 15; in vepu580_h264e_tune_reg_patch()
150 regs->reg_s3.lvl16_intra_UL_CST_THD.lvl16_intra_ul_cst_thld = 2501; in vepu580_h264e_tune_reg_patch()
151 regs->reg_s3.RDO_QUANT.quant_f_bias_P = 341; in vepu580_h264e_tune_reg_patch()
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/rockchip-linux_mpp/mpp/hal/vpu/vp8e/
H A Dhal_vp8e_vepu2_v2.c42 Vp8eVepu2Reg_t *regs = (Vp8eVepu2Reg_t *)ctx->regs; in vp8e_vpu_frame_start() local
44 memset(regs, 0, sizeof(Vp8eVepu2Reg_t)); in vp8e_vpu_frame_start()
46 regs->sw109.val = hw_cfg->irq_disable ? (regs->sw109.val | 0x0100) : in vp8e_vpu_frame_start()
47 (regs->sw109.val & 0xfeff); in vp8e_vpu_frame_start()
50 regs->sw54.val = 0x1000; in vp8e_vpu_frame_start()
53 regs->sw105.val = 0xfc000000; in vp8e_vpu_frame_start()
55 regs->sw105.val = 0xfc000000; in vp8e_vpu_frame_start()
57 regs->sw105.val = 0x3c000000; in vp8e_vpu_frame_start()
60 regs->sw77.base_stream = hw_cfg->output_strm_base; in vp8e_vpu_frame_start()
62 regs->sw78.base_control = hw_cfg->size_tbl_base; in vp8e_vpu_frame_start()
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H A Dhal_vp8e_vepu1_v2.c41 Vp8eVepu1Reg_t *regs = (Vp8eVepu1Reg_t *) ctx->regs; in vp8e_vpu_frame_start() local
43 memset(regs, 0, sizeof(Vp8eVepu1Reg_t)); in vp8e_vpu_frame_start()
45 regs->sw1.val = hw_cfg->irq_disable ? (regs->sw1.val | 0x02) : in vp8e_vpu_frame_start()
46 (regs->sw1.val & 0xfffffffd); in vp8e_vpu_frame_start()
50 regs->sw2.val = 0xd00f; in vp8e_vpu_frame_start()
53 regs->sw2.val = 0xd00f; in vp8e_vpu_frame_start()
55 regs->sw2.val = 0x900e; in vp8e_vpu_frame_start()
57 regs->sw5.base_stream = hw_cfg->output_strm_base; in vp8e_vpu_frame_start()
60 regs->sw6.base_control = hw_cfg->size_tbl_base; in vp8e_vpu_frame_start()
61 regs->sw14.nal_size_write = (hw_cfg->size_tbl_base != 0); in vp8e_vpu_frame_start()
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/rockchip-linux_mpp/mpp/hal/vpu/mpg4d/
H A Dhal_m4vd_vdpu1.c37 M4vdVdpu1Regs_t *regs = ctx->regs; in vdpu1_mpg4d_setup_regs_by_syntax() local
83 regs->SwReg04.sw_pic_mb_width = (pp->vop_width + 15) >> 4; in vdpu1_mpg4d_setup_regs_by_syntax()
84 regs->SwReg04.sw_pic_mb_hight_p = (pp->vop_height + 15) >> 4; in vdpu1_mpg4d_setup_regs_by_syntax()
87 regs->SwReg04.sw_mb_width_off = pp->vop_width & 0xf; in vdpu1_mpg4d_setup_regs_by_syntax()
88 regs->SwReg04.sw_mb_height_off = pp->vop_height & 0xf; in vdpu1_mpg4d_setup_regs_by_syntax()
90 regs->SwReg04.sw_mb_width_off = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
91 regs->SwReg04.sw_mb_height_off = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
94 regs->SwReg03.sw_dec_mode = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
101 regs->SwReg18.sw_alt_scan_flag_e = pp->alternate_vertical_scan_flag; in vdpu1_mpg4d_setup_regs_by_syntax()
102 regs->SwReg48.sw_startmb_x = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
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H A Dhal_m4vd_vdpu2.c37 M4vdVdpu2Regs_t *regs = ctx->regs; in vdpu2_mpg4d_setup_regs_by_syntax() local
83 regs->reg120.sw_pic_mb_width = (pp->vop_width + 15) >> 4; in vdpu2_mpg4d_setup_regs_by_syntax()
84 regs->reg120.sw_pic_mb_hight_p = (pp->vop_height + 15) >> 4; in vdpu2_mpg4d_setup_regs_by_syntax()
86 regs->reg120.sw_mb_width_off = pp->vop_width & 0xf; in vdpu2_mpg4d_setup_regs_by_syntax()
87 regs->reg120.sw_mb_height_off = pp->vop_height & 0xf; in vdpu2_mpg4d_setup_regs_by_syntax()
89 regs->reg120.sw_mb_width_off = 0; in vdpu2_mpg4d_setup_regs_by_syntax()
90 regs->reg120.sw_mb_height_off = 0; in vdpu2_mpg4d_setup_regs_by_syntax()
92 regs->reg53_dec_mode = 1; in vdpu2_mpg4d_setup_regs_by_syntax()
99 regs->reg136.sw_alt_scan_flag_e = pp->alternate_vertical_scan_flag; in vdpu2_mpg4d_setup_regs_by_syntax()
100 regs->reg52_error_concealment.sw_xdim_mbst = 0; in vdpu2_mpg4d_setup_regs_by_syntax()
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/rockchip-linux_mpp/mpp/hal/vpu/h263d/
H A Dhal_h263d_vdpu2.c34 Vpu2H263dRegSet_t *regs = (Vpu2H263dRegSet_t*)ctx->regs; in vpu2_h263d_setup_regs_by_syntax() local
61 regs->reg120.sw_pic_mb_width = (pp->vop_width + 15) >> 4; in vpu2_h263d_setup_regs_by_syntax()
62 regs->reg120.sw_pic_mb_hight_p = (pp->vop_height + 15) >> 4; in vpu2_h263d_setup_regs_by_syntax()
63 regs->reg120.sw_mb_width_off = pp->vop_width & 0xf; in vpu2_h263d_setup_regs_by_syntax()
64 regs->reg120.sw_mb_height_off = pp->vop_height & 0xf; in vpu2_h263d_setup_regs_by_syntax()
66 regs->reg53_dec_mode = 2; in vpu2_h263d_setup_regs_by_syntax()
67 regs->reg50_dec_ctrl.sw_filtering_dis = 1; in vpu2_h263d_setup_regs_by_syntax()
68 regs->reg136.sw_rounding = 0; in vpu2_h263d_setup_regs_by_syntax()
69 regs->reg51_stream_info.sw_init_qp = pp->vop_quant; in vpu2_h263d_setup_regs_by_syntax()
70 regs->reg122.sw_sync_markers_en = 1; in vpu2_h263d_setup_regs_by_syntax()
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H A Dhal_h263d_vdpu1.c34 Vpu1H263dRegSet_t *regs = (Vpu1H263dRegSet_t*)ctx->regs; in vpu1_h263d_setup_regs_by_syntax() local
61 regs->SwReg04.sw_pic_mb_width = (pp->vop_width + 15) >> 4; in vpu1_h263d_setup_regs_by_syntax()
62 regs->SwReg04.sw_pic_mb_hight_p = (pp->vop_height + 15) >> 4; in vpu1_h263d_setup_regs_by_syntax()
63 regs->SwReg04.sw_mb_width_off = pp->vop_width & 0xf; in vpu1_h263d_setup_regs_by_syntax()
64 regs->SwReg04.sw_mb_height_off = pp->vop_height & 0xf; in vpu1_h263d_setup_regs_by_syntax()
66 regs->SwReg03.sw_dec_mode = 2; in vpu1_h263d_setup_regs_by_syntax()
67 regs->SwReg03.sw_filtering_dis = 1; in vpu1_h263d_setup_regs_by_syntax()
68 regs->SwReg18.sw_h263_vc1_rc = 0; in vpu1_h263d_setup_regs_by_syntax()
69 regs->SwReg06.sw_init_qp = pp->vop_quant; in vpu1_h263d_setup_regs_by_syntax()
70 regs->SwReg05.sw_sync_markers_e = 1; in vpu1_h263d_setup_regs_by_syntax()
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/rockchip-linux_mpp/mpp/hal/vpu/av1d/
H A Dhal_av1d_vdpu.c66 VdpuAv1dRegSet *regs; member
103 VdpuAv1dRegSet *regs; member
144 reg_ctx->reg_buf[i].regs = mpp_calloc(VdpuAv1dRegSet, 1); in hal_av1d_alloc_res()
145 memset(reg_ctx->reg_buf[i].regs, 0, sizeof(VdpuAv1dRegSet)); in hal_av1d_alloc_res()
149 reg_ctx->regs = reg_ctx->reg_buf[0].regs; in hal_av1d_alloc_res()
240 MPP_FREE(reg_ctx->reg_buf[i].regs); in hal_av1d_release_res()
290 static void set_ref_width(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) in set_ref_width() argument
293 regs->swreg33.sw_ref0_width = val; in set_ref_width()
295 regs->swreg34.sw_ref1_width = val; in set_ref_width()
297 regs->swreg35.sw_ref2_width = val; in set_ref_width()
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/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu541.c74 void *regs; member
510 static void vepu541_h265_set_l2_regs(H265eV541HalContext *ctx, H265eV54xL2RegSet *regs) in vepu541_h265_set_l2_regs() argument
515 memcpy(&regs->lvl32_intra_CST_THD0, lvl32_intra_cst_thd, sizeof(lvl32_intra_cst_thd)); in vepu541_h265_set_l2_regs()
516 memcpy(&regs->lvl16_intra_CST_THD0, lvl16_intra_cst_thd, sizeof(lvl16_intra_cst_thd)); in vepu541_h265_set_l2_regs()
517 memcpy(&regs->lvl32_intra_CST_WGT0, lvl32_intra_cst_wgt, sizeof(lvl32_intra_cst_wgt)); in vepu541_h265_set_l2_regs()
518 memcpy(&regs->lvl16_intra_CST_WGT0, lvl16_intra_cst_wgt, sizeof(lvl16_intra_cst_wgt)); in vepu541_h265_set_l2_regs()
519 regs->rdo_quant.quant_f_bias_I = 171; in vepu541_h265_set_l2_regs()
520 regs->rdo_quant.quant_f_bias_P = 85; in vepu541_h265_set_l2_regs()
521 memcpy(&regs->atr_thd0, atr_thd, sizeof(atr_thd)); in vepu541_h265_set_l2_regs()
522 memcpy(&regs->lvl16_atr_wgt, lvl16_4_atr_wgt, sizeof(lvl16_4_atr_wgt)); in vepu541_h265_set_l2_regs()
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H A Dhal_h265e_vepu540c.c72 void *regs; member
423 static void vepu540c_h265_global_cfg_set(H265eV540cHalContext *ctx, H265eV540cRegSet *regs) in vepu540c_h265_global_cfg_set() argument
427 hevc_vepu540c_rc_roi *rc_regs = &regs->reg_rc_roi; in vepu540c_h265_global_cfg_set()
428 hevc_vepu540c_wgt *reg_wgt = &regs->reg_wgt; in vepu540c_h265_global_cfg_set()
429 vepu540c_rdo_cfg *reg_rdo = &regs->reg_rdo; in vepu540c_h265_global_cfg_set()
456 regs->reg_wgt.me_sqi_cfg.cime_pmv_num = 1; in vepu540c_h265_global_cfg_set()
457 regs->reg_wgt.me_sqi_cfg.cime_fuse = 1; in vepu540c_h265_global_cfg_set()
458 regs->reg_wgt.me_sqi_cfg.itp_mode = 0; in vepu540c_h265_global_cfg_set()
459 regs->reg_wgt.me_sqi_cfg.move_lambda = 2; in vepu540c_h265_global_cfg_set()
460 regs->reg_wgt.me_sqi_cfg.rime_lvl_mrg = 0; in vepu540c_h265_global_cfg_set()
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/rockchip-linux_mpp/mpp/hal/vpu/vp8d/
H A Dhal_vp8d_vdpu2.c54 if (NULL == ctx->regs) { in hal_vp8d_vdpu2_init()
55 ctx->regs = mpp_calloc_size(void, sizeof(VP8DRegSet_t)); in hal_vp8d_vdpu2_init()
56 if (NULL == ctx->regs) { in hal_vp8d_vdpu2_init()
96 if (ctx->regs) { in hal_vp8d_vdpu2_init()
97 mpp_free(ctx->regs); in hal_vp8d_vdpu2_init()
98 ctx->regs = NULL; in hal_vp8d_vdpu2_init()
152 if (ctx->regs) { in hal_vp8d_vdpu2_deinit()
153 mpp_free(ctx->regs); in hal_vp8d_vdpu2_deinit()
154 ctx->regs = NULL; in hal_vp8d_vdpu2_deinit()
164 VP8DRegSet_t *reg = (VP8DRegSet_t *)ctx->regs; in hal_vp8_init_hwcfg()
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H A Dhal_vp8d_vdpu1.c53 if (NULL == ctx->regs) { in hal_vp8d_vdpu1_init()
54 ctx->regs = mpp_calloc_size(void, sizeof(VP8DRegSet_t)); in hal_vp8d_vdpu1_init()
55 if (NULL == ctx->regs) { in hal_vp8d_vdpu1_init()
94 if (ctx->regs) { in hal_vp8d_vdpu1_init()
95 mpp_free(ctx->regs); in hal_vp8d_vdpu1_init()
96 ctx->regs = NULL; in hal_vp8d_vdpu1_init()
150 if (ctx->regs) { in hal_vp8d_vdpu1_deinit()
151 mpp_free(ctx->regs); in hal_vp8d_vdpu1_deinit()
152 ctx->regs = NULL; in hal_vp8d_vdpu1_deinit()
162 VP8DRegSet_t *reg = (VP8DRegSet_t *)ctx->regs; in hal_vp8_init_hwcfg()
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/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu540c_common.c161 Vepu540cJpegReg *regs = (Vepu540cJpegReg *)cfg->jpeg_reg_base; in vepu540c_set_jpeg_reg() local
170 regs->reg0264_adr_src0 = mpp_buffer_get_fd(task->input); in vepu540c_set_jpeg_reg()
171 regs->reg0265_adr_src1 = regs->reg0264_adr_src0; in vepu540c_set_jpeg_reg()
172 regs->reg0266_adr_src2 = regs->reg0264_adr_src0; in vepu540c_set_jpeg_reg()
176 regs->reg0256_adr_bsbt = mpp_buffer_get_fd(task->output); in vepu540c_set_jpeg_reg()
177 regs->reg0257_adr_bsbb = regs->reg0256_adr_bsbt; in vepu540c_set_jpeg_reg()
178 regs->reg0258_adr_bsbs = regs->reg0256_adr_bsbt; in vepu540c_set_jpeg_reg()
179 regs->reg0259_adr_bsbr = regs->reg0256_adr_bsbt; in vepu540c_set_jpeg_reg()
184 regs->reg0272_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in vepu540c_set_jpeg_reg()
185 regs->reg0273_src_fill.pic_wfill = (syn->width & 0x7) in vepu540c_set_jpeg_reg()
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H A Dvepu580_common.c13 Vepu580OsdReg *regs = (Vepu580OsdReg *)cfg->reg_base; in vepu580_set_osd() local
33 memcpy(regs->plt_data, plt_cfg->plt, sizeof(MppEncOSDPlt)); in vepu580_set_osd()
34 regs->reg3074.osd_plt_cks = 1; in vepu580_set_osd()
35 regs->reg3074.osd_plt_typ = VEPU5xx_OSD_PLT_TYPE_USERDEF; in vepu580_set_osd()
37 regs->reg3074.osd_plt_cks = 0; in vepu580_set_osd()
38 regs->reg3074.osd_plt_typ = VEPU5xx_OSD_PLT_TYPE_DEFAULT; in vepu580_set_osd()
41 regs->reg3074.osd_e = 0; in vepu580_set_osd()
42 regs->reg3072.osd_lu_inv_en = 0; in vepu580_set_osd()
43 regs->reg3072.osd_ch_inv_en = 0; in vepu580_set_osd()
44 regs->reg3072.osd_lu_inv_msk = 0; in vepu580_set_osd()
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H A Dvepu541_common.c248 Vepu541OsdReg *regs = (Vepu541OsdReg *)(cfg->reg_base + (size_t)VEPU541_OSD_CFG_OFFSET); in vepu541_set_osd() local
275 regs->reg112.osd_plt_cks = 1; in vepu541_set_osd()
276 regs->reg112.osd_plt_typ = VEPU5xx_OSD_PLT_TYPE_USERDEF; in vepu541_set_osd()
278 regs->reg112.osd_plt_cks = 0; in vepu541_set_osd()
279 regs->reg112.osd_plt_typ = VEPU5xx_OSD_PLT_TYPE_DEFAULT; in vepu541_set_osd()
282 regs->reg112.osd_e = 0; in vepu541_set_osd()
283 regs->reg112.osd_inv_e = 0; in vepu541_set_osd()
291 regs->reg112.osd_e |= tmp->enable << i; in vepu541_set_osd()
292 regs->reg112.osd_inv_e |= tmp->inverse << i; in vepu541_set_osd()
295 Vepu541OsdPos *pos = &regs->osd_pos[i]; in vepu541_set_osd()
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/rockchip-linux_mpp/mpp/hal/vpu/jpegd/
H A Dhal_jpegd_rkv.c242 if (ctx->regs == NULL) { in hal_jpegd_rkv_init()
243 ctx->regs = mpp_calloc_size(void, sizeof(JpegRegSet)); in hal_jpegd_rkv_init()
244 if (ctx->regs == NULL) { in hal_jpegd_rkv_init()
277 JpegRegSet *regs = (JpegRegSet *)ctx->regs; in setup_output_fmt() local
285 regs->reg2_sys.scaledown_mode = SCALEDOWN_HALF; in setup_output_fmt()
287 regs->reg2_sys.scaledown_mode = SCALEDOWN_QUARTER; in setup_output_fmt()
289 regs->reg2_sys.scaledown_mode = SCALEDOWN_ONE_EIGHTS; in setup_output_fmt()
291 regs->reg2_sys.scaledown_mode = SCALEDOWN_DISABLE; in setup_output_fmt()
299 regs->reg2_sys.yuv_out_format = YUV_OUT_FMT_2_NV12; in setup_output_fmt()
305 regs->reg2_sys.yuv_out_format = YUV_OUT_FMT_2_YUYV; in setup_output_fmt()
[all …]
/rockchip-linux_mpp/mpp/hal/rkenc/jpege/
H A Dhal_jpege_vepu511.c33 void *regs; member
73 ctx->regs = mpp_calloc(JpegV511RegSet, 1); in hal_jpege_vepu511_init()
101 MPP_FREE(ctx->regs); in hal_jpege_vepu511_deinit()
197 Vepu511JpegReg *regs = (Vepu511JpegReg *)cfg->jpeg_reg_base; in vepu511_set_jpeg_reg() local
206 regs->adr_src0 = mpp_buffer_get_fd(task->input); in vepu511_set_jpeg_reg()
207 regs->adr_src1 = regs->adr_src0; in vepu511_set_jpeg_reg()
208 regs->adr_src2 = regs->adr_src0; in vepu511_set_jpeg_reg()
212 regs->adr_bsbt = mpp_buffer_get_fd(task->output); in vepu511_set_jpeg_reg()
213 regs->adr_bsbb = regs->adr_bsbt; in vepu511_set_jpeg_reg()
214 regs->adr_bsbs = regs->adr_bsbt; in vepu511_set_jpeg_reg()
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/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu34x.c65 #define SET_REF_INFO(regs, index, field, value)\ argument
68 case 0: regs.reg99.ref0_##field = value; break;\
69 case 1: regs.reg99.ref1_##field = value; break;\
70 case 2: regs.reg99.ref2_##field = value; break;\
71 case 3: regs.reg99.ref3_##field = value; break;\
72 case 4: regs.reg100.ref4_##field = value; break;\
73 case 5: regs.reg100.ref5_##field = value; break;\
74 case 6: regs.reg100.ref6_##field = value; break;\
75 case 7: regs.reg100.ref7_##field = value; break;\
76 case 8: regs.reg101.ref8_##field = value; break;\
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H A Dhal_h264d_vdpu382.c67 #define SET_REF_INFO(regs, index, field, value)\ argument
70 case 0: regs.reg99.ref0_##field = value; break;\
71 case 1: regs.reg99.ref1_##field = value; break;\
72 case 2: regs.reg99.ref2_##field = value; break;\
73 case 3: regs.reg99.ref3_##field = value; break;\
74 case 4: regs.reg100.ref4_##field = value; break;\
75 case 5: regs.reg100.ref5_##field = value; break;\
76 case 6: regs.reg100.ref6_##field = value; break;\
77 case 7: regs.reg100.ref7_##field = value; break;\
78 case 8: regs.reg101.ref8_##field = value; break;\
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H A Dhal_h264d_vdpu384a.c41 #define SET_REF_INFO(regs, index, field, value)\ argument
44 case 0: regs.reg99.ref0_##field = value; break;\
45 case 1: regs.reg99.ref1_##field = value; break;\
46 case 2: regs.reg99.ref2_##field = value; break;\
47 case 3: regs.reg99.ref3_##field = value; break;\
48 case 4: regs.reg100.ref4_##field = value; break;\
49 case 5: regs.reg100.ref5_##field = value; break;\
50 case 6: regs.reg100.ref6_##field = value; break;\
51 case 7: regs.reg100.ref7_##field = value; break;\
52 case 8: regs.reg101.ref8_##field = value; break;\
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/rockchip-linux_mpp/mpp/hal/rkdec/av1d/
H A Dhal_av1d_vdpu383.c51 #define SET_REF_HOR_VIRSTRIDE(regs, ref_index, value)\ argument
54 case 0: regs.reg83_ref0_hor_virstride = value; break;\
55 case 1: regs.reg86_ref1_hor_virstride = value; break;\
56 case 2: regs.reg89_ref2_hor_virstride = value; break;\
57 case 3: regs.reg92_ref3_hor_virstride = value; break;\
58 case 4: regs.reg95_ref4_hor_virstride = value; break;\
59 case 5: regs.reg98_ref5_hor_virstride = value; break;\
60 case 6: regs.reg101_ref6_hor_virstride = value; break;\
61 case 7: regs.reg104_ref7_hor_virstride = value; break;\
65 #define SET_REF_RASTER_UV_HOR_VIRSTRIDE(regs, ref_index, value)\ argument
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/rockchip-linux_mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_vdpu383.c48 Vdpu383Avs2dRegSet *regs; member
57 Vdpu383Avs2dRegSet *regs; member
236 static void init_ctrl_regs(Vdpu383Avs2dRegSet *regs) in init_ctrl_regs() argument
238 Vdpu383CtrlReg *ctrl_regs = &regs->ctrl_regs; in init_ctrl_regs()
320 static void hal_avs2d_rcb_info_update(void *hal, Vdpu383Avs2dRegSet *regs) in hal_avs2d_rcb_info_update() argument
330 (void) regs; in hal_avs2d_rcb_info_update()
351 static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu383Avs2dRegSet *regs, HalTaskInfo *task) in fill_registers() argument
386 regs->ctrl_regs.reg9.fbc_e = 1; in fill_registers()
387 regs->avs2d_paras.reg68_hor_virstride = fbc_hdr_stride / 64; in fill_registers()
388 fbd_offset = regs->avs2d_paras.reg68_hor_virstride * MPP_ALIGN(ver_virstride, 64) * 4; in fill_registers()
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