Lines Matching refs:regs
41 #define SET_REF_INFO(regs, index, field, value)\ argument
44 case 0: regs.reg99.ref0_##field = value; break;\
45 case 1: regs.reg99.ref1_##field = value; break;\
46 case 2: regs.reg99.ref2_##field = value; break;\
47 case 3: regs.reg99.ref3_##field = value; break;\
48 case 4: regs.reg100.ref4_##field = value; break;\
49 case 5: regs.reg100.ref5_##field = value; break;\
50 case 6: regs.reg100.ref6_##field = value; break;\
51 case 7: regs.reg100.ref7_##field = value; break;\
52 case 8: regs.reg101.ref8_##field = value; break;\
53 case 9: regs.reg101.ref9_##field = value; break;\
54 case 10: regs.reg101.ref10_##field = value; break;\
55 case 11: regs.reg101.ref11_##field = value; break;\
56 case 12: regs.reg102.ref12_##field = value; break;\
57 case 13: regs.reg102.ref13_##field = value; break;\
58 case 14: regs.reg102.ref14_##field = value; break;\
59 case 15: regs.reg102.ref15_##field = value; break;\
67 Vdpu384aH264dRegSet *regs; member
97 Vdpu384aH264dRegSet *regs; member
351 static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu384aH264dRegSet *regs, HalTaskInfo *task) in set_registers() argument
359 regs->h264d_paras.reg66_stream_len = p_hal->strm_len; in set_registers()
381 regs->ctrl_regs.reg9.dpb_data_sel = 0; in set_registers()
382 regs->ctrl_regs.reg9.dpb_output_dis = 0; in set_registers()
383 regs->ctrl_regs.reg9.pp_m_output_mode = 0; in set_registers()
385 regs->h264d_paras.reg68_dpb_hor_virstride = fbc_hdr_stride / 64; in set_registers()
386 regs->h264d_addrs.reg193_dpb_fbc64x4_payload_offset = fbd_offset; in set_registers()
387 … regs->h264d_paras.reg80_error_ref_hor_virstride = regs->h264d_paras.reg68_dpb_hor_virstride; in set_registers()
389 regs->ctrl_regs.reg9.dpb_data_sel = 1; in set_registers()
390 regs->ctrl_regs.reg9.dpb_output_dis = 1; in set_registers()
391 regs->ctrl_regs.reg9.pp_m_output_mode = 2; in set_registers()
393 regs->h264d_paras.reg77_pp_m_hor_stride = hor_virstride * 6 / 16; in set_registers()
394 regs->h264d_paras.reg79_pp_m_y_virstride = (y_virstride + uv_virstride) / 16; in set_registers()
395 … regs->h264d_paras.reg80_error_ref_hor_virstride = regs->h264d_paras.reg77_pp_m_hor_stride; in set_registers()
397 regs->ctrl_regs.reg9.dpb_data_sel = 1; in set_registers()
398 regs->ctrl_regs.reg9.dpb_output_dis = 1; in set_registers()
399 regs->ctrl_regs.reg9.pp_m_output_mode = 1; in set_registers()
401 regs->h264d_paras.reg77_pp_m_hor_stride = hor_virstride / 16; in set_registers()
402 regs->h264d_paras.reg78_pp_m_uv_hor_stride = hor_virstride / 16; in set_registers()
403 regs->h264d_paras.reg79_pp_m_y_virstride = y_virstride / 16; in set_registers()
404 … regs->h264d_paras.reg80_error_ref_hor_virstride = regs->h264d_paras.reg77_pp_m_hor_stride; in set_registers()
406 …regs->h264d_paras.reg81_error_ref_raster_uv_hor_virstride = regs->h264d_paras.reg78_pp_m_uv_hor_st… in set_registers()
407 regs->h264d_paras.reg82_error_ref_virstride = regs->h264d_paras.reg79_pp_m_y_virstride; in set_registers()
419 regs->common_addr.reg135_pp_m_decout_base = fd; in set_registers()
420 regs->h264d_addrs.reg192_dpb_payload64x4_st_cur_base = fd; in set_registers()
424 regs->h264d_addrs.reg216_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]); in set_registers()
425 regs->h264d_addrs.reg169_error_ref_base = fd; in set_registers()
456 regs->h264d_addrs.reg169_error_ref_base = mpp_buffer_get_fd(mbuffer); in set_registers()
460 regs->h264d_addrs.reg170_185_ref_base[i] = fd; in set_registers()
461 regs->h264d_addrs.reg195_210_payload_st_ref_base[i] = fd; in set_registers()
463 regs->h264d_addrs.reg217_232_colmv_ref_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]); in set_registers()
478 regs->h264d_addrs.reg170_185_ref_base[15] = fd; in set_registers()
479 regs->h264d_addrs.reg195_210_payload_st_ref_base[15] = fd; in set_registers()
481 regs->h264d_addrs.reg217_232_colmv_ref_base[15] = mpp_buffer_get_fd(mv_buf->buf[0]); in set_registers()
487 regs->common_addr.reg128_strm_base = mpp_buffer_get_fd(mbuffer); in set_registers()
488 regs->common_addr.reg129_stream_buf_st_base = mpp_buffer_get_fd(mbuffer); in set_registers()
489 regs->common_addr.reg130_stream_buf_end_base = mpp_buffer_get_fd(mbuffer); in set_registers()
517 regs->common_addr.reg133_scale_down_base = fd; in set_registers()
523 regs->common_addr.reg135_pp_m_decout_base = fd; in set_registers()
524 regs->h264d_addrs.reg192_dpb_payload64x4_st_cur_base = fd; in set_registers()
525 regs->h264d_addrs.reg169_error_ref_base = fd; in set_registers()
526 … vdpu384a_setup_down_scale(mframe, p_hal->dev, ®s->ctrl_regs, (void*)®s->h264d_paras); in set_registers()
529 regs->common_addr.reg133_scale_down_base = fd; in set_registers()
530 … vdpu384a_setup_down_scale(mframe, p_hal->dev, ®s->ctrl_regs, (void*)®s->h264d_paras); in set_registers()
534 regs->ctrl_regs.reg9.scale_down_en = 0; in set_registers()
542 static MPP_RET init_ctrl_regs(Vdpu384aH264dRegSet *regs) in init_ctrl_regs() argument
544 Vdpu384aCtrlReg *ctrl_regs = ®s->ctrl_regs; in init_ctrl_regs()
607 reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu384aH264dRegSet, 1); in vdpu384a_h264d_init()
608 init_ctrl_regs(reg_ctx->reg_buf[i].regs); in vdpu384a_h264d_init()
616 reg_ctx->regs = reg_ctx->reg_buf[0].regs; in vdpu384a_h264d_init()
652 MPP_FREE(reg_ctx->reg_buf[i].regs); in vdpu384a_h264d_deinit()
771 Vdpu384aH264dRegSet *regs = ctx->regs; in vdpu384a_h264d_gen_regs() local
815 regs = ctx->reg_buf[i].regs; in vdpu384a_h264d_gen_regs()
839 set_registers(p_hal, regs, task); in vdpu384a_h264d_gen_regs()
844 regs->common_addr.reg131_gbl_base = ctx->bufs_fd; in vdpu384a_h264d_gen_regs()
845 regs->h264d_paras.reg67_global_len = VDPU384A_SPSPPS_SIZE / 16; // 128 bit as unit in vdpu384a_h264d_gen_regs()
850 regs->common_addr.reg132_scanlist_addr = ctx->bufs_fd; in vdpu384a_h264d_gen_regs()
853 regs->common_addr.reg132_scanlist_addr = 0; in vdpu384a_h264d_gen_regs()
857 vdpu384a_setup_rcb(®s->common_addr, p_hal->dev, p_hal->fast_mode ? in vdpu384a_h264d_gen_regs()
860 vdpu384a_setup_statistic(®s->ctrl_regs); in vdpu384a_h264d_gen_regs()
879 Vdpu384aH264dRegSet *regs = p_hal->fast_mode ? in vdpu384a_h264d_start() local
880 reg_ctx->reg_buf[task->dec.reg_index].regs : in vdpu384a_h264d_start()
881 reg_ctx->regs; in vdpu384a_h264d_start()
888 wr_cfg.reg = ®s->ctrl_regs; in vdpu384a_h264d_start()
889 wr_cfg.size = sizeof(regs->ctrl_regs); in vdpu384a_h264d_start()
897 wr_cfg.reg = ®s->common_addr; in vdpu384a_h264d_start()
898 wr_cfg.size = sizeof(regs->common_addr); in vdpu384a_h264d_start()
906 wr_cfg.reg = ®s->h264d_paras; in vdpu384a_h264d_start()
907 wr_cfg.size = sizeof(regs->h264d_paras); in vdpu384a_h264d_start()
915 wr_cfg.reg = ®s->h264d_addrs; in vdpu384a_h264d_start()
916 wr_cfg.size = sizeof(regs->h264d_addrs); in vdpu384a_h264d_start()
924 rd_cfg.reg = ®s->ctrl_regs.reg15; in vdpu384a_h264d_start()
925 rd_cfg.size = sizeof(regs->ctrl_regs.reg15); in vdpu384a_h264d_start()
956 reg_ctx->reg_buf[task->dec.reg_index].regs : in vdpu384a_h264d_wait()
957 reg_ctx->regs; in vdpu384a_h264d_wait()
973 param.regs = (RK_U32 *)p_regs; in vdpu384a_h264d_wait()