Lines Matching refs:regs
37 M4vdVdpu1Regs_t *regs = ctx->regs; in vdpu1_mpg4d_setup_regs_by_syntax() local
83 regs->SwReg04.sw_pic_mb_width = (pp->vop_width + 15) >> 4; in vdpu1_mpg4d_setup_regs_by_syntax()
84 regs->SwReg04.sw_pic_mb_hight_p = (pp->vop_height + 15) >> 4; in vdpu1_mpg4d_setup_regs_by_syntax()
87 regs->SwReg04.sw_mb_width_off = pp->vop_width & 0xf; in vdpu1_mpg4d_setup_regs_by_syntax()
88 regs->SwReg04.sw_mb_height_off = pp->vop_height & 0xf; in vdpu1_mpg4d_setup_regs_by_syntax()
90 regs->SwReg04.sw_mb_width_off = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
91 regs->SwReg04.sw_mb_height_off = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
94 regs->SwReg03.sw_dec_mode = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
101 regs->SwReg18.sw_alt_scan_flag_e = pp->alternate_vertical_scan_flag; in vdpu1_mpg4d_setup_regs_by_syntax()
102 regs->SwReg48.sw_startmb_x = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
103 regs->SwReg48.sw_startmb_y = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
104 regs->SwReg03.sw_filtering_dis = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
105 regs->SwReg18.sw_mpeg4_vc1_rc = pp->vop_rounding_type; in vdpu1_mpg4d_setup_regs_by_syntax()
106 regs->SwReg05.sw_intradc_vlc_thr = pp->intra_dc_vlc_thr; in vdpu1_mpg4d_setup_regs_by_syntax()
107 regs->SwReg06.sw_init_qp = pp->vop_quant; in vdpu1_mpg4d_setup_regs_by_syntax()
108 regs->SwReg05.sw_sync_markers_e = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
117 RK_U32 val = regs->SwReg12.sw_rlc_vlc_base; in vdpu1_mpg4d_setup_regs_by_syntax()
123 regs->SwReg12.sw_rlc_vlc_base = val; in vdpu1_mpg4d_setup_regs_by_syntax()
126 regs->SwReg05.sw_strm_start_bit = start_bit_offset; in vdpu1_mpg4d_setup_regs_by_syntax()
127 regs->SwReg06.sw_stream_len = left_bytes; in vdpu1_mpg4d_setup_regs_by_syntax()
129 regs->SwReg05.sw_vop_time_incr = pp->vop_time_increment_resolution; in vdpu1_mpg4d_setup_regs_by_syntax()
140 regs->SwReg03.sw_pic_b_e = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
141 regs->SwReg03.sw_pic_inter_e = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
142 regs->SwReg18.sw_mpeg4_vc1_rc = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
143 regs->SwReg14.sw_refer0_base = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
147 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_ref1; in vdpu1_mpg4d_setup_regs_by_syntax()
148 regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_ref1; in vdpu1_mpg4d_setup_regs_by_syntax()
150 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
151 regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
156 regs->SwReg16.sw_refer2_base = (RK_U32)ctx->fd_ref0; in vdpu1_mpg4d_setup_regs_by_syntax()
157 regs->SwReg17.sw_refer3_base = (RK_U32)ctx->fd_ref0; in vdpu1_mpg4d_setup_regs_by_syntax()
159 regs->SwReg16.sw_refer2_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
160 regs->SwReg17.sw_refer3_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
163 regs->SwReg18.sw_fcode_fwd_hor = pp->vop_fcode_forward; in vdpu1_mpg4d_setup_regs_by_syntax()
164 regs->SwReg18.sw_fcode_fwd_ver = pp->vop_fcode_forward; in vdpu1_mpg4d_setup_regs_by_syntax()
165 regs->SwReg18.sw_fcode_bwd_hor = pp->vop_fcode_backward; in vdpu1_mpg4d_setup_regs_by_syntax()
166 regs->SwReg18.sw_fcode_bwd_ver = pp->vop_fcode_backward; in vdpu1_mpg4d_setup_regs_by_syntax()
167 regs->SwReg03.sw_write_mvs_e = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
168 regs->SwReg41.sw_dir_mv_base = mv_buf_fd; in vdpu1_mpg4d_setup_regs_by_syntax()
169 regs->SwReg19.sw_refer5_base = trb_per_trd_d0; in vdpu1_mpg4d_setup_regs_by_syntax()
170 regs->SwReg21.sw_refer7_base = trb_per_trd_d1; in vdpu1_mpg4d_setup_regs_by_syntax()
171 regs->SwReg20.sw_refer6_base = trb_per_trd_dm1; in vdpu1_mpg4d_setup_regs_by_syntax()
174 regs->SwReg03.sw_pic_b_e = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
175 regs->SwReg03.sw_pic_inter_e = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
178 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_ref0; in vdpu1_mpg4d_setup_regs_by_syntax()
179 regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_ref0; in vdpu1_mpg4d_setup_regs_by_syntax()
181 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
182 regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
184 regs->SwReg16.sw_refer2_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
185 regs->SwReg17.sw_refer3_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
187 regs->SwReg18.sw_fcode_fwd_hor = pp->vop_fcode_forward; in vdpu1_mpg4d_setup_regs_by_syntax()
188 regs->SwReg18.sw_fcode_fwd_ver = pp->vop_fcode_forward; in vdpu1_mpg4d_setup_regs_by_syntax()
189 regs->SwReg03.sw_write_mvs_e = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
190 regs->SwReg41.sw_dir_mv_base = mv_buf_fd; in vdpu1_mpg4d_setup_regs_by_syntax()
193 regs->SwReg03.sw_pic_b_e = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
194 regs->SwReg03.sw_pic_inter_e = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
196 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
197 regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
198 regs->SwReg16.sw_refer2_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
199 regs->SwReg17.sw_refer3_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
201 regs->SwReg03.sw_write_mvs_e = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
202 regs->SwReg41.sw_dir_mv_base = mv_buf_fd; in vdpu1_mpg4d_setup_regs_by_syntax()
204 regs->SwReg18.sw_fcode_fwd_hor = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
205 regs->SwReg18.sw_fcode_fwd_ver = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
213 regs->SwReg03.sw_pic_interlace_e = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
214 regs->SwReg03.sw_pic_fieldmode_e = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
215 regs->SwReg04.sw_topfieldfirst_e = pp->top_field_first; in vdpu1_mpg4d_setup_regs_by_syntax()
218 regs->SwReg18.sw_prev_anc_type = pp->prev_coding_type; in vdpu1_mpg4d_setup_regs_by_syntax()
219 regs->SwReg05.sw_type1_quant_e = pp->quant_type; in vdpu1_mpg4d_setup_regs_by_syntax()
220 regs->SwReg40.sw_qtable_base = mpp_buffer_get_fd(ctx->qp_table); in vdpu1_mpg4d_setup_regs_by_syntax()
221 regs->SwReg18.sw_mv_accuracy_fwd = pp->quarter_sample; in vdpu1_mpg4d_setup_regs_by_syntax()
228 M4vdVdpu1Regs_t *regs = NULL; in vdpu1_mpg4d_init() local
254 regs = mpp_calloc(M4vdVdpu1Regs_t, 1); in vdpu1_mpg4d_init()
255 if (NULL == regs) { in vdpu1_mpg4d_init()
273 ctx->regs = regs; in vdpu1_mpg4d_init()
280 if (regs) { in vdpu1_mpg4d_init()
281 mpp_free(regs); in vdpu1_mpg4d_init()
282 regs = NULL; in vdpu1_mpg4d_init()
310 if (ctx->regs) { in vdpu1_mpg4d_deinit()
311 mpp_free(ctx->regs); in vdpu1_mpg4d_deinit()
312 ctx->regs = NULL; in vdpu1_mpg4d_deinit()
347 M4vdVdpu1Regs_t *regs = ctx->regs; in vdpu1_mpg4d_gen_regs() local
353 memset(regs, 0, sizeof(M4vdVdpu1Regs_t)); in vdpu1_mpg4d_gen_regs()
358 regs->SwReg02.sw_dec_out_endian = 1; in vdpu1_mpg4d_gen_regs()
359 regs->SwReg02.sw_dec_in_endian = 1; in vdpu1_mpg4d_gen_regs()
360 regs->SwReg02.sw_dec_inswap32_e = 1; in vdpu1_mpg4d_gen_regs()
361 regs->SwReg02.sw_dec_outswap32_e = 1; in vdpu1_mpg4d_gen_regs()
362 regs->SwReg02.sw_dec_strswap32_e = 1; in vdpu1_mpg4d_gen_regs()
363 regs->SwReg02.sw_dec_strendian_e = 1; in vdpu1_mpg4d_gen_regs()
364 regs->SwReg02.sw_dec_max_burst = 16; in vdpu1_mpg4d_gen_regs()
365 regs->SwReg55.sw_apf_threshold = 1; in vdpu1_mpg4d_gen_regs()
366 regs->SwReg02.sw_dec_timeout_e = 1; in vdpu1_mpg4d_gen_regs()
367 regs->SwReg02.sw_dec_clk_gate_e = 1; in vdpu1_mpg4d_gen_regs()
368 regs->SwReg01.sw_dec_en = 1; in vdpu1_mpg4d_gen_regs()
369 regs->SwReg49.sw_pred_bc_tap_0_0 = -1; in vdpu1_mpg4d_gen_regs()
370 regs->SwReg49.sw_pred_bc_tap_0_1 = 3; in vdpu1_mpg4d_gen_regs()
371 regs->SwReg49.sw_pred_bc_tap_0_2 = -6; in vdpu1_mpg4d_gen_regs()
372 regs->SwReg34.sw_pred_bc_tap_0_3 = 20; in vdpu1_mpg4d_gen_regs()
385 regs->SwReg13.dec_out_st_adr = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_gen_regs()
386 regs->SwReg12.sw_rlc_vlc_base = mpp_buffer_get_fd(buf_pkt); in vdpu1_mpg4d_gen_regs()
404 RK_U32* regs = (RK_U32 *)ctx->regs; in vdpu1_mpg4d_start() local
411 mpp_log("reg[%03d]: %08x\n", i, regs[i]); in vdpu1_mpg4d_start()
420 wr_cfg.reg = regs; in vdpu1_mpg4d_start()
430 rd_cfg.reg = regs; in vdpu1_mpg4d_start()
455 M4vdVdpu1Regs_t *regs = (M4vdVdpu1Regs_t *)ctx->regs; in vdpu1_mpg4d_wait() local
466 mpp_log("reg[%03d]: %08x\n", i, ((RK_U32 *)regs)[i]); in vdpu1_mpg4d_wait()
473 param.regs = (RK_U32 *)ctx->regs; in vdpu1_mpg4d_wait()
474 param.hard_err = !regs->SwReg01.sw_dec_rdy_int; in vdpu1_mpg4d_wait()
479 memset(®s->SwReg01, 0, sizeof(RK_U32)); in vdpu1_mpg4d_wait()