Lines Matching refs:regs
37 M4vdVdpu2Regs_t *regs = ctx->regs; in vdpu2_mpg4d_setup_regs_by_syntax() local
83 regs->reg120.sw_pic_mb_width = (pp->vop_width + 15) >> 4; in vdpu2_mpg4d_setup_regs_by_syntax()
84 regs->reg120.sw_pic_mb_hight_p = (pp->vop_height + 15) >> 4; in vdpu2_mpg4d_setup_regs_by_syntax()
86 regs->reg120.sw_mb_width_off = pp->vop_width & 0xf; in vdpu2_mpg4d_setup_regs_by_syntax()
87 regs->reg120.sw_mb_height_off = pp->vop_height & 0xf; in vdpu2_mpg4d_setup_regs_by_syntax()
89 regs->reg120.sw_mb_width_off = 0; in vdpu2_mpg4d_setup_regs_by_syntax()
90 regs->reg120.sw_mb_height_off = 0; in vdpu2_mpg4d_setup_regs_by_syntax()
92 regs->reg53_dec_mode = 1; in vdpu2_mpg4d_setup_regs_by_syntax()
99 regs->reg136.sw_alt_scan_flag_e = pp->alternate_vertical_scan_flag; in vdpu2_mpg4d_setup_regs_by_syntax()
100 regs->reg52_error_concealment.sw_xdim_mbst = 0; in vdpu2_mpg4d_setup_regs_by_syntax()
101 regs->reg52_error_concealment.sw_ydim_mbst = 0; in vdpu2_mpg4d_setup_regs_by_syntax()
102 regs->reg50_dec_ctrl.sw_dblk_flt_dis = 1; in vdpu2_mpg4d_setup_regs_by_syntax()
103 regs->reg136.sw_rounding = pp->vop_rounding_type; in vdpu2_mpg4d_setup_regs_by_syntax()
104 regs->reg122.sw_intradc_vlc_thr = pp->intra_dc_vlc_thr; in vdpu2_mpg4d_setup_regs_by_syntax()
105 regs->reg51_stream_info.sw_qp_init_val = pp->vop_quant; in vdpu2_mpg4d_setup_regs_by_syntax()
106 regs->reg122.sw_sync_markers_en = 1; in vdpu2_mpg4d_setup_regs_by_syntax()
115 RK_U32 val = regs->reg64_input_stream_base; in vdpu2_mpg4d_setup_regs_by_syntax()
121 regs->reg64_input_stream_base = val; in vdpu2_mpg4d_setup_regs_by_syntax()
124 regs->reg122.sw_stream_start_word = start_bit_offset; in vdpu2_mpg4d_setup_regs_by_syntax()
125 regs->reg51_stream_info.sw_stream_len = left_bytes; in vdpu2_mpg4d_setup_regs_by_syntax()
127 regs->reg122.sw_vop_time_incr = pp->vop_time_increment_resolution; in vdpu2_mpg4d_setup_regs_by_syntax()
138 regs->reg57_enable_ctrl.sw_pic_type_sel1 = 1; in vdpu2_mpg4d_setup_regs_by_syntax()
139 regs->reg57_enable_ctrl.sw_pic_type_sel0 = 1; in vdpu2_mpg4d_setup_regs_by_syntax()
140 regs->reg136.sw_rounding = 0; in vdpu2_mpg4d_setup_regs_by_syntax()
141 regs->reg131_ref0_base = 1; in vdpu2_mpg4d_setup_regs_by_syntax()
145 regs->reg131_ref0_base = (RK_U32)ctx->fd_ref1; in vdpu2_mpg4d_setup_regs_by_syntax()
146 regs->reg148_ref1_base = (RK_U32)ctx->fd_ref1; in vdpu2_mpg4d_setup_regs_by_syntax()
148 regs->reg131_ref0_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
149 regs->reg148_ref1_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
154 regs->reg134_ref2_base = (RK_U32)ctx->fd_ref0; in vdpu2_mpg4d_setup_regs_by_syntax()
155 regs->reg135_ref3_base = (RK_U32)ctx->fd_ref0; in vdpu2_mpg4d_setup_regs_by_syntax()
157 regs->reg134_ref2_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
158 regs->reg135_ref3_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
161 regs->reg136.sw_hrz_bit_of_fwd_mv = pp->vop_fcode_forward; in vdpu2_mpg4d_setup_regs_by_syntax()
162 regs->reg136.sw_vrz_bit_of_fwd_mv = pp->vop_fcode_forward; in vdpu2_mpg4d_setup_regs_by_syntax()
163 regs->reg136.sw_hrz_bit_of_bwd_mv = pp->vop_fcode_backward; in vdpu2_mpg4d_setup_regs_by_syntax()
164 regs->reg136.sw_vrz_bit_of_bwd_mv = pp->vop_fcode_backward; in vdpu2_mpg4d_setup_regs_by_syntax()
165 regs->reg57_enable_ctrl.sw_dmmv_wr_en = 0; in vdpu2_mpg4d_setup_regs_by_syntax()
166 regs->reg62_directmv_base = mv_buf_fd; in vdpu2_mpg4d_setup_regs_by_syntax()
167 regs->reg137.sw_trb_per_trd_d0 = trb_per_trd_d0; in vdpu2_mpg4d_setup_regs_by_syntax()
168 regs->reg139.sw_trb_per_trd_d1 = trb_per_trd_d1; in vdpu2_mpg4d_setup_regs_by_syntax()
169 regs->reg138.sw_trb_per_trd_dm1 = trb_per_trd_dm1; in vdpu2_mpg4d_setup_regs_by_syntax()
172 regs->reg57_enable_ctrl.sw_pic_type_sel1 = 0; in vdpu2_mpg4d_setup_regs_by_syntax()
173 regs->reg57_enable_ctrl.sw_pic_type_sel0 = 1; in vdpu2_mpg4d_setup_regs_by_syntax()
176 regs->reg131_ref0_base = (RK_U32)ctx->fd_ref0; in vdpu2_mpg4d_setup_regs_by_syntax()
177 regs->reg148_ref1_base = (RK_U32)ctx->fd_ref0; in vdpu2_mpg4d_setup_regs_by_syntax()
179 regs->reg131_ref0_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
180 regs->reg148_ref1_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
182 regs->reg134_ref2_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
183 regs->reg135_ref3_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
185 regs->reg136.sw_hrz_bit_of_fwd_mv = pp->vop_fcode_forward; in vdpu2_mpg4d_setup_regs_by_syntax()
186 regs->reg136.sw_vrz_bit_of_fwd_mv = pp->vop_fcode_forward; in vdpu2_mpg4d_setup_regs_by_syntax()
187 regs->reg57_enable_ctrl.sw_dmmv_wr_en = 1; in vdpu2_mpg4d_setup_regs_by_syntax()
188 regs->reg62_directmv_base = mv_buf_fd; in vdpu2_mpg4d_setup_regs_by_syntax()
191 regs->reg57_enable_ctrl.sw_pic_type_sel1 = 0; in vdpu2_mpg4d_setup_regs_by_syntax()
192 regs->reg57_enable_ctrl.sw_pic_type_sel0 = 0; in vdpu2_mpg4d_setup_regs_by_syntax()
194 regs->reg131_ref0_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
195 regs->reg148_ref1_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
196 regs->reg134_ref2_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
197 regs->reg135_ref3_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
199 regs->reg57_enable_ctrl.sw_dmmv_wr_en = 0; in vdpu2_mpg4d_setup_regs_by_syntax()
200 regs->reg62_directmv_base = mv_buf_fd; in vdpu2_mpg4d_setup_regs_by_syntax()
202 regs->reg136.sw_hrz_bit_of_fwd_mv = 1; in vdpu2_mpg4d_setup_regs_by_syntax()
203 regs->reg136.sw_vrz_bit_of_fwd_mv = 1; in vdpu2_mpg4d_setup_regs_by_syntax()
211 regs->reg57_enable_ctrl.sw_curpic_code_sel = 1; in vdpu2_mpg4d_setup_regs_by_syntax()
212 regs->reg57_enable_ctrl.sw_curpic_stru_sel = 0; in vdpu2_mpg4d_setup_regs_by_syntax()
213 regs->reg120.sw_topfieldfirst_e = pp->top_field_first; in vdpu2_mpg4d_setup_regs_by_syntax()
216 regs->reg136.sw_prev_pic_type = pp->prev_coding_type; in vdpu2_mpg4d_setup_regs_by_syntax()
217 regs->reg122.sw_quant_type_1_en = pp->quant_type; in vdpu2_mpg4d_setup_regs_by_syntax()
218 regs->reg61_qtable_base = mpp_buffer_get_fd(ctx->qp_table); in vdpu2_mpg4d_setup_regs_by_syntax()
219 regs->reg136.sw_fwd_mv_y_resolution = pp->quarter_sample; in vdpu2_mpg4d_setup_regs_by_syntax()
226 M4vdVdpu2Regs_t *regs = NULL; in vdpu2_mpg4d_init() local
252 regs = mpp_calloc(M4vdVdpu2Regs_t, 1); in vdpu2_mpg4d_init()
253 if (NULL == regs) { in vdpu2_mpg4d_init()
271 ctx->regs = regs; in vdpu2_mpg4d_init()
278 if (regs) { in vdpu2_mpg4d_init()
279 mpp_free(regs); in vdpu2_mpg4d_init()
280 regs = NULL; in vdpu2_mpg4d_init()
308 if (ctx->regs) { in vdpu2_mpg4d_deinit()
309 mpp_free(ctx->regs); in vdpu2_mpg4d_deinit()
310 ctx->regs = NULL; in vdpu2_mpg4d_deinit()
345 M4vdVdpu2Regs_t *regs = ctx->regs; in vdpu2_mpg4d_gen_regs() local
351 memset(regs, 0, sizeof(M4vdVdpu2Regs_t)); in vdpu2_mpg4d_gen_regs()
356 regs->reg54_endian.sw_dec_out_endian = 1; in vdpu2_mpg4d_gen_regs()
357 regs->reg54_endian.sw_dec_in_endian = 1; in vdpu2_mpg4d_gen_regs()
358 regs->reg54_endian.sw_dec_in_wordsp = 1; in vdpu2_mpg4d_gen_regs()
359 regs->reg54_endian.sw_dec_out_wordsp = 1; in vdpu2_mpg4d_gen_regs()
360 regs->reg54_endian.sw_dec_strswap32_e = 1; in vdpu2_mpg4d_gen_regs()
361 regs->reg54_endian.sw_dec_strendian_e = 1; in vdpu2_mpg4d_gen_regs()
362 regs->reg56_axi_ctrl.sw_dec_max_burlen = 16; in vdpu2_mpg4d_gen_regs()
363 regs->reg52_error_concealment.sw_adv_pref_thrd = 1; in vdpu2_mpg4d_gen_regs()
364 regs->reg57_enable_ctrl.sw_timeout_sts_en = 1; in vdpu2_mpg4d_gen_regs()
365 regs->reg57_enable_ctrl.sw_dec_clkgate_en = 1; in vdpu2_mpg4d_gen_regs()
366 regs->reg57_enable_ctrl.sw_dec_st_work = 1; in vdpu2_mpg4d_gen_regs()
367 regs->reg59.sw_pflt_set0_tap0 = -1; in vdpu2_mpg4d_gen_regs()
368 regs->reg59.sw_pflt_set0_tap1 = 3; in vdpu2_mpg4d_gen_regs()
369 regs->reg59.sw_pflt_set0_tap2 = -6; in vdpu2_mpg4d_gen_regs()
370 regs->reg153.sw_pred_bc_tap_0_3 = 20; in vdpu2_mpg4d_gen_regs()
383 regs->reg63_cur_pic_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_gen_regs()
384 regs->reg64_input_stream_base = mpp_buffer_get_fd(buf_pkt); in vdpu2_mpg4d_gen_regs()
402 RK_U32* regs = (RK_U32 *)ctx->regs; in vdpu2_mpg4d_start() local
409 mpp_log("reg[%03d]: %08x\n", i, regs[i]); in vdpu2_mpg4d_start()
418 wr_cfg.reg = regs; in vdpu2_mpg4d_start()
428 rd_cfg.reg = regs; in vdpu2_mpg4d_start()
453 M4vdVdpu2Regs_t *regs = (M4vdVdpu2Regs_t *)ctx->regs; in vdpu2_mpg4d_wait() local
464 mpp_log("reg[%03d]: %08x\n", i, ((RK_U32 *)regs)[i]); in vdpu2_mpg4d_wait()
471 if (!regs->reg55_Interrupt.sw_dec_rdy_int) in vdpu2_mpg4d_wait()
475 param.regs = (RK_U32 *)ctx->regs; in vdpu2_mpg4d_wait()