Lines Matching refs:regs
74 void *regs; member
510 static void vepu541_h265_set_l2_regs(H265eV541HalContext *ctx, H265eV54xL2RegSet *regs) in vepu541_h265_set_l2_regs() argument
515 memcpy(®s->lvl32_intra_CST_THD0, lvl32_intra_cst_thd, sizeof(lvl32_intra_cst_thd)); in vepu541_h265_set_l2_regs()
516 memcpy(®s->lvl16_intra_CST_THD0, lvl16_intra_cst_thd, sizeof(lvl16_intra_cst_thd)); in vepu541_h265_set_l2_regs()
517 memcpy(®s->lvl32_intra_CST_WGT0, lvl32_intra_cst_wgt, sizeof(lvl32_intra_cst_wgt)); in vepu541_h265_set_l2_regs()
518 memcpy(®s->lvl16_intra_CST_WGT0, lvl16_intra_cst_wgt, sizeof(lvl16_intra_cst_wgt)); in vepu541_h265_set_l2_regs()
519 regs->rdo_quant.quant_f_bias_I = 171; in vepu541_h265_set_l2_regs()
520 regs->rdo_quant.quant_f_bias_P = 85; in vepu541_h265_set_l2_regs()
521 memcpy(®s->atr_thd0, atr_thd, sizeof(atr_thd)); in vepu541_h265_set_l2_regs()
522 memcpy(®s->lvl16_atr_wgt, lvl16_4_atr_wgt, sizeof(lvl16_4_atr_wgt)); in vepu541_h265_set_l2_regs()
524 memcpy(®s->thd_541.atf_thd0, atf_thd, sizeof(atf_thd)); in vepu541_h265_set_l2_regs()
525 regs->thd_541.atf_thd0.atf_thd0_i32 = 0; in vepu541_h265_set_l2_regs()
526 regs->thd_541.atf_thd0.atf_thd1_i32 = 63; in vepu541_h265_set_l2_regs()
527 regs->thd_541.atf_thd1.atf_thd0_i16 = 0; in vepu541_h265_set_l2_regs()
528 regs->thd_541.atf_thd1.atf_thd1_i16 = 63; in vepu541_h265_set_l2_regs()
529 regs->thd_541.atf_sad_thd0.atf_thd0_p64 = 0; in vepu541_h265_set_l2_regs()
530 regs->thd_541.atf_sad_thd0.atf_thd1_p64 = 63; in vepu541_h265_set_l2_regs()
531 regs->thd_541.atf_sad_thd1.atf_thd0_p32 = 0; in vepu541_h265_set_l2_regs()
532 regs->thd_541.atf_sad_thd1.atf_thd1_p32 = 63; in vepu541_h265_set_l2_regs()
533 regs->thd_541.atf_sad_wgt0.atf_thd0_p16 = 0; in vepu541_h265_set_l2_regs()
534 regs->thd_541.atf_sad_wgt0.atf_thd1_p16 = 63; in vepu541_h265_set_l2_regs()
536 memcpy(®s->thd_540.atf_thd0, atf_thd, sizeof(atf_thd)); in vepu541_h265_set_l2_regs()
537 regs->thd_540.atf_thd0.atf_thd0_i32 = 0; in vepu541_h265_set_l2_regs()
538 regs->thd_540.atf_thd0.atf_thd1_i32 = 63; in vepu541_h265_set_l2_regs()
539 regs->thd_540.atf_thd1.atf_thd0_i16 = 0; in vepu541_h265_set_l2_regs()
540 regs->thd_540.atf_thd1.atf_thd1_i16 = 63; in vepu541_h265_set_l2_regs()
541 regs->thd_540.atf_sad_thd0.atf_thd0_p64 = 0; in vepu541_h265_set_l2_regs()
542 regs->thd_540.atf_sad_thd0.atf_thd1_p64 = 63; in vepu541_h265_set_l2_regs()
543 regs->thd_540.atf_sad_thd1.atf_thd0_p32 = 0; in vepu541_h265_set_l2_regs()
544 regs->thd_540.atf_sad_thd1.atf_thd1_p32 = 63; in vepu541_h265_set_l2_regs()
545 regs->thd_540.atf_sad_wgt0.atf_thd0_p16 = 0; in vepu541_h265_set_l2_regs()
546 regs->thd_540.atf_sad_wgt0.atf_thd1_p16 = 63; in vepu541_h265_set_l2_regs()
547 vepu540_h265_set_l2_regs(regs); in vepu541_h265_set_l2_regs()
551 regs->atf_sad_wgt1.atf_wgt_i16 = 19; in vepu541_h265_set_l2_regs()
552 regs->atf_sad_wgt1.atf_wgt_i32 = 19; in vepu541_h265_set_l2_regs()
553 regs->atf_sad_wgt2.atf_wgt_p32 = 13; in vepu541_h265_set_l2_regs()
554 regs->atf_sad_wgt2.atf_wgt_p64 = 13; in vepu541_h265_set_l2_regs()
555 regs->atf_sad_ofst0.atf_wgt_p16 = 13; in vepu541_h265_set_l2_regs()
557 regs->atf_sad_wgt1.atf_wgt_i16 = 16; in vepu541_h265_set_l2_regs()
558 regs->atf_sad_wgt1.atf_wgt_i32 = 16; in vepu541_h265_set_l2_regs()
559 regs->atf_sad_wgt2.atf_wgt_p32 = 16; in vepu541_h265_set_l2_regs()
560 regs->atf_sad_wgt2.atf_wgt_p64 = 16; in vepu541_h265_set_l2_regs()
561 regs->atf_sad_ofst0.atf_wgt_p16 = 16; in vepu541_h265_set_l2_regs()
564 memcpy(®s->atf_sad_ofst1, atf_sad_ofst, sizeof(atf_sad_ofst)); in vepu541_h265_set_l2_regs()
565 memcpy(®s->lamd_satd_qp[0], lamd_satd_qp, sizeof(lamd_satd_qp)); in vepu541_h265_set_l2_regs()
566 memcpy(®s->lamd_moda_qp[0], lamd_moda_qp, sizeof(lamd_moda_qp)); in vepu541_h265_set_l2_regs()
567 memcpy(®s->lamd_modb_qp[0], lamd_modb_qp, sizeof(lamd_modb_qp)); in vepu541_h265_set_l2_regs()
571 regs->aq_tthd[i] = hw->aq_thrd_i[i]; in vepu541_h265_set_l2_regs()
572 regs->aq_step[i] = hw->aq_step_i[i] & 0x3f; in vepu541_h265_set_l2_regs()
576 regs->aq_tthd[i] = hw->aq_thrd_p[i]; in vepu541_h265_set_l2_regs()
577 regs->aq_step[i] = hw->aq_step_p[i] & 0x3f; in vepu541_h265_set_l2_regs()
582 regs->rdo_quant.quant_f_bias_I = hw->qbias_i; in vepu541_h265_set_l2_regs()
583 regs->rdo_quant.quant_f_bias_P = hw->qbias_p; in vepu541_h265_set_l2_regs()
587 cfg.reg = regs; in vepu541_h265_set_l2_regs()
605 ctx->regs = mpp_calloc(H265eV541RegSet, 1); in hal_h265e_v541_init()
629 ctx->osd_cfg.reg_base = ctx->regs; in hal_h265e_v541_init()
661 MPP_FREE(ctx->regs); in hal_h265e_v541_deinit()
820 static MPP_RET setup_vepu541_intra_refresh(H265eV541RegSet *regs, H265eV541HalContext *ctx, RK_U32 … in setup_vepu541_intra_refresh() argument
884 regs->me_rnge.cime_srch_v = 1; in setup_vepu541_intra_refresh()
895 regs->me_rnge.cime_srch_h = 1; in setup_vepu541_intra_refresh()
905 regs->enc_pic.roi_en = 1; in setup_vepu541_intra_refresh()
906 regs->roi_addr_hevc = fd; in setup_vepu541_intra_refresh()
918 vepu541_h265_set_roi_regs(H265eV541HalContext *ctx, H265eV541RegSet *regs) in vepu541_h265_set_roi_regs() argument
923 regs->enc_pic.roi_en = 1; in vepu541_h265_set_roi_regs()
924 regs->roi_addr_hevc = mpp_buffer_get_fd(cfg->base_cfg_buf); in vepu541_h265_set_roi_regs()
926 regs->enc_pic.roi_en = 1; in vepu541_h265_set_roi_regs()
927 regs->roi_addr_hevc = mpp_buffer_get_fd(ctx->qpmap); in vepu541_h265_set_roi_regs()
961 regs->enc_pic.roi_en = 1; in vepu541_h265_set_roi_regs()
962 regs->roi_addr_hevc = mpp_buffer_get_fd(ctx->roi_buf); in vepu541_h265_set_roi_regs()
972 static MPP_RET vepu541_h265_set_rc_regs(H265eV541HalContext *ctx, H265eV541RegSet *regs, HalEncTask… in vepu541_h265_set_rc_regs() argument
989 regs->enc_pic.pic_qp = rc_cfg->quality_target; in vepu541_h265_set_rc_regs()
990 regs->synt_sli1.sli_qp = rc_cfg->quality_target; in vepu541_h265_set_rc_regs()
992 regs->rc_qp.rc_max_qp = rc_cfg->quality_target; in vepu541_h265_set_rc_regs()
993 regs->rc_qp.rc_min_qp = rc_cfg->quality_target; in vepu541_h265_set_rc_regs()
1002 regs->enc_pic.pic_qp = rc_cfg->quality_target; in vepu541_h265_set_rc_regs()
1003 regs->synt_sli1.sli_qp = rc_cfg->quality_target; in vepu541_h265_set_rc_regs()
1004 regs->rc_cfg.rc_en = 1; in vepu541_h265_set_rc_regs()
1005 regs->rc_cfg.aqmode_en = 1; in vepu541_h265_set_rc_regs()
1006 regs->rc_cfg.qp_mode = 1; in vepu541_h265_set_rc_regs()
1008 regs->rc_cfg.rc_ctu_num = mb_wd64; in vepu541_h265_set_rc_regs()
1010 regs->rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ? in vepu541_h265_set_rc_regs()
1012 regs->rc_qp.rc_max_qp = rc_cfg->quality_max; in vepu541_h265_set_rc_regs()
1013 regs->rc_qp.rc_min_qp = rc_cfg->quality_min; in vepu541_h265_set_rc_regs()
1014 regs->rc_tgt.ctu_ebits = ctu_target_bits_mul_16; in vepu541_h265_set_rc_regs()
1016 regs->rc_erp0.bits_thd0 = 2 * negative_bits_thd; in vepu541_h265_set_rc_regs()
1017 regs->rc_erp1.bits_thd1 = negative_bits_thd; in vepu541_h265_set_rc_regs()
1018 regs->rc_erp2.bits_thd2 = positive_bits_thd; in vepu541_h265_set_rc_regs()
1019 regs->rc_erp3.bits_thd3 = 2 * positive_bits_thd; in vepu541_h265_set_rc_regs()
1020 regs->rc_erp4.bits_thd4 = 0x7FFFFFFF; in vepu541_h265_set_rc_regs()
1021 regs->rc_erp5.bits_thd5 = 0x7FFFFFFF; in vepu541_h265_set_rc_regs()
1022 regs->rc_erp6.bits_thd6 = 0x7FFFFFFF; in vepu541_h265_set_rc_regs()
1023 regs->rc_erp7.bits_thd7 = 0x7FFFFFFF; in vepu541_h265_set_rc_regs()
1024 regs->rc_erp8.bits_thd8 = 0x7FFFFFFF; in vepu541_h265_set_rc_regs()
1026 regs->rc_adj0.qp_adjust0 = -2; in vepu541_h265_set_rc_regs()
1027 regs->rc_adj0.qp_adjust1 = -1; in vepu541_h265_set_rc_regs()
1028 regs->rc_adj0.qp_adjust2 = 0; in vepu541_h265_set_rc_regs()
1029 regs->rc_adj0.qp_adjust3 = 1; in vepu541_h265_set_rc_regs()
1030 regs->rc_adj0.qp_adjust4 = 2; in vepu541_h265_set_rc_regs()
1031 regs->rc_adj1.qp_adjust5 = 0; in vepu541_h265_set_rc_regs()
1032 regs->rc_adj1.qp_adjust6 = 0; in vepu541_h265_set_rc_regs()
1033 regs->rc_adj1.qp_adjust7 = 0; in vepu541_h265_set_rc_regs()
1034 regs->rc_adj1.qp_adjust8 = 0; in vepu541_h265_set_rc_regs()
1036 … regs->qpmap0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min; in vepu541_h265_set_rc_regs()
1037 … regs->qpmap0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max; in vepu541_h265_set_rc_regs()
1038 … regs->qpmap0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min; in vepu541_h265_set_rc_regs()
1039 … regs->qpmap0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max; in vepu541_h265_set_rc_regs()
1040 … regs->qpmap0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;; in vepu541_h265_set_rc_regs()
1041 … regs->qpmap1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max; in vepu541_h265_set_rc_regs()
1042 … regs->qpmap1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;; in vepu541_h265_set_rc_regs()
1043 … regs->qpmap1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max; in vepu541_h265_set_rc_regs()
1044 … regs->qpmap1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;; in vepu541_h265_set_rc_regs()
1045 … regs->qpmap1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max; in vepu541_h265_set_rc_regs()
1046 … regs->qpmap2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;; in vepu541_h265_set_rc_regs()
1047 … regs->qpmap2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max; in vepu541_h265_set_rc_regs()
1048 … regs->qpmap2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;; in vepu541_h265_set_rc_regs()
1049 … regs->qpmap2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max; in vepu541_h265_set_rc_regs()
1050 … regs->qpmap2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;; in vepu541_h265_set_rc_regs()
1051 … regs->qpmap3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max; in vepu541_h265_set_rc_regs()
1052 regs->qpmap3.qpmap_mode = h265->qpmap_mode; in vepu541_h265_set_rc_regs()
1055 regs->enc_pic.rdo_wgt_sel = 0; in vepu541_h265_set_rc_regs()
1057 regs->enc_pic.rdo_wgt_sel = 1; in vepu541_h265_set_rc_regs()
1066 H265eV541RegSet *regs = ctx->regs; in vepu541_h265_set_pp_regs() local
1070 regs->dtrns_map.src_bus_edin = fmt->src_endian; in vepu541_h265_set_pp_regs()
1071 regs->src_fmt.src_cfmt = fmt->format; in vepu541_h265_set_pp_regs()
1072 regs->src_fmt.alpha_swap = fmt->alpha_swap; in vepu541_h265_set_pp_regs()
1073 regs->src_fmt.rbuv_swap = fmt->rbuv_swap; in vepu541_h265_set_pp_regs()
1074 regs->src_fmt.src_range = fmt->src_range; in vepu541_h265_set_pp_regs()
1075 regs->src_proc.src_mirr = prep_cfg->mirroring > 0; in vepu541_h265_set_pp_regs()
1076 regs->src_proc.src_rot = prep_cfg->rotation; in vepu541_h265_set_pp_regs()
1088 if (regs->src_fmt.src_cfmt == VEPU5xx_FMT_BGRA8888) in vepu541_h265_set_pp_regs()
1090 else if (regs->src_fmt.src_cfmt == VEPU5xx_FMT_BGR888) in vepu541_h265_set_pp_regs()
1092 else if (regs->src_fmt.src_cfmt == VEPU5xx_FMT_BGR565 || in vepu541_h265_set_pp_regs()
1093 regs->src_fmt.src_cfmt == VEPU5xx_FMT_YUYV422 || in vepu541_h265_set_pp_regs()
1094 regs->src_fmt.src_cfmt == VEPU5xx_FMT_UYVY422) in vepu541_h265_set_pp_regs()
1098 stridec = (regs->src_fmt.src_cfmt == VEPU5xx_FMT_YUV422SP || in vepu541_h265_set_pp_regs()
1099 regs->src_fmt.src_cfmt == VEPU5xx_FMT_YUV420SP) ? in vepu541_h265_set_pp_regs()
1102 if (regs->src_fmt.src_cfmt < VEPU5xx_FMT_ARGB1555) { in vepu541_h265_set_pp_regs()
1107 regs->src_udfy.wght_r2y = cfg_coeffs->_2y.r_coeff; in vepu541_h265_set_pp_regs()
1108 regs->src_udfy.wght_g2y = cfg_coeffs->_2y.g_coeff; in vepu541_h265_set_pp_regs()
1109 regs->src_udfy.wght_b2y = cfg_coeffs->_2y.b_coeff; in vepu541_h265_set_pp_regs()
1111 regs->src_udfu.wght_r2u = cfg_coeffs->_2u.r_coeff; in vepu541_h265_set_pp_regs()
1112 regs->src_udfu.wght_g2u = cfg_coeffs->_2u.g_coeff; in vepu541_h265_set_pp_regs()
1113 regs->src_udfu.wght_b2u = cfg_coeffs->_2u.b_coeff; in vepu541_h265_set_pp_regs()
1115 regs->src_udfv.wght_r2v = cfg_coeffs->_2v.r_coeff; in vepu541_h265_set_pp_regs()
1116 regs->src_udfv.wght_g2v = cfg_coeffs->_2v.g_coeff; in vepu541_h265_set_pp_regs()
1117 regs->src_udfv.wght_b2v = cfg_coeffs->_2v.b_coeff; in vepu541_h265_set_pp_regs()
1119 regs->src_udfo.ofst_y = cfg_coeffs->_2y.offset; in vepu541_h265_set_pp_regs()
1120 regs->src_udfo.ofst_u = cfg_coeffs->_2u.offset; in vepu541_h265_set_pp_regs()
1121 regs->src_udfo.ofst_v = cfg_coeffs->_2v.offset; in vepu541_h265_set_pp_regs()
1126 regs->src_strid.src_ystrid = stridey; in vepu541_h265_set_pp_regs()
1127 regs->src_strid.src_cstrid = stridec; in vepu541_h265_set_pp_regs()
1132 static void vepu541_h265_set_slice_regs(H265eSyntax_new *syn, H265eV541RegSet *regs) in vepu541_h265_set_slice_regs() argument
1134 …regs->synt_sps.smpl_adpt_ofst_en = syn->pp.sample_adaptive_offset_enabled_flag;//slice->m_sps->… in vepu541_h265_set_slice_regs()
1135 regs->synt_sps.num_st_ref_pic = syn->pp.num_short_term_ref_pic_sets; in vepu541_h265_set_slice_regs()
1136 regs->synt_sps.num_lt_ref_pic = syn->pp.num_long_term_ref_pics_sps; in vepu541_h265_set_slice_regs()
1137 regs->synt_sps.lt_ref_pic_prsnt = syn->pp.long_term_ref_pics_present_flag; in vepu541_h265_set_slice_regs()
1138 regs->synt_sps.tmpl_mvp_en = syn->pp.sps_temporal_mvp_enabled_flag; in vepu541_h265_set_slice_regs()
1139 regs->synt_sps.log2_max_poc_lsb = syn->pp.log2_max_pic_order_cnt_lsb_minus4; in vepu541_h265_set_slice_regs()
1140 regs->synt_sps.strg_intra_smth = syn->pp.strong_intra_smoothing_enabled_flag; in vepu541_h265_set_slice_regs()
1142 regs->synt_pps.dpdnt_sli_seg_en = syn->pp.dependent_slice_segments_enabled_flag; in vepu541_h265_set_slice_regs()
1143 regs->synt_pps.out_flg_prsnt_flg = syn->pp.output_flag_present_flag; in vepu541_h265_set_slice_regs()
1144 regs->synt_pps.num_extr_sli_hdr = syn->pp.num_extra_slice_header_bits; in vepu541_h265_set_slice_regs()
1145 regs->synt_pps.sgn_dat_hid_en = syn->pp.sign_data_hiding_enabled_flag; in vepu541_h265_set_slice_regs()
1146 regs->synt_pps.cbc_init_prsnt_flg = syn->pp.cabac_init_present_flag; in vepu541_h265_set_slice_regs()
1147 regs->synt_pps.pic_init_qp = syn->pp.init_qp_minus26 + 26; in vepu541_h265_set_slice_regs()
1148 regs->synt_pps.cu_qp_dlt_en = syn->pp.cu_qp_delta_enabled_flag; in vepu541_h265_set_slice_regs()
1149 regs->synt_pps.chrm_qp_ofst_prsn = syn->pp.pps_slice_chroma_qp_offsets_present_flag; in vepu541_h265_set_slice_regs()
1150 regs->synt_pps.lp_fltr_acrs_sli = syn->pp.pps_loop_filter_across_slices_enabled_flag; in vepu541_h265_set_slice_regs()
1151 regs->synt_pps.dblk_fltr_ovrd_en = syn->pp.deblocking_filter_override_enabled_flag; in vepu541_h265_set_slice_regs()
1152 regs->synt_pps.lst_mdfy_prsnt_flg = syn->pp.lists_modification_present_flag; in vepu541_h265_set_slice_regs()
1153 regs->synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag; in vepu541_h265_set_slice_regs()
1154 regs->synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth; in vepu541_h265_set_slice_regs()
1155 regs->synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag; in vepu541_h265_set_slice_regs()
1157 regs->synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg; in vepu541_h265_set_slice_regs()
1158 regs->synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg; in vepu541_h265_set_slice_regs()
1159 regs->synt_sli0.merge_up_flag = syn->sp.merge_up_flag; in vepu541_h265_set_slice_regs()
1160 regs->synt_sli0.merge_left_flag = syn->sp.merge_left_flag; in vepu541_h265_set_slice_regs()
1161 regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0; in vepu541_h265_set_slice_regs()
1163 regs->synt_sli0.num_refidx_l1_act = syn->sp.num_refidx_l1_act; in vepu541_h265_set_slice_regs()
1164 regs->synt_sli0.num_refidx_l0_act = syn->sp.num_refidx_l0_act; in vepu541_h265_set_slice_regs()
1166 regs->synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd; in vepu541_h265_set_slice_regs()
1168 regs->synt_sli0.sli_sao_chrm_flg = syn->sp.sli_sao_chrm_flg; in vepu541_h265_set_slice_regs()
1169 regs->synt_sli0.sli_sao_luma_flg = syn->sp.sli_sao_luma_flg; in vepu541_h265_set_slice_regs()
1170 regs->synt_sli0.sli_tmprl_mvp_en = syn->sp.sli_tmprl_mvp_en; in vepu541_h265_set_slice_regs()
1171 regs->enc_pic.tot_poc_num = syn->sp.tot_poc_num; in vepu541_h265_set_slice_regs()
1173 regs->synt_sli0.pic_out_flg = syn->sp.pic_out_flg; in vepu541_h265_set_slice_regs()
1174 regs->synt_sli0.sli_type = syn->sp.slice_type; in vepu541_h265_set_slice_regs()
1175 regs->synt_sli0.sli_rsrv_flg = syn->sp.slice_rsrv_flg; in vepu541_h265_set_slice_regs()
1176 regs->synt_sli0.dpdnt_sli_seg_flg = syn->sp.dpdnt_sli_seg_flg; in vepu541_h265_set_slice_regs()
1177 regs->synt_sli0.sli_pps_id = syn->sp.sli_pps_id; in vepu541_h265_set_slice_regs()
1178 regs->synt_sli0.no_out_pri_pic = syn->sp.no_out_pri_pic; in vepu541_h265_set_slice_regs()
1181 regs->synt_sli1.sli_tc_ofst_div2 = syn->sp.sli_tc_ofst_div2;; in vepu541_h265_set_slice_regs()
1182 regs->synt_sli1.sli_beta_ofst_div2 = syn->sp.sli_beta_ofst_div2; in vepu541_h265_set_slice_regs()
1183 regs->synt_sli1.sli_lp_fltr_acrs_sli = syn->sp.sli_lp_fltr_acrs_sli; in vepu541_h265_set_slice_regs()
1184 regs->synt_sli1.sli_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis; in vepu541_h265_set_slice_regs()
1185 regs->synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg; in vepu541_h265_set_slice_regs()
1186 regs->synt_sli1.sli_cb_qp_ofst = syn->pp.pps_slice_chroma_qp_offsets_present_flag ? in vepu541_h265_set_slice_regs()
1188 regs->synt_sli1.max_mrg_cnd = syn->sp.max_mrg_cnd; in vepu541_h265_set_slice_regs()
1190 regs->synt_sli1.col_ref_idx = syn->sp.col_ref_idx; in vepu541_h265_set_slice_regs()
1191 regs->synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg; in vepu541_h265_set_slice_regs()
1192 regs->synt_sli2_rodr.sli_poc_lsb = syn->sp.sli_poc_lsb; in vepu541_h265_set_slice_regs()
1193 regs->synt_sli2_rodr.sli_hdr_ext_len = syn->sp.sli_hdr_ext_len; in vepu541_h265_set_slice_regs()
1197 static void vepu541_h265_set_ref_regs(H265eSyntax_new *syn, H265eV541RegSet *regs) in vepu541_h265_set_ref_regs() argument
1199 regs->synt_ref_mark0.st_ref_pic_flg = syn->sp.st_ref_pic_flg; in vepu541_h265_set_ref_regs()
1200 regs->synt_ref_mark0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0; in vepu541_h265_set_ref_regs()
1201 regs->synt_ref_mark0.num_lt_pic = syn->sp.num_lt_pic; in vepu541_h265_set_ref_regs()
1203 regs->synt_ref_mark1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0; in vepu541_h265_set_ref_regs()
1204 regs->synt_ref_mark1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0; in vepu541_h265_set_ref_regs()
1205 regs->synt_ref_mark1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0; in vepu541_h265_set_ref_regs()
1206 regs->synt_ref_mark1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1; in vepu541_h265_set_ref_regs()
1207 regs->synt_ref_mark1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2; in vepu541_h265_set_ref_regs()
1208 regs->synt_ref_mark1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0; in vepu541_h265_set_ref_regs()
1209 regs->synt_ref_mark1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0; in vepu541_h265_set_ref_regs()
1210 regs->synt_ref_mark1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1; in vepu541_h265_set_ref_regs()
1211 regs->synt_ref_mark1.num_neg_pic = syn->sp.num_neg_pic; in vepu541_h265_set_ref_regs()
1212 regs->synt_ref_mark1.num_pos_pic = syn->sp.num_pos_pic; in vepu541_h265_set_ref_regs()
1214 regs->synt_ref_mark1.used_by_s0_flg = syn->sp.used_by_s0_flg; in vepu541_h265_set_ref_regs()
1215 regs->synt_ref_mark2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10; in vepu541_h265_set_ref_regs()
1216 regs->synt_ref_mark2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11; in vepu541_h265_set_ref_regs()
1217 regs->synt_ref_mark3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12; in vepu541_h265_set_ref_regs()
1218 regs->synt_ref_mark3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13; in vepu541_h265_set_ref_regs()
1220 regs->synt_ref_mark4.poc_lsb_lt1 = syn->sp.poc_lsb_lt1; in vepu541_h265_set_ref_regs()
1221 regs->synt_ref_mark5.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1; in vepu541_h265_set_ref_regs()
1222 regs->synt_ref_mark4.poc_lsb_lt2 = syn->sp.poc_lsb_lt2; in vepu541_h265_set_ref_regs()
1223 regs->synt_ref_mark1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2; in vepu541_h265_set_ref_regs()
1224 regs->synt_ref_mark5.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2; in vepu541_h265_set_ref_regs()
1225 regs->synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0; in vepu541_h265_set_ref_regs()
1226 regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0; in vepu541_h265_set_ref_regs()
1230 …oid vepu541_h265_set_me_regs(H265eV541HalContext *ctx, H265eSyntax_new *syn, H265eV541RegSet *regs) in vepu541_h265_set_me_regs() argument
1273 regs->me_rnge.cime_srch_h = merangx / 32; in vepu541_h265_set_me_regs()
1274 regs->me_rnge.cime_srch_v = merangy / 32; in vepu541_h265_set_me_regs()
1276 regs->me_rnge.rime_srch_h = 7; in vepu541_h265_set_me_regs()
1277 regs->me_rnge.rime_srch_v = 5; in vepu541_h265_set_me_regs()
1278 regs->me_rnge.dlt_frm_num = 0x1; in vepu541_h265_set_me_regs()
1280 regs->me_cnst.pmv_mdst_h = 5; in vepu541_h265_set_me_regs()
1281 regs->me_cnst.pmv_mdst_v = 5; in vepu541_h265_set_me_regs()
1282 regs->me_cnst.mv_limit = 0; in vepu541_h265_set_me_regs()
1283 regs->me_cnst.mv_num = 2; in vepu541_h265_set_me_regs()
1288 regs->me_cnst.colmv_load = 0; in vepu541_h265_set_me_regs()
1290 regs->me_cnst.colmv_load = 1; in vepu541_h265_set_me_regs()
1292 regs->me_cnst.colmv_store = 1; in vepu541_h265_set_me_regs()
1296 regs->me_ram.cime_rama_h = 12; in vepu541_h265_set_me_regs()
1298 regs->me_ram.cime_rama_h = 16; in vepu541_h265_set_me_regs()
1300 regs->me_ram.cime_rama_h = 20; in vepu541_h265_set_me_regs()
1304 RK_S32 swin_scope_wd16 = (regs->me_rnge.cime_srch_h + 3 + 1) / 4 * 2 + 1; in vepu541_h265_set_me_regs()
1305 RK_S32 tmpMin = (regs->me_rnge.cime_srch_v + 3) / 4 * 2 + 1; in vepu541_h265_set_me_regs()
1306 if (regs->me_ram.cime_rama_h / 4 < tmpMin) { in vepu541_h265_set_me_regs()
1307 tmpMin = regs->me_ram.cime_rama_h / 4; in vepu541_h265_set_me_regs()
1309 regs->me_ram.cime_rama_max = in vepu541_h265_set_me_regs()
1312 regs->me_ram.cach_l2_tag = 0x0; in vepu541_h265_set_me_regs()
1317 regs->me_ram.cach_l2_tag = 0x0; in vepu541_h265_set_me_regs()
1319 regs->me_ram.cach_l2_tag = 0x1; in vepu541_h265_set_me_regs()
1321 regs->me_ram.cach_l2_tag = 0x2; in vepu541_h265_set_me_regs()
1323 regs->me_ram.cach_l2_tag = 0x3; in vepu541_h265_set_me_regs()
1326 static void vepu540_h265_set_me_ram(H265eSyntax_new *syn, H265eV541RegSet *regs, in vepu540_h265_set_me_ram() argument
1332 pic_cime_temp = ((regs->enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 * 64; in vepu540_h265_set_me_ram()
1333 regs->me_ram.cime_linebuf_w = pic_cime_temp / 64; in vepu540_h265_set_me_ram()
1338 RK_S32 cime_srch_w = regs->me_rnge.cime_srch_h; in vepu540_h265_set_me_ram()
1351 regs->me_ram.cime_linebuf_w = pic_cime_temp / 64; in vepu540_h265_set_me_ram()
1362 …while ((w_temp > ((h_temp - h_val_0)*regs->me_ram.cime_linebuf_w * 4 + ((h_val_1 - h_temp) * 4 * 7… in vepu540_h265_set_me_ram()
1366 …if (w_temp < (RK_S32)((h_temp - h_val_0)*regs->me_ram.cime_linebuf_w * 4 + ((h_val_1 - h_temp) * 4… in vepu540_h265_set_me_ram()
1369 regs->me_ram.cime_rama_h = h_temp; in vepu540_h265_set_me_ram()
1377 if (regs->me_ram.cime_rama_h / 4 < tmpMin) { in vepu540_h265_set_me_ram()
1378 tmpMin = regs->me_ram.cime_rama_h / 4; in vepu540_h265_set_me_ram()
1380 …regs->me_ram.cime_rama_max = (pic_wd64 * (tmpMin - 1)) + ((pic_wd64 >= swin_scope_wd16) ? swin_sco… in vepu540_h265_set_me_ram()
1384 … regs->me_ram.cime_rama_h, regs->me_ram.cime_rama_max, regs->me_ram.cime_linebuf_w); in vepu540_h265_set_me_ram()
1386 void vepu54x_h265_set_hw_address(H265eV541HalContext *ctx, H265eV541RegSet *regs, HalEncTask *task) in vepu54x_h265_set_hw_address() argument
1395 regs->adr_srcy_hevc = mpp_buffer_get_fd(enc_task->input); in vepu54x_h265_set_hw_address()
1396 regs->adr_srcu_hevc = regs->adr_srcy_hevc; in vepu54x_h265_set_hw_address()
1397 regs->adr_srcv_hevc = regs->adr_srcy_hevc; in vepu54x_h265_set_hw_address()
1402 regs->rfpw_h_addr_hevc = mpp_buffer_get_fd(recon_buf->buf[0]); in vepu54x_h265_set_hw_address()
1403 regs->rfpw_b_addr_hevc = regs->rfpw_h_addr_hevc; in vepu54x_h265_set_hw_address()
1408 regs->dspw_addr_hevc = mpp_buffer_get_fd(recon_buf->buf[1]); in vepu54x_h265_set_hw_address()
1409 regs->cmvw_addr_hevc = mpp_buffer_get_fd(recon_buf->buf[2]); in vepu54x_h265_set_hw_address()
1410 regs->rfpr_h_addr_hevc = mpp_buffer_get_fd(ref_buf->buf[0]); in vepu54x_h265_set_hw_address()
1411 regs->rfpr_b_addr_hevc = regs->rfpr_h_addr_hevc; in vepu54x_h265_set_hw_address()
1412 regs->dspr_addr_hevc = mpp_buffer_get_fd(ref_buf->buf[1]); in vepu54x_h265_set_hw_address()
1413 regs->cmvr_addr_hevc = mpp_buffer_get_fd(ref_buf->buf[2]); in vepu54x_h265_set_hw_address()
1431 regs->lpfw_addr_hevc = mpp_buffer_get_fd(ctx->hw_tile_buf[0]); in vepu54x_h265_set_hw_address()
1432 regs->lpfr_addr_hevc = mpp_buffer_get_fd(ctx->hw_tile_buf[1]); in vepu54x_h265_set_hw_address()
1436 regs->enc_pic.mei_stor = 1; in vepu54x_h265_set_hw_address()
1437 regs->meiw_addr_hevc = mpp_buffer_get_fd(md_info_buf); in vepu54x_h265_set_hw_address()
1439 regs->enc_pic.mei_stor = 0; in vepu54x_h265_set_hw_address()
1440 regs->meiw_addr_hevc = 0; in vepu54x_h265_set_hw_address()
1443 regs->bsbb_addr_hevc = mpp_buffer_get_fd(enc_task->output); in vepu54x_h265_set_hw_address()
1445 regs->bsbt_addr_hevc = regs->bsbb_addr_hevc; in vepu54x_h265_set_hw_address()
1446 regs->bsbr_addr_hevc = regs->bsbb_addr_hevc; in vepu54x_h265_set_hw_address()
1447 regs->bsbw_addr_hevc = regs->bsbb_addr_hevc; in vepu54x_h265_set_hw_address()
1451 regs->pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); in vepu54x_h265_set_hw_address()
1452 regs->pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); in vepu54x_h265_set_hw_address()
1455 static void setup_vepu541_split(H265eV541RegSet *regs, MppEncSliceSplit *cfg) in setup_vepu541_split() argument
1461 regs->sli_spl.sli_splt = 0; in setup_vepu541_split()
1462 regs->sli_spl.sli_splt_mode = 0; in setup_vepu541_split()
1463 regs->sli_spl.sli_splt_cpst = 0; in setup_vepu541_split()
1464 regs->sli_spl.sli_max_num_m1 = 0; in setup_vepu541_split()
1465 regs->sli_spl.sli_flsh = 0; in setup_vepu541_split()
1466 regs->sli_spl.sli_splt_cnum_m1 = 0; in setup_vepu541_split()
1468 regs->sli_spl_byte.sli_splt_byte = 0; in setup_vepu541_split()
1469 regs->enc_pic.slen_fifo = 0; in setup_vepu541_split()
1472 regs->sli_spl.sli_splt = 1; in setup_vepu541_split()
1473 regs->sli_spl.sli_splt_mode = 0; in setup_vepu541_split()
1474 regs->sli_spl.sli_splt_cpst = 0; in setup_vepu541_split()
1475 regs->sli_spl.sli_max_num_m1 = 500; in setup_vepu541_split()
1476 regs->sli_spl.sli_flsh = 1; in setup_vepu541_split()
1477 regs->sli_spl.sli_splt_cnum_m1 = 0; in setup_vepu541_split()
1479 regs->sli_spl_byte.sli_splt_byte = cfg->split_arg; in setup_vepu541_split()
1480 regs->enc_pic.slen_fifo = 0; in setup_vepu541_split()
1483 regs->sli_spl.sli_splt = 1; in setup_vepu541_split()
1484 regs->sli_spl.sli_splt_mode = 1; in setup_vepu541_split()
1485 regs->sli_spl.sli_splt_cpst = 0; in setup_vepu541_split()
1486 regs->sli_spl.sli_max_num_m1 = 500; in setup_vepu541_split()
1487 regs->sli_spl.sli_flsh = 1; in setup_vepu541_split()
1488 regs->sli_spl.sli_splt_cnum_m1 = cfg->split_arg - 1; in setup_vepu541_split()
1490 regs->sli_spl_byte.sli_splt_byte = 0; in setup_vepu541_split()
1491 regs->enc_pic.slen_fifo = 0; in setup_vepu541_split()
1506 H265eV541RegSet *regs = ctx->regs; in hal_h265e_v541_gen_regs() local
1522 memset(regs, 0, sizeof(H265eV541RegSet)); in hal_h265e_v541_gen_regs()
1523 regs->enc_strt.lkt_num = 0; in hal_h265e_v541_gen_regs()
1524 regs->enc_strt.rkvenc_cmd = ctx->enc_mode; in hal_h265e_v541_gen_regs()
1525 regs->enc_strt.enc_cke = 1; in hal_h265e_v541_gen_regs()
1526 regs->enc_clr.safe_clr = 0x0; in hal_h265e_v541_gen_regs()
1528 regs->lkt_addr.lkt_addr = 0x0; in hal_h265e_v541_gen_regs()
1529 regs->int_en.enc_done_en = 1; in hal_h265e_v541_gen_regs()
1530 regs->int_en.lkt_done_en = 1; in hal_h265e_v541_gen_regs()
1531 regs->int_en.sclr_done_en = 1; in hal_h265e_v541_gen_regs()
1532 regs->int_en.slc_done_en = 1; in hal_h265e_v541_gen_regs()
1533 regs->int_en.bsf_ovflw_en = 1; in hal_h265e_v541_gen_regs()
1534 regs->int_en.brsp_ostd_en = 1; in hal_h265e_v541_gen_regs()
1535 regs->int_en.wbus_err_en = 1; in hal_h265e_v541_gen_regs()
1536 regs->int_en.rbus_err_en = 1; in hal_h265e_v541_gen_regs()
1537 regs->int_en.wdg_en = 0; in hal_h265e_v541_gen_regs()
1539 regs->enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in hal_h265e_v541_gen_regs()
1540 regs->enc_rsl.pic_wfill = (syn->pp.pic_width & 0x7) in hal_h265e_v541_gen_regs()
1542 regs->enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1; in hal_h265e_v541_gen_regs()
1543 regs->enc_rsl.pic_hfill = (syn->pp.pic_height & 0x7) in hal_h265e_v541_gen_regs()
1546 regs->enc_pic.enc_stnd = 1; //H265 in hal_h265e_v541_gen_regs()
1547 regs->enc_pic.cur_frm_ref = !syn->sp.non_reference_flag; //current frame will be refered in hal_h265e_v541_gen_regs()
1548 regs->enc_pic.bs_scp = 1; in hal_h265e_v541_gen_regs()
1549 regs->enc_pic.node_int = 0; in hal_h265e_v541_gen_regs()
1550 regs->enc_pic.log2_ctu_num = ceil(log2((double)pic_wd64 * pic_h64)); in hal_h265e_v541_gen_regs()
1552 regs->enc_pic.rdo_wgt_sel = (ctx->frame_type == INTRA_FRAME) ? 0 : 1; in hal_h265e_v541_gen_regs()
1554 regs->enc_wdg.vs_load_thd = 0; in hal_h265e_v541_gen_regs()
1555 regs->enc_wdg.rfp_load_thd = 0; in hal_h265e_v541_gen_regs()
1558 regs->dtrns_cfg_540.cime_dspw_orsd = (ctx->frame_type == INTER_P_FRAME); in hal_h265e_v541_gen_regs()
1559 regs->dtrns_cfg_540.axi_brsp_cke = 0x0; in hal_h265e_v541_gen_regs()
1561 regs->dtrns_cfg_541.cime_dspw_orsd = (ctx->frame_type == INTER_P_FRAME); in hal_h265e_v541_gen_regs()
1562 regs->dtrns_cfg_541.axi_brsp_cke = 0x0; in hal_h265e_v541_gen_regs()
1565 regs->dtrns_map.lpfw_bus_ordr = 0x0; in hal_h265e_v541_gen_regs()
1566 regs->dtrns_map.cmvw_bus_ordr = 0x0; in hal_h265e_v541_gen_regs()
1567 regs->dtrns_map.dspw_bus_ordr = 0x0; in hal_h265e_v541_gen_regs()
1568 regs->dtrns_map.rfpw_bus_ordr = 0x0; in hal_h265e_v541_gen_regs()
1569 regs->dtrns_map.src_bus_edin = 0x0; in hal_h265e_v541_gen_regs()
1570 regs->dtrns_map.meiw_bus_edin = 0x0; in hal_h265e_v541_gen_regs()
1571 regs->dtrns_map.bsw_bus_edin = 0x7; in hal_h265e_v541_gen_regs()
1572 regs->dtrns_map.lktr_bus_edin = 0x0; in hal_h265e_v541_gen_regs()
1573 regs->dtrns_map.roir_bus_edin = 0x0; in hal_h265e_v541_gen_regs()
1574 regs->dtrns_map.lktw_bus_edin = 0x0; in hal_h265e_v541_gen_regs()
1575 regs->dtrns_map.afbc_bsize = 0x1; in hal_h265e_v541_gen_regs()
1578 regs->src_proc.src_mirr = 0; in hal_h265e_v541_gen_regs()
1579 regs->src_proc.src_rot = 0; in hal_h265e_v541_gen_regs()
1580 regs->src_proc.txa_en = 1; in hal_h265e_v541_gen_regs()
1581 regs->src_proc.afbcd_en = (MPP_FRAME_FMT_IS_FBC(syn->pp.mpp_format)) ? 1 : 0; in hal_h265e_v541_gen_regs()
1586 regs->klut_ofst.chrm_kult_ofst = (ctx->frame_type == INTRA_FRAME) ? 0 : 3; in hal_h265e_v541_gen_regs()
1587 memcpy(®s->klut_wgt0, &klut_weight[0], sizeof(klut_weight)); in hal_h265e_v541_gen_regs()
1589 regs->adr_srcy_hevc = mpp_buffer_get_fd(enc_task->input); in hal_h265e_v541_gen_regs()
1590 regs->adr_srcu_hevc = regs->adr_srcy_hevc; in hal_h265e_v541_gen_regs()
1591 regs->adr_srcv_hevc = regs->adr_srcy_hevc; in hal_h265e_v541_gen_regs()
1593 setup_vepu541_split(regs, &ctx->cfg->split); in hal_h265e_v541_gen_regs()
1595 vepu541_h265_set_me_regs(ctx, syn, regs); in hal_h265e_v541_gen_regs()
1597 regs->rdo_cfg.chrm_special = 1; in hal_h265e_v541_gen_regs()
1598 regs->rdo_cfg.cu_inter_en = 0xf; in hal_h265e_v541_gen_regs()
1599 regs->rdo_cfg.cu_intra_en = 0xf; in hal_h265e_v541_gen_regs()
1602 regs->rdo_cfg.ltm_col = 0; in hal_h265e_v541_gen_regs()
1603 regs->rdo_cfg.ltm_idx0l0 = 1; in hal_h265e_v541_gen_regs()
1605 regs->rdo_cfg.ltm_col = 0; in hal_h265e_v541_gen_regs()
1606 regs->rdo_cfg.ltm_idx0l0 = 0; in hal_h265e_v541_gen_regs()
1609 regs->rdo_cfg.chrm_klut_en = 1; in hal_h265e_v541_gen_regs()
1610 regs->rdo_cfg.seq_scaling_matrix_present_flg = syn->pp.scaling_list_enabled_flag; in hal_h265e_v541_gen_regs()
1611 regs->synt_nal.nal_unit_type = h265e_get_nal_type(&syn->sp, ctx->frame_type); in hal_h265e_v541_gen_regs()
1613 vepu54x_h265_set_hw_address(ctx, regs, task); in hal_h265e_v541_gen_regs()
1616 vepu541_h265_set_rc_regs(ctx, regs, task); in hal_h265e_v541_gen_regs()
1618 vepu541_h265_set_slice_regs(syn, regs); in hal_h265e_v541_gen_regs()
1620 vepu541_h265_set_ref_regs(syn, regs); in hal_h265e_v541_gen_regs()
1627 vepu541_h265_set_roi_regs(ctx, regs); in hal_h265e_v541_gen_regs()
1630 setup_vepu541_intra_refresh(regs, ctx, frm_status->seq_idx % ctx->cfg->rc.gop); in hal_h265e_v541_gen_regs()
1637 void hal_h265e_v540_set_uniform_tile(H265eV541RegSet *regs, H265eSyntax_new *syn, in hal_h265e_v540_set_uniform_tile() argument
1644 regs->tile_cfg.tile_width_m1 = tile_width - 1; in hal_h265e_v540_set_uniform_tile()
1645 regs->tile_cfg.tile_height_m1 = mb_h - 1; in hal_h265e_v540_set_uniform_tile()
1646 regs->rc_cfg.rc_ctu_num = tile_width; in hal_h265e_v540_set_uniform_tile()
1647 regs->tile_cfg.tile_en = syn->pp.tiles_enabled_flag; in hal_h265e_v540_set_uniform_tile()
1648 regs->tile_pos.tile_x = tile_start_x; in hal_h265e_v540_set_uniform_tile()
1649 regs->tile_pos.tile_y = 0; in hal_h265e_v540_set_uniform_tile()
1651 RK_U32 tmp = regs->lpfr_addr_hevc; in hal_h265e_v540_set_uniform_tile()
1652 regs->lpfr_addr_hevc = regs->lpfw_addr_hevc; in hal_h265e_v540_set_uniform_tile()
1653 regs->lpfw_addr_hevc = tmp; in hal_h265e_v540_set_uniform_tile()
1657 regs->tile_pos.tile_x, regs->rc_cfg.rc_ctu_num, in hal_h265e_v540_set_uniform_tile()
1658 regs->tile_cfg.tile_width_m1); in hal_h265e_v540_set_uniform_tile()
1683 RK_U32 *regs = (RK_U32*)ctx->regs; in hal_h265e_v540_start() local
1684 H265eV541RegSet *hw_regs = ctx->regs; in hal_h265e_v540_start()
1706 cfg.reg = ctx->regs; in hal_h265e_v540_start()
1737 hal_h265e_dbg_regs("set reg[%04x]: 0%08x\n", i * 4, regs[i]); in hal_h265e_v540_start()
1785 RK_U32 *regs = (RK_U32*)ctx->regs; in hal_h265e_v541_start() local
1798 cfg.reg = ctx->regs; in hal_h265e_v541_start()
1838 hal_h265e_dbg_regs("set reg[%04d]: 0%08x\n", i, regs[i]); in hal_h265e_v541_start()