Lines Matching refs:regs

161     Vepu540cJpegReg *regs = (Vepu540cJpegReg *)cfg->jpeg_reg_base;  in vepu540c_set_jpeg_reg()  local
170 regs->reg0264_adr_src0 = mpp_buffer_get_fd(task->input); in vepu540c_set_jpeg_reg()
171 regs->reg0265_adr_src1 = regs->reg0264_adr_src0; in vepu540c_set_jpeg_reg()
172 regs->reg0266_adr_src2 = regs->reg0264_adr_src0; in vepu540c_set_jpeg_reg()
176 regs->reg0256_adr_bsbt = mpp_buffer_get_fd(task->output); in vepu540c_set_jpeg_reg()
177 regs->reg0257_adr_bsbb = regs->reg0256_adr_bsbt; in vepu540c_set_jpeg_reg()
178 regs->reg0258_adr_bsbs = regs->reg0256_adr_bsbt; in vepu540c_set_jpeg_reg()
179 regs->reg0259_adr_bsbr = regs->reg0256_adr_bsbt; in vepu540c_set_jpeg_reg()
184 regs->reg0272_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in vepu540c_set_jpeg_reg()
185 regs->reg0273_src_fill.pic_wfill = (syn->width & 0x7) in vepu540c_set_jpeg_reg()
187 regs->reg0272_enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1; in vepu540c_set_jpeg_reg()
188 regs->reg0273_src_fill.pic_hfill = (syn->height & 0x7) in vepu540c_set_jpeg_reg()
191 regs->reg0274_src_fmt.src_cfmt = fmt->format; in vepu540c_set_jpeg_reg()
192 regs->reg0274_src_fmt.alpha_swap = fmt->alpha_swap; in vepu540c_set_jpeg_reg()
193 regs->reg0274_src_fmt.rbuv_swap = fmt->rbuv_swap; in vepu540c_set_jpeg_reg()
194 regs->reg0274_src_fmt.src_range_trns_en = 0; in vepu540c_set_jpeg_reg()
195 regs->reg0274_src_fmt.src_range_trns_sel = 0; in vepu540c_set_jpeg_reg()
196 regs->reg0274_src_fmt.chroma_ds_mode = 0; in vepu540c_set_jpeg_reg()
197 regs->reg0274_src_fmt.out_fmt = 1; in vepu540c_set_jpeg_reg()
199 regs->reg0279_src_proc.src_mirr = 0 ;//prep_cfg->mirroring > 0; in vepu540c_set_jpeg_reg()
200 regs->reg0279_src_proc.src_rot = syn->rotation; in vepu540c_set_jpeg_reg()
205 if (regs->reg0274_src_fmt.src_cfmt == VEPU5xx_FMT_BGRA8888) in vepu540c_set_jpeg_reg()
207 else if (regs->reg0274_src_fmt.src_cfmt == VEPU5xx_FMT_BGR888) in vepu540c_set_jpeg_reg()
209 else if (regs->reg0274_src_fmt.src_cfmt == VEPU5xx_FMT_BGR565 || in vepu540c_set_jpeg_reg()
210 regs->reg0274_src_fmt.src_cfmt == VEPU5xx_FMT_YUYV422 || in vepu540c_set_jpeg_reg()
211 regs->reg0274_src_fmt.src_cfmt == VEPU5xx_FMT_UYVY422) in vepu540c_set_jpeg_reg()
215 stridec = (regs->reg0274_src_fmt.src_cfmt == VEPU5xx_FMT_YUV422SP || in vepu540c_set_jpeg_reg()
216 regs->reg0274_src_fmt.src_cfmt == VEPU5xx_FMT_YUV420SP) ? in vepu540c_set_jpeg_reg()
219 if (regs->reg0274_src_fmt.src_cfmt < VEPU5xx_FMT_ARGB1555) { in vepu540c_set_jpeg_reg()
220 regs->reg0275_src_udfy.csc_wgt_r2y = 66; in vepu540c_set_jpeg_reg()
221 regs->reg0275_src_udfy.csc_wgt_g2y = 129; in vepu540c_set_jpeg_reg()
222 regs->reg0275_src_udfy.csc_wgt_b2y = 25; in vepu540c_set_jpeg_reg()
224 regs->reg0276_src_udfu.csc_wgt_r2u = -38; in vepu540c_set_jpeg_reg()
225 regs->reg0276_src_udfu.csc_wgt_g2u = -74; in vepu540c_set_jpeg_reg()
226 regs->reg0276_src_udfu.csc_wgt_b2u = 112; in vepu540c_set_jpeg_reg()
228 regs->reg0277_src_udfv.csc_wgt_r2v = 112; in vepu540c_set_jpeg_reg()
229 regs->reg0277_src_udfv.csc_wgt_g2v = -94; in vepu540c_set_jpeg_reg()
230 regs->reg0277_src_udfv.csc_wgt_b2v = -18; in vepu540c_set_jpeg_reg()
232 regs->reg0278_src_udfo.csc_ofst_y = 16; in vepu540c_set_jpeg_reg()
233 regs->reg0278_src_udfo.csc_ofst_u = 128; in vepu540c_set_jpeg_reg()
234 regs->reg0278_src_udfo.csc_ofst_v = 128; in vepu540c_set_jpeg_reg()
236 regs->reg0281_src_strd0.src_strd0 = stridey; in vepu540c_set_jpeg_reg()
237 regs->reg0282_src_strd1.src_strd1 = stridec; in vepu540c_set_jpeg_reg()
238 regs->reg0280_pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); in vepu540c_set_jpeg_reg()
239 regs->reg0280_pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); in vepu540c_set_jpeg_reg()
247 regs->reg0284_y_cfg.bias_y = 0; in vepu540c_set_jpeg_reg()
248 regs->reg0285_u_cfg.bias_u = 0; in vepu540c_set_jpeg_reg()
249 regs->reg0286_v_cfg.bias_v = 0; in vepu540c_set_jpeg_reg()
251 regs->reg0287_base_cfg.jpeg_ri = 0; in vepu540c_set_jpeg_reg()
252 regs->reg0287_base_cfg.jpeg_out_mode = 0; in vepu540c_set_jpeg_reg()
253 regs->reg0287_base_cfg.jpeg_start_rst_m = 0; in vepu540c_set_jpeg_reg()
254 regs->reg0287_base_cfg.jpeg_pic_last_ecs = 1; in vepu540c_set_jpeg_reg()
255 regs->reg0287_base_cfg.jpeg_slen_fifo = 0; in vepu540c_set_jpeg_reg()
256 regs->reg0287_base_cfg.jpeg_stnd = 1; //enable in vepu540c_set_jpeg_reg()
258 regs->reg0288_uvc_cfg.uvc_partition0_len = 0; in vepu540c_set_jpeg_reg()
259 regs->reg0288_uvc_cfg.uvc_partition_len = 0; in vepu540c_set_jpeg_reg()
260 regs->reg0288_uvc_cfg.uvc_skip_len = 0; in vepu540c_set_jpeg_reg()