Lines Matching refs:regs
645 static void setup_vepu580_normal(HalVepu580RegSet *regs) in setup_vepu580_normal() argument
650 regs->reg_ctl.enc_strt.lkt_num = 0; in setup_vepu580_normal()
651 regs->reg_ctl.enc_strt.vepu_cmd = 1; in setup_vepu580_normal()
652 regs->reg_ctl.func_en.cke = 1; in setup_vepu580_normal()
653 regs->reg_ctl.func_en.resetn_hw_en = 1; in setup_vepu580_normal()
654 regs->reg_ctl.func_en.enc_done_tmvp_en = 1; in setup_vepu580_normal()
657 regs->reg_ctl.enc_clr.safe_clr = 0; in setup_vepu580_normal()
658 regs->reg_ctl.enc_clr.force_clr = 0; in setup_vepu580_normal()
661 regs->reg_ctl.int_en.enc_done_en = 1; in setup_vepu580_normal()
662 regs->reg_ctl.int_en.lkt_node_done_en = 1; in setup_vepu580_normal()
663 regs->reg_ctl.int_en.sclr_done_en = 1; in setup_vepu580_normal()
664 regs->reg_ctl.int_en.slc_done_en = 0; in setup_vepu580_normal()
665 regs->reg_ctl.int_en.bsf_oflw_en = 1; in setup_vepu580_normal()
666 regs->reg_ctl.int_en.brsp_otsd_en = 1; in setup_vepu580_normal()
667 regs->reg_ctl.int_en.wbus_err_en = 1; in setup_vepu580_normal()
668 regs->reg_ctl.int_en.rbus_err_en = 1; in setup_vepu580_normal()
669 regs->reg_ctl.int_en.wdg_en = 1; in setup_vepu580_normal()
672 regs->reg_ctl.int_msk.enc_done_msk = 0; in setup_vepu580_normal()
673 regs->reg_ctl.int_msk.lkt_node_done_msk = 0; in setup_vepu580_normal()
674 regs->reg_ctl.int_msk.sclr_done_msk = 0; in setup_vepu580_normal()
675 regs->reg_ctl.int_msk.slc_done_msk = 0; in setup_vepu580_normal()
676 regs->reg_ctl.int_msk.bsf_oflw_msk = 0; in setup_vepu580_normal()
677 regs->reg_ctl.int_msk.brsp_otsd_msk = 0; in setup_vepu580_normal()
678 regs->reg_ctl.int_msk.wbus_err_msk = 0; in setup_vepu580_normal()
679 regs->reg_ctl.int_msk.rbus_err_msk = 0; in setup_vepu580_normal()
680 regs->reg_ctl.int_msk.wdg_msk = 0; in setup_vepu580_normal()
682 regs->reg_ctl.enc_wdg.vs_load_thd = 0x1fffff; in setup_vepu580_normal()
683 regs->reg_ctl.enc_wdg.rfp_load_thd = 0; in setup_vepu580_normal()
686 regs->reg_ctl.dtrns_map.cmvw_bus_ordr = 0; in setup_vepu580_normal()
687 regs->reg_ctl.dtrns_map.dspw_bus_ordr = 0; in setup_vepu580_normal()
688 regs->reg_ctl.dtrns_map.rfpw_bus_ordr = 0; in setup_vepu580_normal()
689 regs->reg_ctl.dtrns_map.src_bus_edin = 0; in setup_vepu580_normal()
690 regs->reg_ctl.dtrns_map.meiw_bus_edin = 0; in setup_vepu580_normal()
691 regs->reg_ctl.dtrns_map.bsw_bus_edin = 7; in setup_vepu580_normal()
692 regs->reg_ctl.dtrns_map.lktr_bus_edin = 0; in setup_vepu580_normal()
693 regs->reg_ctl.dtrns_map.roir_bus_edin = 0; in setup_vepu580_normal()
694 regs->reg_ctl.dtrns_map.lktw_bus_edin = 0; in setup_vepu580_normal()
695 regs->reg_ctl.dtrns_map.afbc_bsize = 1; in setup_vepu580_normal()
697 regs->reg_ctl.dtrns_cfg.axi_brsp_cke = 0; in setup_vepu580_normal()
698 regs->reg_ctl.dtrns_cfg.dspr_otsd = 1; in setup_vepu580_normal()
702 static MPP_RET setup_vepu580_prep(HalVepu580RegSet *regs, MppEncPrepCfg *prep, in setup_vepu580_prep() argument
718 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu580_prep()
719 regs->reg_base.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu580_prep()
720 regs->reg_base.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu580_prep()
721 regs->reg_base.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu580_prep()
723 regs->reg_ctl.dtrns_map.src_bus_edin = cfg.src_endian; in setup_vepu580_prep()
725 regs->reg_base.src_fmt.src_cfmt = hw_fmt; in setup_vepu580_prep()
726 regs->reg_base.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu580_prep()
727 regs->reg_base.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu580_prep()
728 regs->reg_base.src_fmt.out_fmt = (fmt == MPP_FMT_YUV400) ? 0 : 1; in setup_vepu580_prep()
731 regs->reg_base.src_fmt.src_range = 1; in setup_vepu580_prep()
733 regs->reg_base.src_fmt.src_range = (prep->range == MPP_FRAME_RANGE_JPEG) ? 1 : 0; in setup_vepu580_prep()
773 regs->reg_base.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu580_prep()
774 regs->reg_base.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu580_prep()
775 regs->reg_base.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu580_prep()
777 regs->reg_base.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu580_prep()
778 regs->reg_base.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu580_prep()
779 regs->reg_base.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu580_prep()
781 regs->reg_base.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in setup_vepu580_prep()
782 regs->reg_base.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu580_prep()
783 regs->reg_base.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu580_prep()
785 regs->reg_base.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu580_prep()
786 regs->reg_base.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu580_prep()
787 regs->reg_base.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; in setup_vepu580_prep()
791 regs->reg_base.src_udfy.csc_wgt_b2y = cfg.weight[0]; in setup_vepu580_prep()
792 regs->reg_base.src_udfy.csc_wgt_g2y = cfg.weight[1]; in setup_vepu580_prep()
793 regs->reg_base.src_udfy.csc_wgt_r2y = cfg.weight[2]; in setup_vepu580_prep()
795 regs->reg_base.src_udfu.csc_wgt_b2u = cfg.weight[3]; in setup_vepu580_prep()
796 regs->reg_base.src_udfu.csc_wgt_g2u = cfg.weight[4]; in setup_vepu580_prep()
797 regs->reg_base.src_udfu.csc_wgt_r2u = cfg.weight[5]; in setup_vepu580_prep()
799 regs->reg_base.src_udfv.csc_wgt_b2v = cfg.weight[6]; in setup_vepu580_prep()
800 regs->reg_base.src_udfv.csc_wgt_g2v = cfg.weight[7]; in setup_vepu580_prep()
801 regs->reg_base.src_udfv.csc_wgt_r2v = cfg.weight[8]; in setup_vepu580_prep()
803 regs->reg_base.src_udfo.csc_ofst_y = cfg.offset[0]; in setup_vepu580_prep()
804 regs->reg_base.src_udfo.csc_ofst_u = cfg.offset[1]; in setup_vepu580_prep()
805 regs->reg_base.src_udfo.csc_ofst_v = cfg.offset[2]; in setup_vepu580_prep()
808 regs->reg_base.src_proc.afbcd_en = MPP_FRAME_FMT_IS_FBC(fmt) ? 1 : 0; in setup_vepu580_prep()
809 regs->reg_base.src_strd0.src_strd0 = y_stride; in setup_vepu580_prep()
810 regs->reg_base.src_strd1.src_strd1 = c_stride; in setup_vepu580_prep()
812 regs->reg_base.src_proc.src_mirr = prep->mirroring > 0; in setup_vepu580_prep()
813 regs->reg_base.src_proc.src_rot = prep->rotation; in setup_vepu580_prep()
814 regs->reg_base.src_proc.txa_en = 0; in setup_vepu580_prep()
816 regs->reg_base.sli_cfg.sli_crs_en = 1; in setup_vepu580_prep()
818 regs->reg_base.pic_ofst.pic_ofst_y = 0; in setup_vepu580_prep()
819 regs->reg_base.pic_ofst.pic_ofst_x = 0; in setup_vepu580_prep()
826 static MPP_RET vepu580_h264e_save_pass1_patch(HalVepu580RegSet *regs, HalH264eVepu580Ctx *ctx) in vepu580_h264e_save_pass1_patch() argument
839 regs->reg_base.enc_pic.cur_frm_ref = 1; in vepu580_h264e_save_pass1_patch()
840 regs->reg_base.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1); in vepu580_h264e_save_pass1_patch()
841 regs->reg_base.rfpw_b_addr = regs->reg_base.rfpw_h_addr; in vepu580_h264e_save_pass1_patch()
842 regs->reg_base.enc_pic.rec_fbc_dis = 1; in vepu580_h264e_save_pass1_patch()
847 regs->reg_base.sli_splt.sli_splt = 0; in vepu580_h264e_save_pass1_patch()
848 regs->reg_base.enc_pic.slen_fifo = 0; in vepu580_h264e_save_pass1_patch()
853 static MPP_RET vepu580_h264e_use_pass1_patch(HalVepu580RegSet *regs, HalH264eVepu580Ctx *ctx) in vepu580_h264e_use_pass1_patch() argument
863 regs->reg_base.src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP; in vepu580_h264e_use_pass1_patch()
864 regs->reg_base.src_fmt.alpha_swap = 0; in vepu580_h264e_use_pass1_patch()
865 regs->reg_base.src_fmt.rbuv_swap = 0; in vepu580_h264e_use_pass1_patch()
866 regs->reg_base.src_fmt.out_fmt = 1; in vepu580_h264e_use_pass1_patch()
868 regs->reg_base.src_proc.afbcd_en = 0; in vepu580_h264e_use_pass1_patch()
869 regs->reg_base.src_strd0.src_strd0 = hor_stride; in vepu580_h264e_use_pass1_patch()
870 regs->reg_base.src_strd1.src_strd1 = hor_stride; in vepu580_h264e_use_pass1_patch()
872 regs->reg_base.src_proc.src_mirr = 0; in vepu580_h264e_use_pass1_patch()
873 regs->reg_base.src_proc.src_rot = 0; in vepu580_h264e_use_pass1_patch()
874 regs->reg_base.src_proc.txa_en = 0; in vepu580_h264e_use_pass1_patch()
876 regs->reg_base.pic_ofst.pic_ofst_y = 0; in vepu580_h264e_use_pass1_patch()
877 regs->reg_base.pic_ofst.pic_ofst_x = 0; in vepu580_h264e_use_pass1_patch()
880 regs->reg_base.adr_src0 = fd_in; in vepu580_h264e_use_pass1_patch()
881 regs->reg_base.adr_src1 = fd_in; in vepu580_h264e_use_pass1_patch()
882 regs->reg_base.adr_src2 = fd_in; in vepu580_h264e_use_pass1_patch()
891 static void setup_vepu580_codec(HalVepu580RegSet *regs, H264eSps *sps, in setup_vepu580_codec() argument
896 regs->reg_base.enc_pic.enc_stnd = 0; in setup_vepu580_codec()
897 regs->reg_base.enc_pic.cur_frm_ref = slice->nal_reference_idc > 0; in setup_vepu580_codec()
898 regs->reg_base.enc_pic.bs_scp = 1; in setup_vepu580_codec()
900 regs->reg_base.synt_nal.nal_ref_idc = slice->nal_reference_idc; in setup_vepu580_codec()
901 regs->reg_base.synt_nal.nal_unit_type = slice->nalu_type; in setup_vepu580_codec()
903 regs->reg_base.synt_sps.max_fnum = sps->log2_max_frame_num_minus4; in setup_vepu580_codec()
904 regs->reg_base.synt_sps.drct_8x8 = sps->direct8x8_inference; in setup_vepu580_codec()
905 regs->reg_base.synt_sps.mpoc_lm4 = sps->log2_max_poc_lsb_minus4; in setup_vepu580_codec()
907 regs->reg_base.synt_pps.etpy_mode = pps->entropy_coding_mode; in setup_vepu580_codec()
908 regs->reg_base.synt_pps.trns_8x8 = pps->transform_8x8_mode; in setup_vepu580_codec()
909 regs->reg_base.synt_pps.csip_flag = pps->constrained_intra_pred; in setup_vepu580_codec()
910 regs->reg_base.synt_pps.num_ref0_idx = pps->num_ref_idx_l0_default_active - 1; in setup_vepu580_codec()
911 regs->reg_base.synt_pps.num_ref1_idx = pps->num_ref_idx_l1_default_active - 1; in setup_vepu580_codec()
912 regs->reg_base.synt_pps.pic_init_qp = pps->pic_init_qp; in setup_vepu580_codec()
913 regs->reg_base.synt_pps.cb_ofst = pps->chroma_qp_index_offset; in setup_vepu580_codec()
914 regs->reg_base.synt_pps.cr_ofst = pps->second_chroma_qp_index_offset; in setup_vepu580_codec()
915 regs->reg_base.synt_pps.wght_pred = pps->weighted_pred; in setup_vepu580_codec()
916 regs->reg_base.synt_pps.dbf_cp_flg = pps->deblocking_filter_control; in setup_vepu580_codec()
918 regs->reg_base.synt_sli0.sli_type = (slice->slice_type == H264_I_SLICE) ? (2) : (0); in setup_vepu580_codec()
919 regs->reg_base.synt_sli0.pps_id = slice->pic_parameter_set_id; in setup_vepu580_codec()
920 regs->reg_base.synt_sli0.drct_smvp = 0; in setup_vepu580_codec()
921 regs->reg_base.synt_sli0.num_ref_ovrd = slice->num_ref_idx_override; in setup_vepu580_codec()
922 regs->reg_base.synt_sli0.cbc_init_idc = slice->cabac_init_idc; in setup_vepu580_codec()
923 regs->reg_base.synt_sli0.frm_num = slice->frame_num; in setup_vepu580_codec()
925 …regs->reg_base.synt_sli1.idr_pid = (slice->slice_type == H264_I_SLICE) ? slice->idr_pic_id … in setup_vepu580_codec()
926 regs->reg_base.synt_sli1.poc_lsb = slice->pic_order_cnt_lsb; in setup_vepu580_codec()
929 regs->reg_base.synt_sli2.dis_dblk_idc = slice->disable_deblocking_filter_idc; in setup_vepu580_codec()
930 regs->reg_base.synt_sli2.sli_alph_ofst = slice->slice_alpha_c0_offset_div2; in setup_vepu580_codec()
938 regs->reg_base.synt_sli2.ref_list0_rodr = 1; in setup_vepu580_codec()
939 regs->reg_base.synt_sli2.rodr_pic_idx = rplmo.modification_of_pic_nums_idc; in setup_vepu580_codec()
944 regs->reg_base.synt_sli2.rodr_pic_num = rplmo.abs_diff_pic_num_minus1; in setup_vepu580_codec()
947 regs->reg_base.synt_sli2.rodr_pic_num = rplmo.long_term_pic_idx; in setup_vepu580_codec()
956 regs->reg_base.synt_sli2.ref_list0_rodr = 0; in setup_vepu580_codec()
957 regs->reg_base.synt_sli2.rodr_pic_idx = 0; in setup_vepu580_codec()
958 regs->reg_base.synt_sli2.rodr_pic_num = 0; in setup_vepu580_codec()
963 regs->reg_base.synt_refm0.nopp_flg = 0; in setup_vepu580_codec()
964 regs->reg_base.synt_refm0.ltrf_flg = 0; in setup_vepu580_codec()
965 regs->reg_base.synt_refm0.arpm_flg = 0; in setup_vepu580_codec()
966 regs->reg_base.synt_refm0.mmco4_pre = 0; in setup_vepu580_codec()
967 regs->reg_base.synt_refm0.mmco_type0 = 0; in setup_vepu580_codec()
968 regs->reg_base.synt_refm0.mmco_parm0 = 0; in setup_vepu580_codec()
969 regs->reg_base.synt_refm0.mmco_type1 = 0; in setup_vepu580_codec()
970 regs->reg_base.synt_refm1.mmco_parm1 = 0; in setup_vepu580_codec()
971 regs->reg_base.synt_refm0.mmco_type2 = 0; in setup_vepu580_codec()
972 regs->reg_base.synt_refm1.mmco_parm2 = 0; in setup_vepu580_codec()
973 regs->reg_base.synt_refm2.long_term_frame_idx0 = 0; in setup_vepu580_codec()
974 regs->reg_base.synt_refm2.long_term_frame_idx1 = 0; in setup_vepu580_codec()
975 regs->reg_base.synt_refm2.long_term_frame_idx2 = 0; in setup_vepu580_codec()
981 regs->reg_base.synt_refm0.nopp_flg = slice->no_output_of_prior_pics; in setup_vepu580_codec()
982 regs->reg_base.synt_refm0.ltrf_flg = slice->long_term_reference_flag; in setup_vepu580_codec()
987 regs->reg_base.synt_refm0.arpm_flg = 1; in setup_vepu580_codec()
1022 regs->reg_base.synt_refm0.mmco_type0 = type; in setup_vepu580_codec()
1023 regs->reg_base.synt_refm0.mmco_parm0 = param_0; in setup_vepu580_codec()
1024 regs->reg_base.synt_refm2.long_term_frame_idx0 = param_1; in setup_vepu580_codec()
1058 regs->reg_base.synt_refm0.mmco_type1 = type; in setup_vepu580_codec()
1059 regs->reg_base.synt_refm1.mmco_parm1 = param_0; in setup_vepu580_codec()
1060 regs->reg_base.synt_refm2.long_term_frame_idx1 = param_1; in setup_vepu580_codec()
1094 regs->reg_base.synt_refm0.mmco_type2 = type; in setup_vepu580_codec()
1095 regs->reg_base.synt_refm1.mmco_parm2 = param_0; in setup_vepu580_codec()
1096 regs->reg_base.synt_refm2.long_term_frame_idx2 = param_1; in setup_vepu580_codec()
1104 static void setup_vepu580_rdo_pred(HalVepu580RegSet *regs, H264eSps *sps, in setup_vepu580_rdo_pred() argument
1110 regs->reg_rc_klut.klut_ofst.chrm_klut_ofst = 0; in setup_vepu580_rdo_pred()
1111 memcpy(®s->reg_rc_klut.klut_wgt0, &h264e_klut_weight[0], CHROMA_KLUT_TAB_SIZE); in setup_vepu580_rdo_pred()
1113 regs->reg_rc_klut.klut_ofst.chrm_klut_ofst = 3; in setup_vepu580_rdo_pred()
1114 memcpy(®s->reg_rc_klut.klut_wgt0, &h264e_klut_weight[4], CHROMA_KLUT_TAB_SIZE); in setup_vepu580_rdo_pred()
1117 regs->reg_base.iprd_csts.vthd_y = 9; in setup_vepu580_rdo_pred()
1118 regs->reg_base.iprd_csts.vthd_c = 63; in setup_vepu580_rdo_pred()
1120 regs->reg_base.rdo_cfg.rect_size = (sps->profile_idc == H264_PROFILE_BASELINE && in setup_vepu580_rdo_pred()
1122 regs->reg_base.rdo_cfg.inter_4x4 = 1; in setup_vepu580_rdo_pred()
1123 regs->reg_base.rdo_cfg.vlc_lmt = (sps->profile_idc < H264_PROFILE_MAIN) && in setup_vepu580_rdo_pred()
1125 regs->reg_base.rdo_cfg.chrm_spcl = 1; in setup_vepu580_rdo_pred()
1126 regs->reg_base.rdo_cfg.rdo_mask = 0; in setup_vepu580_rdo_pred()
1127 regs->reg_base.rdo_cfg.ccwa_e = 1; in setup_vepu580_rdo_pred()
1128 regs->reg_base.rdo_cfg.scl_lst_sel = pps->pic_scaling_matrix_present; in setup_vepu580_rdo_pred()
1129 regs->reg_base.rdo_cfg.atr_e = 1; in setup_vepu580_rdo_pred()
1130 regs->reg_base.rdo_cfg.atf_intra_e = 1; in setup_vepu580_rdo_pred()
1135 static void setup_vepu580_rdo_bias_cfg(Vepu580RdoCfg *regs, MppEncHwCfg *hw) in setup_vepu580_rdo_bias_cfg() argument
1139 regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt00 = bias > 24 ? bias : 24; in setup_vepu580_rdo_bias_cfg()
1140 regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt01 = bias > 22 ? bias : 22; in setup_vepu580_rdo_bias_cfg()
1141 regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt02 = bias > 21 ? bias : 21; in setup_vepu580_rdo_bias_cfg()
1142 regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt10 = bias > 22 ? bias : 22; in setup_vepu580_rdo_bias_cfg()
1143 regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt11 = bias > 21 ? bias : 21; in setup_vepu580_rdo_bias_cfg()
1144 regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt12 = bias > 20 ? bias : 20; in setup_vepu580_rdo_bias_cfg()
1145 regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt20 = bias > 20 ? bias : 20; in setup_vepu580_rdo_bias_cfg()
1146 regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt21 = bias > 19 ? bias : 19; in setup_vepu580_rdo_bias_cfg()
1147 regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt22 = bias > 18 ? bias : 18; in setup_vepu580_rdo_bias_cfg()
1148 regs->rdo_intra_atf_wgt3.atf_rdo_intra_wgt30 = bias; in setup_vepu580_rdo_bias_cfg()
1149 regs->rdo_intra_atf_wgt3.atf_rdo_intra_wgt31 = bias; in setup_vepu580_rdo_bias_cfg()
1150 regs->rdo_intra_atf_wgt3.atf_rdo_intra_wgt32 = bias; in setup_vepu580_rdo_bias_cfg()
1155 regs->rdo_skip_cime_thd0.atf_rdo_skip_cime_thd0 = hw->skip_sad < 10 ? hw->skip_sad : 10; in setup_vepu580_rdo_bias_cfg()
1156 regs->rdo_skip_cime_thd0.atf_rdo_skip_cime_thd1 = hw->skip_sad < 8 ? hw->skip_sad : 8; in setup_vepu580_rdo_bias_cfg()
1157 regs->rdo_skip_cime_thd1.atf_rdo_skip_cime_thd2 = hw->skip_sad < 15 ? hw->skip_sad : 15; in setup_vepu580_rdo_bias_cfg()
1158 regs->rdo_skip_cime_thd1.atf_rdo_skip_cime_thd3 = hw->skip_sad; in setup_vepu580_rdo_bias_cfg()
1159 regs->rdo_skip_atf_wgt0.atf_rdo_skip_atf_wgt00 = bias > 20 ? bias : 20; in setup_vepu580_rdo_bias_cfg()
1160 regs->rdo_skip_atf_wgt0.atf_rdo_skip_atf_wgt10 = bias; in setup_vepu580_rdo_bias_cfg()
1161 regs->rdo_skip_atf_wgt0.atf_rdo_skip_atf_wgt11 = bias; in setup_vepu580_rdo_bias_cfg()
1162 regs->rdo_skip_atf_wgt0.atf_rdo_skip_atf_wgt12 = bias; in setup_vepu580_rdo_bias_cfg()
1163 regs->rdo_skip_atf_wgt1.atf_rdo_skip_atf_wgt20 = bias; in setup_vepu580_rdo_bias_cfg()
1164 regs->rdo_skip_atf_wgt1.atf_rdo_skip_atf_wgt21 = bias; in setup_vepu580_rdo_bias_cfg()
1165 regs->rdo_skip_atf_wgt1.atf_rdo_skip_atf_wgt22 = bias; in setup_vepu580_rdo_bias_cfg()
1166 regs->rdo_skip_atf_wgt2.atf_rdo_skip_atf_wgt30 = bias; in setup_vepu580_rdo_bias_cfg()
1167 regs->rdo_skip_atf_wgt2.atf_rdo_skip_atf_wgt31 = bias; in setup_vepu580_rdo_bias_cfg()
1168 regs->rdo_skip_atf_wgt2.atf_rdo_skip_atf_wgt32 = bias; in setup_vepu580_rdo_bias_cfg()
1169 regs->rdo_skip_atf_wgt3.atf_rdo_skip_atf_wgt40 = bias; in setup_vepu580_rdo_bias_cfg()
1170 regs->rdo_skip_atf_wgt3.atf_rdo_skip_atf_wgt41 = bias; in setup_vepu580_rdo_bias_cfg()
1171 regs->rdo_skip_atf_wgt3.atf_rdo_skip_atf_wgt42 = bias; in setup_vepu580_rdo_bias_cfg()
1175 static void setup_vepu580_rdo_cfg(Vepu580RdoCfg *regs) in setup_vepu580_rdo_cfg() argument
1180 regs->rdo_sqi_cfg.atf_pskip_en = 1; in setup_vepu580_rdo_cfg()
1183 regs->rdo_intra_cime_thd0.atf_rdo_intra_cime_thd0 = 28; in setup_vepu580_rdo_cfg()
1184 regs->rdo_intra_cime_thd0.atf_rdo_intra_cime_thd1 = 44; in setup_vepu580_rdo_cfg()
1185 regs->rdo_intra_cime_thd1.atf_rdo_intra_cime_thd2 = 72; in setup_vepu580_rdo_cfg()
1188 regs->rdo_intra_var_thd0.atf_rdo_intra_var_thd00 = 25; in setup_vepu580_rdo_cfg()
1189 regs->rdo_intra_var_thd0.atf_rdo_intra_var_thd01 = 64; in setup_vepu580_rdo_cfg()
1190 regs->rdo_intra_var_thd1.atf_rdo_intra_var_thd10 = 25; in setup_vepu580_rdo_cfg()
1191 regs->rdo_intra_var_thd1.atf_rdo_intra_var_thd11 = 64; in setup_vepu580_rdo_cfg()
1192 regs->rdo_intra_var_thd2.atf_rdo_intra_var_thd20 = 70; in setup_vepu580_rdo_cfg()
1193 regs->rdo_intra_var_thd2.atf_rdo_intra_var_thd21 = 100; in setup_vepu580_rdo_cfg()
1194 regs->rdo_intra_var_thd3.atf_rdo_intra_var_thd30 = 70; in setup_vepu580_rdo_cfg()
1195 regs->rdo_intra_var_thd3.atf_rdo_intra_var_thd31 = 100; in setup_vepu580_rdo_cfg()
1198 regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt00 = 24; in setup_vepu580_rdo_cfg()
1199 regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt01 = 22; in setup_vepu580_rdo_cfg()
1200 regs->rdo_intra_atf_wgt0.atf_rdo_intra_wgt02 = 21; in setup_vepu580_rdo_cfg()
1201 regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt10 = 22; in setup_vepu580_rdo_cfg()
1202 regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt11 = 21; in setup_vepu580_rdo_cfg()
1203 regs->rdo_intra_atf_wgt1.atf_rdo_intra_wgt12 = 20; in setup_vepu580_rdo_cfg()
1204 regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt20 = 20; in setup_vepu580_rdo_cfg()
1205 regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt21 = 19; in setup_vepu580_rdo_cfg()
1206 regs->rdo_intra_atf_wgt2.atf_rdo_intra_wgt22 = 18; in setup_vepu580_rdo_cfg()
1207 regs->rdo_intra_atf_wgt3.atf_rdo_intra_wgt30 = 16; in setup_vepu580_rdo_cfg()
1208 regs->rdo_intra_atf_wgt3.atf_rdo_intra_wgt31 = 16; in setup_vepu580_rdo_cfg()
1209 regs->rdo_intra_atf_wgt3.atf_rdo_intra_wgt32 = 16; in setup_vepu580_rdo_cfg()
1212 regs->rdo_skip_cime_thd0.atf_rdo_skip_cime_thd0 = 10; in setup_vepu580_rdo_cfg()
1213 regs->rdo_skip_cime_thd0.atf_rdo_skip_cime_thd1 = 8; in setup_vepu580_rdo_cfg()
1214 regs->rdo_skip_cime_thd1.atf_rdo_skip_cime_thd2 = 15; in setup_vepu580_rdo_cfg()
1215 regs->rdo_skip_cime_thd1.atf_rdo_skip_cime_thd3 = 25; in setup_vepu580_rdo_cfg()
1216 regs->rdo_skip_var_thd0.atf_rdo_skip_var_thd10 = 25; in setup_vepu580_rdo_cfg()
1217 regs->rdo_skip_var_thd0.atf_rdo_skip_var_thd11 = 40; in setup_vepu580_rdo_cfg()
1218 regs->rdo_skip_var_thd1.atf_rdo_skip_var_thd20 = 25; in setup_vepu580_rdo_cfg()
1219 regs->rdo_skip_var_thd1.atf_rdo_skip_var_thd21 = 40; in setup_vepu580_rdo_cfg()
1220 regs->rdo_skip_var_thd2.atf_rdo_skip_var_thd30 = 70; in setup_vepu580_rdo_cfg()
1221 regs->rdo_skip_var_thd2.atf_rdo_skip_var_thd31 = 100; in setup_vepu580_rdo_cfg()
1222 regs->rdo_skip_var_thd3.atf_rdo_skip_var_thd40 = 70; in setup_vepu580_rdo_cfg()
1223 regs->rdo_skip_var_thd3.atf_rdo_skip_var_thd41 = 100; in setup_vepu580_rdo_cfg()
1226 regs->rdo_skip_atf_wgt0.atf_rdo_skip_atf_wgt00 = 20; in setup_vepu580_rdo_cfg()
1227 regs->rdo_skip_atf_wgt0.atf_rdo_skip_atf_wgt10 = 16; in setup_vepu580_rdo_cfg()
1228 regs->rdo_skip_atf_wgt0.atf_rdo_skip_atf_wgt11 = 16; in setup_vepu580_rdo_cfg()
1229 regs->rdo_skip_atf_wgt0.atf_rdo_skip_atf_wgt12 = 16; in setup_vepu580_rdo_cfg()
1230 regs->rdo_skip_atf_wgt1.atf_rdo_skip_atf_wgt20 = 16; in setup_vepu580_rdo_cfg()
1231 regs->rdo_skip_atf_wgt1.atf_rdo_skip_atf_wgt21 = 16; in setup_vepu580_rdo_cfg()
1232 regs->rdo_skip_atf_wgt1.atf_rdo_skip_atf_wgt22 = 16; in setup_vepu580_rdo_cfg()
1233 regs->rdo_skip_atf_wgt2.atf_rdo_skip_atf_wgt30 = 16; in setup_vepu580_rdo_cfg()
1234 regs->rdo_skip_atf_wgt2.atf_rdo_skip_atf_wgt31 = 16; in setup_vepu580_rdo_cfg()
1235 regs->rdo_skip_atf_wgt2.atf_rdo_skip_atf_wgt32 = 16; in setup_vepu580_rdo_cfg()
1236 regs->rdo_skip_atf_wgt3.atf_rdo_skip_atf_wgt40 = 16; in setup_vepu580_rdo_cfg()
1237 regs->rdo_skip_atf_wgt3.atf_rdo_skip_atf_wgt41 = 16; in setup_vepu580_rdo_cfg()
1238 regs->rdo_skip_atf_wgt3.atf_rdo_skip_atf_wgt42 = 16; in setup_vepu580_rdo_cfg()
1243 static void setup_vepu580_rc_base(HalVepu580RegSet *regs, HalH264eVepu580Ctx *ctx, EncRcTask *rc_ta… in setup_vepu580_rc_base() argument
1267 regs->reg_rc_klut.roi_qthd0.qpmin_area0 = qp_min; in setup_vepu580_rc_base()
1268 regs->reg_rc_klut.roi_qthd0.qpmax_area0 = qp_max; in setup_vepu580_rc_base()
1269 regs->reg_rc_klut.roi_qthd0.qpmin_area1 = qp_min; in setup_vepu580_rc_base()
1270 regs->reg_rc_klut.roi_qthd0.qpmax_area1 = qp_max; in setup_vepu580_rc_base()
1271 regs->reg_rc_klut.roi_qthd0.qpmin_area2 = qp_min; in setup_vepu580_rc_base()
1273 regs->reg_rc_klut.roi_qthd1.qpmax_area2 = qp_max; in setup_vepu580_rc_base()
1274 regs->reg_rc_klut.roi_qthd1.qpmin_area3 = qp_min; in setup_vepu580_rc_base()
1275 regs->reg_rc_klut.roi_qthd1.qpmax_area3 = qp_max; in setup_vepu580_rc_base()
1276 regs->reg_rc_klut.roi_qthd1.qpmin_area4 = qp_min; in setup_vepu580_rc_base()
1277 regs->reg_rc_klut.roi_qthd1.qpmax_area4 = qp_max; in setup_vepu580_rc_base()
1279 regs->reg_rc_klut.roi_qthd2.qpmin_area5 = qp_min; in setup_vepu580_rc_base()
1280 regs->reg_rc_klut.roi_qthd2.qpmax_area5 = qp_max; in setup_vepu580_rc_base()
1281 regs->reg_rc_klut.roi_qthd2.qpmin_area6 = qp_min; in setup_vepu580_rc_base()
1282 regs->reg_rc_klut.roi_qthd2.qpmax_area6 = qp_max; in setup_vepu580_rc_base()
1283 regs->reg_rc_klut.roi_qthd2.qpmin_area7 = qp_min; in setup_vepu580_rc_base()
1285 regs->reg_rc_klut.roi_qthd3.qpmax_area7 = qp_max; in setup_vepu580_rc_base()
1286 regs->reg_rc_klut.roi_qthd3.qpmap_mode = qpmap_mode; in setup_vepu580_rc_base()
1289 regs->reg_base.enc_pic.pic_qp = qp_target; in setup_vepu580_rc_base()
1290 regs->reg_base.rc_qp.rc_max_qp = qp_target; in setup_vepu580_rc_base()
1291 regs->reg_base.rc_qp.rc_min_qp = qp_target; in setup_vepu580_rc_base()
1303 regs->reg_base.enc_pic.pic_qp = qp_target; in setup_vepu580_rc_base()
1304 regs->reg_base.rc_cfg.rc_en = 1; in setup_vepu580_rc_base()
1305 regs->reg_base.rc_cfg.aq_en = 1; in setup_vepu580_rc_base()
1306 regs->reg_base.rc_cfg.aq_mode = 0; in setup_vepu580_rc_base()
1307 regs->reg_base.rc_cfg.rc_ctu_num = mb_w; in setup_vepu580_rc_base()
1308 regs->reg_base.rc_qp.rc_qp_range = (slice->slice_type == H264_I_SLICE) ? in setup_vepu580_rc_base()
1310 regs->reg_base.rc_qp.rc_max_qp = qp_max; in setup_vepu580_rc_base()
1311 regs->reg_base.rc_qp.rc_min_qp = qp_min; in setup_vepu580_rc_base()
1312 regs->reg_base.rc_tgt.ctu_ebit = mb_target_bits_mul_16; in setup_vepu580_rc_base()
1314 regs->reg_rc_klut.rc_adj0.qp_adj0 = -2; in setup_vepu580_rc_base()
1315 regs->reg_rc_klut.rc_adj0.qp_adj1 = -1; in setup_vepu580_rc_base()
1316 regs->reg_rc_klut.rc_adj0.qp_adj2 = 0; in setup_vepu580_rc_base()
1317 regs->reg_rc_klut.rc_adj0.qp_adj3 = 1; in setup_vepu580_rc_base()
1318 regs->reg_rc_klut.rc_adj0.qp_adj4 = 2; in setup_vepu580_rc_base()
1319 regs->reg_rc_klut.rc_adj1.qp_adj5 = 0; in setup_vepu580_rc_base()
1320 regs->reg_rc_klut.rc_adj1.qp_adj6 = 0; in setup_vepu580_rc_base()
1321 regs->reg_rc_klut.rc_adj1.qp_adj7 = 0; in setup_vepu580_rc_base()
1322 regs->reg_rc_klut.rc_adj1.qp_adj8 = 1; in setup_vepu580_rc_base()
1324 regs->reg_rc_klut.rc_dthd_0_8[0] = 4 * negative_bits_thd; in setup_vepu580_rc_base()
1325 regs->reg_rc_klut.rc_dthd_0_8[1] = negative_bits_thd; in setup_vepu580_rc_base()
1326 regs->reg_rc_klut.rc_dthd_0_8[2] = positive_bits_thd; in setup_vepu580_rc_base()
1327 regs->reg_rc_klut.rc_dthd_0_8[3] = 4 * positive_bits_thd; in setup_vepu580_rc_base()
1328 regs->reg_rc_klut.rc_dthd_0_8[4] = 0x7FFFFFFF; in setup_vepu580_rc_base()
1329 regs->reg_rc_klut.rc_dthd_0_8[5] = 0x7FFFFFFF; in setup_vepu580_rc_base()
1330 regs->reg_rc_klut.rc_dthd_0_8[6] = 0x7FFFFFFF; in setup_vepu580_rc_base()
1331 regs->reg_rc_klut.rc_dthd_0_8[7] = 0x7FFFFFFF; in setup_vepu580_rc_base()
1332 regs->reg_rc_klut.rc_dthd_0_8[8] = 0x7FFFFFFF; in setup_vepu580_rc_base()
1336 regs->reg_rc_klut.md_sad_thd.md_sad_thd0 = 4; in setup_vepu580_rc_base()
1337 regs->reg_rc_klut.md_sad_thd.md_sad_thd1 = 9; in setup_vepu580_rc_base()
1338 regs->reg_rc_klut.md_sad_thd.md_sad_thd2 = 15; in setup_vepu580_rc_base()
1340 regs->reg_rc_klut.madi_thd.madi_thd0 = 4; in setup_vepu580_rc_base()
1341 regs->reg_rc_klut.madi_thd.madi_thd1 = 9; in setup_vepu580_rc_base()
1342 regs->reg_rc_klut.madi_thd.madi_thd2 = 15; in setup_vepu580_rc_base()
1346 regs->reg_base.rc_qp.rc_qp_range = 0; in setup_vepu580_rc_base()
1352 static void setup_vepu580_io_buf(HalVepu580RegSet *regs, MppDevRegOffCfgs *offsets, in setup_vepu580_io_buf() argument
1370 regs->reg_base.adr_src0 = fd_in; in setup_vepu580_io_buf()
1371 regs->reg_base.adr_src1 = fd_in; in setup_vepu580_io_buf()
1372 regs->reg_base.adr_src2 = fd_in; in setup_vepu580_io_buf()
1374 regs->reg_base.bsbb_addr = fd_out; in setup_vepu580_io_buf()
1375 regs->reg_base.bsbr_addr = fd_out; in setup_vepu580_io_buf()
1376 regs->reg_base.adr_bsbs = fd_out; in setup_vepu580_io_buf()
1377 regs->reg_base.bsbt_addr = fd_out; in setup_vepu580_io_buf()
1483 static MPP_RET setup_vepu580_intra_refresh(HalVepu580RegSet *regs, HalH264eVepu580Ctx *ctx, RK_U32 … in setup_vepu580_intra_refresh() argument
1542 regs->reg_base.me_rnge.cme_srch_v = 1; in setup_vepu580_intra_refresh()
1553 regs->reg_base.me_rnge.cme_srch_h = 1; in setup_vepu580_intra_refresh()
1563 regs->reg_base.enc_pic.roi_en = 1; in setup_vepu580_intra_refresh()
1564 regs->reg_base.roi_addr = base_cfg_fd; in setup_vepu580_intra_refresh()
1574 static void setup_vepu580_roi(HalVepu580RegSet *regs, HalH264eVepu580Ctx *ctx) in setup_vepu580_roi() argument
1590 regs->reg_base.enc_pic.roi_en = 1; in setup_vepu580_roi()
1591 regs->reg_base.roi_addr = mpp_buffer_get_fd(cfg->base_cfg_buf); in setup_vepu580_roi()
1598 regs->reg_base.roi_qp_addr = mpp_buffer_get_fd(cfg->qp_cfg_buf); in setup_vepu580_roi()
1599 regs->reg_base.roi_en.roi_qp_en = 1; in setup_vepu580_roi()
1607 regs->reg_base.qoi_amv_addr = mpp_buffer_get_fd(cfg->amv_cfg_buf); in setup_vepu580_roi()
1608 regs->reg_base.roi_en.roi_amv_en = 1; in setup_vepu580_roi()
1616 regs->reg_base.qoi_mv_addr = mpp_buffer_get_fd(cfg->mv_cfg_buf); in setup_vepu580_roi()
1617 regs->reg_base.roi_en.roi_mv_en = 1; in setup_vepu580_roi()
1627 static void setup_vepu580_recn_refr(HalH264eVepu580Ctx *ctx, HalVepu580RegSet *regs) in setup_vepu580_recn_refr() argument
1646 regs->reg_base.rfpw_h_addr = fd; in setup_vepu580_recn_refr()
1647 regs->reg_base.rfpw_b_addr = fd; in setup_vepu580_recn_refr()
1648 regs->reg_base.dspw_addr = mpp_buffer_get_fd(buf_thumb); in setup_vepu580_recn_refr()
1659 regs->reg_base.rfpr_h_addr = fd; in setup_vepu580_recn_refr()
1660 regs->reg_base.rfpr_b_addr = fd; in setup_vepu580_recn_refr()
1661 regs->reg_base.dspr_addr = mpp_buffer_get_fd(buf_thumb); in setup_vepu580_recn_refr()
1670 static void setup_vepu580_split(HalVepu580RegSet *regs, MppEncCfgSet *enc_cfg) in setup_vepu580_split() argument
1678 regs->reg_base.sli_splt.sli_splt = 0; in setup_vepu580_split()
1679 regs->reg_base.sli_splt.sli_splt_mode = 0; in setup_vepu580_split()
1680 regs->reg_base.sli_splt.sli_splt_cpst = 0; in setup_vepu580_split()
1681 regs->reg_base.sli_splt.sli_max_num_m1 = 0; in setup_vepu580_split()
1682 regs->reg_base.sli_splt.sli_flsh = 0; in setup_vepu580_split()
1683 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = 0; in setup_vepu580_split()
1685 regs->reg_base.sli_byte.sli_splt_byte = 0; in setup_vepu580_split()
1686 regs->reg_base.enc_pic.slen_fifo = 0; in setup_vepu580_split()
1689 regs->reg_base.sli_splt.sli_splt = 1; in setup_vepu580_split()
1690 regs->reg_base.sli_splt.sli_splt_mode = 0; in setup_vepu580_split()
1691 regs->reg_base.sli_splt.sli_splt_cpst = 0; in setup_vepu580_split()
1692 regs->reg_base.sli_splt.sli_max_num_m1 = 500; in setup_vepu580_split()
1693 regs->reg_base.sli_splt.sli_flsh = 1; in setup_vepu580_split()
1694 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = 0; in setup_vepu580_split()
1696 regs->reg_base.sli_byte.sli_splt_byte = cfg->split_arg; in setup_vepu580_split()
1697 regs->reg_base.enc_pic.slen_fifo = cfg->split_out ? 1 : 0; in setup_vepu580_split()
1698 regs->reg_ctl.int_en.slc_done_en = regs->reg_base.enc_pic.slen_fifo; in setup_vepu580_split()
1705 regs->reg_base.sli_splt.sli_splt = 1; in setup_vepu580_split()
1706 regs->reg_base.sli_splt.sli_splt_mode = 1; in setup_vepu580_split()
1707 regs->reg_base.sli_splt.sli_splt_cpst = 0; in setup_vepu580_split()
1708 regs->reg_base.sli_splt.sli_max_num_m1 = 500; in setup_vepu580_split()
1709 regs->reg_base.sli_splt.sli_flsh = 1; in setup_vepu580_split()
1710 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1; in setup_vepu580_split()
1712 regs->reg_base.sli_byte.sli_splt_byte = 0; in setup_vepu580_split()
1713 regs->reg_base.enc_pic.slen_fifo = cfg->split_out ? 1 : 0; in setup_vepu580_split()
1716 (regs->reg_base.enc_pic.slen_fifo && (slice_num > VEPU580_SLICE_FIFO_LEN))) in setup_vepu580_split()
1717 regs->reg_ctl.int_en.slc_done_en = 1; in setup_vepu580_split()
1728 static void calc_cime_parameter(HalVepu580RegSet *regs, H264eSps *sps) in calc_cime_parameter() argument
1730 Vepu580BaseCfg *base_regs = ®s->reg_base; in calc_cime_parameter()
1813 static void setup_vepu580_me(HalVepu580RegSet *regs, H264eSps *sps, in setup_vepu580_me() argument
1859 regs->reg_base.me_rnge.cme_srch_h = cime_blk_w_max / 4; in setup_vepu580_me()
1860 regs->reg_base.me_rnge.cme_srch_v = cime_blk_h_max / 4; in setup_vepu580_me()
1861 regs->reg_base.me_rnge.rme_srch_h = 7; in setup_vepu580_me()
1862 regs->reg_base.me_rnge.rme_srch_v = 5; in setup_vepu580_me()
1863 regs->reg_base.me_rnge.dlt_frm_num = 0; in setup_vepu580_me()
1866 regs->reg_base.me_cfg.pmv_mdst_h = 0; in setup_vepu580_me()
1867 regs->reg_base.me_cfg.pmv_mdst_v = 0; in setup_vepu580_me()
1869 regs->reg_base.me_cfg.pmv_mdst_h = 5; in setup_vepu580_me()
1870 regs->reg_base.me_cfg.pmv_mdst_v = 5; in setup_vepu580_me()
1872 …regs->reg_base.me_cfg.mv_limit = (sps->level_idc > 20) ? 2 : ((sps->level_idc >= 11) ? 1 : 0);//2; in setup_vepu580_me()
1873 regs->reg_base.me_cfg.pmv_num = 2; in setup_vepu580_me()
1874 regs->reg_base.me_cfg.rme_dis = 0; in setup_vepu580_me()
1875 regs->reg_base.me_cfg.fme_dis = 0; in setup_vepu580_me()
1876 regs->reg_base.me_cfg.lvl4_ovrd_en = 0; in setup_vepu580_me()
1878 calc_cime_parameter(regs, sps); in setup_vepu580_me()
1903 static void setup_vepu580_l2(HalVepu580RegSet *regs, H264eSlice *slice, MppEncHwCfg *hw) in setup_vepu580_l2() argument
1909 regs->reg_s3.iprd_wgt_qp_hevc_0_51[0] = 0; in setup_vepu580_l2()
1911 regs->reg_s3.iprd_wgt_qp_hevc_0_51[51] = 0; in setup_vepu580_l2()
1914 memcpy(regs->reg_s3.rdo_wgta_qp_grpa_0_51, &h264e_lambda_default[6], H264E_LAMBDA_TAB_SIZE); in setup_vepu580_l2()
1916 memcpy(regs->reg_s3.rdo_wgta_qp_grpa_0_51, &h264e_lambda_default[6], H264E_LAMBDA_TAB_SIZE); in setup_vepu580_l2()
1918 memset(regs->reg_s3.iprd_wgt_qp_hevc_0_51, 0, H264E_LAMBDA_TAB_SIZE); in setup_vepu580_l2()
1920 regs->reg_rc_klut.madi_cfg.madi_mode = 0; in setup_vepu580_l2()
1921 regs->reg_rc_klut.madi_cfg.madi_thd = 25; in setup_vepu580_l2()
1923 regs->reg_s3.lvl32_intra_CST_THD0.lvl4_intra_cst_thd0 = 1; in setup_vepu580_l2()
1924 regs->reg_s3.lvl32_intra_CST_THD0.lvl4_intra_cst_thd1 = 4; in setup_vepu580_l2()
1925 regs->reg_s3.lvl32_intra_CST_THD1.lvl4_intra_cst_thd2 = 9; in setup_vepu580_l2()
1926 regs->reg_s3.lvl32_intra_CST_THD1.lvl4_intra_cst_thd3 = 36; in setup_vepu580_l2()
1928 regs->reg_s3.lvl16_intra_CST_THD0.lvl8_intra_chrm_cst_thd0 = 1; in setup_vepu580_l2()
1929 regs->reg_s3.lvl16_intra_CST_THD0.lvl8_intra_chrm_cst_thd1 = 4; in setup_vepu580_l2()
1930 regs->reg_s3.lvl16_intra_CST_THD1.lvl8_intra_chrm_cst_thd2 = 9; in setup_vepu580_l2()
1931 regs->reg_s3.lvl16_intra_CST_THD1.lvl8_intra_chrm_cst_thd3 = 36; in setup_vepu580_l2()
1933 regs->reg_s3.lvl8_intra_CST_THD0.lvl8_intra_cst_thd0 = 1; in setup_vepu580_l2()
1934 regs->reg_s3.lvl8_intra_CST_THD0.lvl8_intra_cst_thd1 = 4; in setup_vepu580_l2()
1935 regs->reg_s3.lvl8_intra_CST_THD1.lvl8_intra_cst_thd2 = 9; in setup_vepu580_l2()
1936 regs->reg_s3.lvl8_intra_CST_THD1.lvl8_intra_cst_thd3 = 36; in setup_vepu580_l2()
1938 regs->reg_s3.lvl16_intra_UL_CST_THD.lvl16_intra_ul_cst_thld = 0; in setup_vepu580_l2()
1939 regs->reg_s3.lvl32_intra_CST_WGT0.lvl8_intra_cst_wgt0 = 48; in setup_vepu580_l2()
1940 regs->reg_s3.lvl32_intra_CST_WGT0.lvl8_intra_cst_wgt1 = 60; in setup_vepu580_l2()
1941 regs->reg_s3.lvl32_intra_CST_WGT0.lvl8_intra_cst_wgt2 = 40; in setup_vepu580_l2()
1942 regs->reg_s3.lvl32_intra_CST_WGT0.lvl8_intra_cst_wgt3 = 48; in setup_vepu580_l2()
1944 regs->reg_s3.lvl32_intra_CST_WGT1.lvl4_intra_cst_wgt0 = 48; in setup_vepu580_l2()
1945 regs->reg_s3.lvl32_intra_CST_WGT1.lvl4_intra_cst_wgt1 = 60; in setup_vepu580_l2()
1946 regs->reg_s3.lvl32_intra_CST_WGT1.lvl4_intra_cst_wgt2 = 40; in setup_vepu580_l2()
1947 regs->reg_s3.lvl32_intra_CST_WGT1.lvl4_intra_cst_wgt3 = 48; in setup_vepu580_l2()
1949 regs->reg_s3.lvl16_intra_CST_WGT0.lvl16_intra_cst_wgt0 = 48; in setup_vepu580_l2()
1950 regs->reg_s3.lvl16_intra_CST_WGT0.lvl16_intra_cst_wgt1 = 60; in setup_vepu580_l2()
1951 regs->reg_s3.lvl16_intra_CST_WGT0.lvl16_intra_cst_wgt2 = 40; in setup_vepu580_l2()
1952 regs->reg_s3.lvl16_intra_CST_WGT0.lvl16_intra_cst_wgt3 = 48; in setup_vepu580_l2()
1954 regs->reg_s3.lvl16_intra_CST_WGT1.lvl8_intra_chrm_cst_wgt0 = 36; in setup_vepu580_l2()
1955 regs->reg_s3.lvl16_intra_CST_WGT1.lvl8_intra_chrm_cst_wgt1 = 42; in setup_vepu580_l2()
1956 regs->reg_s3.lvl16_intra_CST_WGT1.lvl8_intra_chrm_cst_wgt2 = 28; in setup_vepu580_l2()
1957 regs->reg_s3.lvl16_intra_CST_WGT1.lvl8_intra_chrm_cst_wgt3 = 32; in setup_vepu580_l2()
1959 regs->reg_s3.RDO_QUANT.quant_f_bias_P = 171; in setup_vepu580_l2()
1962 regs->reg_s3.RDO_QUANT.quant_f_bias_I = 683; in setup_vepu580_l2()
1963 regs->reg_s3.ATR_THD0.atr_thd0 = 1; in setup_vepu580_l2()
1964 regs->reg_s3.ATR_THD0.atr_thd1 = 4; in setup_vepu580_l2()
1965 regs->reg_s3.ATR_THD1.atr_thd2 = 36; in setup_vepu580_l2()
1967 regs->reg_s3.RDO_QUANT.quant_f_bias_I = 583; in setup_vepu580_l2()
1968 regs->reg_s3.ATR_THD0.atr_thd0 = 4; in setup_vepu580_l2()
1969 regs->reg_s3.ATR_THD0.atr_thd1 = 16; in setup_vepu580_l2()
1970 regs->reg_s3.ATR_THD1.atr_thd2 = 81; in setup_vepu580_l2()
1972 regs->reg_s3.ATR_THD1.atr_thdqp = 45; in setup_vepu580_l2()
1975 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt0 = 16; in setup_vepu580_l2()
1976 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt1 = 16; in setup_vepu580_l2()
1977 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt2 = 16; in setup_vepu580_l2()
1979 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt0 = 22; in setup_vepu580_l2()
1980 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt1 = 21; in setup_vepu580_l2()
1981 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt2 = 20; in setup_vepu580_l2()
1983 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt0 = 20; in setup_vepu580_l2()
1984 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt1 = 18; in setup_vepu580_l2()
1985 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt2 = 16; in setup_vepu580_l2()
1987 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt0 = 25; in setup_vepu580_l2()
1988 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt1 = 20; in setup_vepu580_l2()
1989 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt2 = 16; in setup_vepu580_l2()
1991 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt0 = 25; in setup_vepu580_l2()
1992 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt1 = 20; in setup_vepu580_l2()
1993 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt2 = 18; in setup_vepu580_l2()
1995 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt0 = 25; in setup_vepu580_l2()
1996 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt1 = 20; in setup_vepu580_l2()
1997 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt2 = 16; in setup_vepu580_l2()
2002 regs->reg_s3.cime_sqi_cfg.cime_sad_mod_sel = 0; in setup_vepu580_l2()
2003 regs->reg_s3.cime_sqi_cfg.cime_sad_use_big_block = 1; in setup_vepu580_l2()
2004 regs->reg_s3.cime_sqi_cfg.cime_pmv_set_zero = 1; in setup_vepu580_l2()
2005 regs->reg_s3.cime_sqi_cfg.cime_pmv_num = 3; in setup_vepu580_l2()
2008 regs->reg_s3.cime_sqi_thd.cime_mvd_th0 = 32; in setup_vepu580_l2()
2009 regs->reg_s3.cime_sqi_thd.cime_mvd_th1 = 80; in setup_vepu580_l2()
2010 regs->reg_s3.cime_sqi_thd.cime_mvd_th2 = 128; in setup_vepu580_l2()
2013 regs->reg_s3.cime_sqi_multi0.cime_multi0 = 4; in setup_vepu580_l2()
2014 regs->reg_s3.cime_sqi_multi0.cime_multi1 = 8; in setup_vepu580_l2()
2015 regs->reg_s3.cime_sqi_multi1.cime_multi2 = 24; in setup_vepu580_l2()
2016 regs->reg_s3.cime_sqi_multi1.cime_multi3 = 24; in setup_vepu580_l2()
2022 regs->reg_s3.rime_sqi_thd.cime_sad_th0 = 50; in setup_vepu580_l2()
2023 regs->reg_s3.rime_sqi_thd.rime_mvd_th0 = 3; in setup_vepu580_l2()
2024 regs->reg_s3.rime_sqi_thd.rime_mvd_th1 = 8; in setup_vepu580_l2()
2025 regs->reg_s3.rime_sqi_multi.rime_multi0 = 4; in setup_vepu580_l2()
2026 regs->reg_s3.rime_sqi_multi.rime_multi1 = 32; in setup_vepu580_l2()
2027 regs->reg_s3.rime_sqi_multi.rime_multi2 = 128; in setup_vepu580_l2()
2030 regs->reg_s3.fme_sqi_thd0.cime_sad_pu16_th = 2; in setup_vepu580_l2()
2033 regs->reg_s3.fme_sqi_thd1.move_lambda = 1; in setup_vepu580_l2()
2038 regs->reg_rc_klut.aq_tthd[i] = hw->aq_thrd_i[i]; in setup_vepu580_l2()
2039 regs->reg_rc_klut.aq_step[i] = hw->aq_step_i[i] & 0x3f; in setup_vepu580_l2()
2043 regs->reg_rc_klut.aq_tthd[i] = hw->aq_thrd_p[i]; in setup_vepu580_l2()
2044 regs->reg_rc_klut.aq_step[i] = hw->aq_step_p[i] & 0x3f; in setup_vepu580_l2()
2051 static void setup_vepu580_ext_line_buf(HalVepu580RegSet *regs, HalH264eVepu580Ctx *ctx) in setup_vepu580_ext_line_buf() argument
2057 regs->reg_base.ebufb_addr = 0; in setup_vepu580_ext_line_buf()
2058 regs->reg_base.ebufb_addr = 0; in setup_vepu580_ext_line_buf()
2065 regs->reg_base.ebuft_addr = fd; in setup_vepu580_ext_line_buf()
2066 regs->reg_base.ebufb_addr = fd; in setup_vepu580_ext_line_buf()
2117 HalVepu580RegSet *regs = ctx->regs_set; in hal_h264e_vepu580_gen_regs() local
2131 memset(regs, 0, sizeof(*regs)); in hal_h264e_vepu580_gen_regs()
2133 setup_vepu580_normal(regs); in hal_h264e_vepu580_gen_regs()
2134 ret = setup_vepu580_prep(regs, &ctx->cfg->prep, task); in hal_h264e_vepu580_gen_regs()
2139 setup_vepu580_codec(regs, sps, pps, slice); in hal_h264e_vepu580_gen_regs()
2140 setup_vepu580_rdo_pred(regs, sps, pps, slice); in hal_h264e_vepu580_gen_regs()
2141 setup_vepu580_rdo_cfg(®s->reg_rdo); in hal_h264e_vepu580_gen_regs()
2142 setup_vepu580_rdo_bias_cfg(®s->reg_rdo, &cfg->hw); in hal_h264e_vepu580_gen_regs()
2145 memcpy(®s->reg_scl, vepu580_540_h264_flat_scl_tab, sizeof(vepu580_540_h264_flat_scl_tab)); in hal_h264e_vepu580_gen_regs()
2147 setup_vepu580_rc_base(regs, ctx, rc_task); in hal_h264e_vepu580_gen_regs()
2148 setup_vepu580_io_buf(regs, ctx->offsets, task); in hal_h264e_vepu580_gen_regs()
2149 setup_vepu580_roi(regs, ctx); in hal_h264e_vepu580_gen_regs()
2150 setup_vepu580_recn_refr(ctx, regs); in hal_h264e_vepu580_gen_regs()
2152 regs->reg_base.meiw_addr = task->md_info ? mpp_buffer_get_fd(task->md_info) : 0; in hal_h264e_vepu580_gen_regs()
2153 regs->reg_base.enc_pic.mei_stor = task->md_info ? 1 : 0; in hal_h264e_vepu580_gen_regs()
2154 regs->reg_base.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); in hal_h264e_vepu580_gen_regs()
2155 regs->reg_base.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); in hal_h264e_vepu580_gen_regs()
2157 setup_vepu580_split(regs, cfg); in hal_h264e_vepu580_gen_regs()
2158 setup_vepu580_me(regs, sps, slice); in hal_h264e_vepu580_gen_regs()
2161 setup_vepu580_intra_refresh(regs, ctx, frm_status->seq_idx % cfg->rc.gop); in hal_h264e_vepu580_gen_regs()
2171 setup_vepu580_l2(regs, slice, &cfg->hw); in hal_h264e_vepu580_gen_regs()
2172 setup_vepu580_ext_line_buf(regs, ctx); in hal_h264e_vepu580_gen_regs()
2177 vepu580_h264e_save_pass1_patch(regs, ctx); in hal_h264e_vepu580_gen_regs()
2180 vepu580_h264e_use_pass1_patch(regs, ctx); in hal_h264e_vepu580_gen_regs()
2192 HalVepu580RegSet *regs = ctx->regs_set; in hal_h264e_vepu580_start() local
2202 wr_cfg.reg = ®s->reg_ctl; in hal_h264e_vepu580_start()
2203 wr_cfg.size = sizeof(regs->reg_ctl); in hal_h264e_vepu580_start()
2209 for ( i = 0; i < sizeof(regs->reg_ctl) / sizeof(RK_U32); i++) { in hal_h264e_vepu580_start()
2221 wr_cfg.reg = ®s->reg_base; in hal_h264e_vepu580_start()
2222 wr_cfg.size = sizeof(regs->reg_base); in hal_h264e_vepu580_start()
2230 wr_cfg.reg = ®s->reg_rc_klut; in hal_h264e_vepu580_start()
2231 wr_cfg.size = sizeof(regs->reg_rc_klut); in hal_h264e_vepu580_start()
2239 wr_cfg.reg = ®s->reg_s3; in hal_h264e_vepu580_start()
2240 wr_cfg.size = sizeof(regs->reg_s3); in hal_h264e_vepu580_start()
2248 wr_cfg.reg = ®s->reg_rdo; in hal_h264e_vepu580_start()
2249 wr_cfg.size = sizeof(regs->reg_rdo); in hal_h264e_vepu580_start()
2258 wr_cfg.reg = ®s->reg_scl; in hal_h264e_vepu580_start()
2259 wr_cfg.size = sizeof(regs->reg_scl); in hal_h264e_vepu580_start()
2268 wr_cfg.reg = ®s->reg_osd; in hal_h264e_vepu580_start()
2269 wr_cfg.size = sizeof(regs->reg_osd); in hal_h264e_vepu580_start()
2284 rd_cfg.reg = ®s->reg_ctl.int_sta; in hal_h264e_vepu580_start()
2294 rd_cfg.reg = ®s->reg_st; in hal_h264e_vepu580_start()
2295 rd_cfg.size = sizeof(regs->reg_st); in hal_h264e_vepu580_start()
2317 static MPP_RET hal_h264e_vepu580_status_check(HalVepu580RegSet *regs) in hal_h264e_vepu580_status_check() argument
2321 if (regs->reg_ctl.int_sta.lkt_node_done_sta) in hal_h264e_vepu580_status_check()
2324 if (regs->reg_ctl.int_sta.enc_done_sta) in hal_h264e_vepu580_status_check()
2327 if (regs->reg_ctl.int_sta.slc_done_sta) in hal_h264e_vepu580_status_check()
2330 if (regs->reg_ctl.int_sta.sclr_done_sta) in hal_h264e_vepu580_status_check()
2333 if (regs->reg_ctl.int_sta.bsf_oflw_sta) { in hal_h264e_vepu580_status_check()
2338 if (regs->reg_ctl.int_sta.brsp_otsd_sta) { in hal_h264e_vepu580_status_check()
2343 if (regs->reg_ctl.int_sta.wbus_err_sta) { in hal_h264e_vepu580_status_check()
2348 if (regs->reg_ctl.int_sta.rbus_err_sta) { in hal_h264e_vepu580_status_check()
2353 if (regs->reg_ctl.int_sta.wdg_sta) { in hal_h264e_vepu580_status_check()
2365 HalVepu580RegSet *regs = &ctx->regs_sets[task->flags.reg_idx]; in hal_h264e_vepu580_wait() local
2419 ret = hal_h264e_vepu580_status_check(regs); in hal_h264e_vepu580_wait()
2421 task->hw_length += regs->reg_st.bs_lgth_l32; in hal_h264e_vepu580_wait()
2428 ret = hal_h264e_vepu580_status_check(regs); in hal_h264e_vepu580_wait()
2430 task->hw_length += regs->reg_st.bs_lgth_l32; in hal_h264e_vepu580_wait()
2433 mpp_packet_add_segment_info(pkt, type, offset, regs->reg_st.bs_lgth_l32); in hal_h264e_vepu580_wait()
2459 HalVepu580RegSet *regs = &ctx->regs_sets[task->flags.reg_idx]; in hal_h264e_vepu580_ret_task() local
2472 rc_info->quality_real = regs->reg_st.qp_sum / mbs; in hal_h264e_vepu580_ret_task()
2473 rc_info->madi = (!regs->reg_st.st_bnum_b16.num_b16) ? 0 : in hal_h264e_vepu580_ret_task()
2474 regs->reg_st.madi / regs->reg_st.st_bnum_b16.num_b16; in hal_h264e_vepu580_ret_task()
2475 rc_info->madp = (!regs->reg_st.st_bnum_cme.num_ctu) ? 0 : in hal_h264e_vepu580_ret_task()
2476 regs->reg_st.madp / regs->reg_st.st_bnum_cme.num_ctu; in hal_h264e_vepu580_ret_task()
2477 rc_info->iblk4_prop = (regs->reg_st.st_pnum_i4.pnum_i4 + in hal_h264e_vepu580_ret_task()
2478 regs->reg_st.st_pnum_i8.pnum_i8 + in hal_h264e_vepu580_ret_task()
2479 regs->reg_st.st_pnum_i16.pnum_i16) * 256 / mbs; in hal_h264e_vepu580_ret_task()
2481 … rc_info->sse = ((RK_S64)regs->reg_st.sse_h32 << 16) + (regs->reg_st.st_sse_bsl.sse_l16 & 0xffff); in hal_h264e_vepu580_ret_task()
2482 rc_info->lvl16_inter_num = regs->reg_st.st_pnum_p16.pnum_p16; in hal_h264e_vepu580_ret_task()
2483 rc_info->lvl8_inter_num = regs->reg_st.st_pnum_p8.pnum_p8; in hal_h264e_vepu580_ret_task()
2484 rc_info->lvl16_intra_num = regs->reg_st.st_pnum_i16.pnum_i16; in hal_h264e_vepu580_ret_task()
2485 rc_info->lvl8_intra_num = regs->reg_st.st_pnum_i8.pnum_i8; in hal_h264e_vepu580_ret_task()
2486 rc_info->lvl4_intra_num = regs->reg_st.st_pnum_i4.pnum_i4; in hal_h264e_vepu580_ret_task()