Lines Matching refs:regs
72 void *regs; member
423 static void vepu540c_h265_global_cfg_set(H265eV540cHalContext *ctx, H265eV540cRegSet *regs) in vepu540c_h265_global_cfg_set() argument
427 hevc_vepu540c_rc_roi *rc_regs = ®s->reg_rc_roi; in vepu540c_h265_global_cfg_set()
428 hevc_vepu540c_wgt *reg_wgt = ®s->reg_wgt; in vepu540c_h265_global_cfg_set()
429 vepu540c_rdo_cfg *reg_rdo = ®s->reg_rdo; in vepu540c_h265_global_cfg_set()
456 regs->reg_wgt.me_sqi_cfg.cime_pmv_num = 1; in vepu540c_h265_global_cfg_set()
457 regs->reg_wgt.me_sqi_cfg.cime_fuse = 1; in vepu540c_h265_global_cfg_set()
458 regs->reg_wgt.me_sqi_cfg.itp_mode = 0; in vepu540c_h265_global_cfg_set()
459 regs->reg_wgt.me_sqi_cfg.move_lambda = 2; in vepu540c_h265_global_cfg_set()
460 regs->reg_wgt.me_sqi_cfg.rime_lvl_mrg = 0; in vepu540c_h265_global_cfg_set()
461 regs->reg_wgt.me_sqi_cfg.rime_prelvl_en = 3; in vepu540c_h265_global_cfg_set()
462 regs->reg_wgt.me_sqi_cfg.rime_prersu_en = 3; in vepu540c_h265_global_cfg_set()
465 regs->reg_wgt.cime_mvd_th.cime_mvd_th0 = 8; in vepu540c_h265_global_cfg_set()
466 regs->reg_wgt.cime_mvd_th.cime_mvd_th1 = 20; in vepu540c_h265_global_cfg_set()
467 regs->reg_wgt.cime_mvd_th.cime_mvd_th2 = 32; in vepu540c_h265_global_cfg_set()
470 regs->reg_wgt.cime_madp_th.cime_madp_th = 16; in vepu540c_h265_global_cfg_set()
473 regs->reg_wgt.cime_multi.cime_multi0 = 8; in vepu540c_h265_global_cfg_set()
474 regs->reg_wgt.cime_multi.cime_multi1 = 12; in vepu540c_h265_global_cfg_set()
475 regs->reg_wgt.cime_multi.cime_multi2 = 16; in vepu540c_h265_global_cfg_set()
476 regs->reg_wgt.cime_multi.cime_multi3 = 20; in vepu540c_h265_global_cfg_set()
482 regs->reg_wgt.rime_mvd_th.rime_mvd_th0 = 1; in vepu540c_h265_global_cfg_set()
483 regs->reg_wgt.rime_mvd_th.rime_mvd_th1 = 2; in vepu540c_h265_global_cfg_set()
484 regs->reg_wgt.rime_mvd_th.fme_madp_th = 0; in vepu540c_h265_global_cfg_set()
487 regs->reg_wgt.rime_madp_th.rime_madp_th0 = 8; in vepu540c_h265_global_cfg_set()
488 regs->reg_wgt.rime_madp_th.rime_madp_th1 = 16; in vepu540c_h265_global_cfg_set()
491 regs->reg_wgt.rime_multi.rime_multi0 = 4; in vepu540c_h265_global_cfg_set()
492 regs->reg_wgt.rime_multi.rime_multi1 = 8; in vepu540c_h265_global_cfg_set()
493 regs->reg_wgt.rime_multi.rime_multi2 = 12; in vepu540c_h265_global_cfg_set()
496 regs->reg_wgt.cmv_st_th.cmv_th0 = 64; in vepu540c_h265_global_cfg_set()
497 regs->reg_wgt.cmv_st_th.cmv_th1 = 96; in vepu540c_h265_global_cfg_set()
498 regs->reg_wgt.cmv_st_th.cmv_th2 = 128; in vepu540c_h265_global_cfg_set()
516 ctx->regs = mpp_calloc(H265eV540cRegSet, 1); in hal_h265e_v540c_init()
559 MPP_FREE(ctx->regs); in hal_h265e_v540c_deinit()
677 static MPP_RET vepu540c_h265_set_roi_regs(H265eV540cHalContext *ctx, hevc_vepu540c_base *regs)
684 regs->reg0192_enc_pic.roi_en = 1;
685 regs->reg0178_roi_addr = mpp_dev_get_iova_address(ctx->dev, cfg->base_cfg_buf, 0);
687 regs->reg0179_roi_qp_addr = mpp_dev_get_iova_address(ctx->dev, cfg->qp_cfg_buf, 0);
688 regs->reg0228_roi_en.roi_qp_en = 1;
692 regs->reg0180_roi_amv_addr = mpp_dev_get_iova_address(ctx->dev, cfg->amv_cfg_buf, 0);
693 regs->reg0228_roi_en.roi_amv_en = 1;
697 regs->reg0181_roi_mv_addr = mpp_dev_get_iova_address(ctx->dev, cfg->mv_cfg_buf, 0);
698 regs->reg0228_roi_en.roi_mv_en = 1;
706 static MPP_RET vepu540c_h265_set_rc_regs(H265eV540cHalContext *ctx, H265eV540cRegSet *regs, HalEncT… in vepu540c_h265_set_rc_regs() argument
710 hevc_vepu540c_base *reg_base = ®s->reg_base; in vepu540c_h265_set_rc_regs()
711 hevc_vepu540c_rc_roi *reg_rc = ®s->reg_rc_roi; in vepu540c_h265_set_rc_regs()
791 static MPP_RET vepu540c_h265_set_pp_regs(H265eV540cRegSet *regs, VepuFmtCfg *fmt, MppEncPrepCfg *pr… in vepu540c_h265_set_pp_regs() argument
793 hevc_vepu540c_control_cfg *reg_ctl = ®s->reg_ctl; in vepu540c_h265_set_pp_regs()
794 hevc_vepu540c_base *reg_base = ®s->reg_base; in vepu540c_h265_set_pp_regs()
854 static void vepu540c_h265_set_slice_regs(H265eSyntax_new *syn, hevc_vepu540c_base *regs) in vepu540c_h265_set_slice_regs() argument
856 regs->reg0237_synt_sps.smpl_adpt_ofst_e = syn->pp.sample_adaptive_offset_enabled_flag; in vepu540c_h265_set_slice_regs()
857 regs->reg0237_synt_sps.num_st_ref_pic = syn->pp.num_short_term_ref_pic_sets; in vepu540c_h265_set_slice_regs()
858 regs->reg0237_synt_sps.num_lt_ref_pic = syn->pp.num_long_term_ref_pics_sps; in vepu540c_h265_set_slice_regs()
859 regs->reg0237_synt_sps.lt_ref_pic_prsnt = syn->pp.long_term_ref_pics_present_flag; in vepu540c_h265_set_slice_regs()
860 regs->reg0237_synt_sps.tmpl_mvp_e = syn->pp.sps_temporal_mvp_enabled_flag; in vepu540c_h265_set_slice_regs()
861 regs->reg0237_synt_sps.log2_max_poc_lsb = syn->pp.log2_max_pic_order_cnt_lsb_minus4; in vepu540c_h265_set_slice_regs()
862 regs->reg0237_synt_sps.strg_intra_smth = syn->pp.strong_intra_smoothing_enabled_flag; in vepu540c_h265_set_slice_regs()
864 regs->reg0238_synt_pps.dpdnt_sli_seg_en = syn->pp.dependent_slice_segments_enabled_flag; in vepu540c_h265_set_slice_regs()
865 regs->reg0238_synt_pps.out_flg_prsnt_flg = syn->pp.output_flag_present_flag; in vepu540c_h265_set_slice_regs()
866 regs->reg0238_synt_pps.num_extr_sli_hdr = syn->pp.num_extra_slice_header_bits; in vepu540c_h265_set_slice_regs()
867 regs->reg0238_synt_pps.sgn_dat_hid_en = syn->pp.sign_data_hiding_enabled_flag; in vepu540c_h265_set_slice_regs()
868 regs->reg0238_synt_pps.cbc_init_prsnt_flg = syn->pp.cabac_init_present_flag; in vepu540c_h265_set_slice_regs()
869 regs->reg0238_synt_pps.pic_init_qp = syn->pp.init_qp_minus26 + 26; in vepu540c_h265_set_slice_regs()
870 regs->reg0238_synt_pps.cu_qp_dlt_en = syn->pp.cu_qp_delta_enabled_flag; in vepu540c_h265_set_slice_regs()
871 regs->reg0238_synt_pps.chrm_qp_ofst_prsn = syn->pp.pps_slice_chroma_qp_offsets_present_flag; in vepu540c_h265_set_slice_regs()
872 … regs->reg0238_synt_pps.lp_fltr_acrs_sli = syn->pp.pps_loop_filter_across_slices_enabled_flag; in vepu540c_h265_set_slice_regs()
873 regs->reg0238_synt_pps.dblk_fltr_ovrd_en = syn->pp.deblocking_filter_override_enabled_flag; in vepu540c_h265_set_slice_regs()
874 regs->reg0238_synt_pps.lst_mdfy_prsnt_flg = syn->pp.lists_modification_present_flag; in vepu540c_h265_set_slice_regs()
875 … regs->reg0238_synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag; in vepu540c_h265_set_slice_regs()
876 regs->reg0238_synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth; in vepu540c_h265_set_slice_regs()
877 regs->reg0238_synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag; in vepu540c_h265_set_slice_regs()
879 regs->reg0239_synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg; in vepu540c_h265_set_slice_regs()
880 regs->reg0239_synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg; in vepu540c_h265_set_slice_regs()
881 regs->reg0239_synt_sli0.mrg_up_flg = syn->sp.merge_up_flag; in vepu540c_h265_set_slice_regs()
882 regs->reg0239_synt_sli0.mrg_lft_flg = syn->sp.merge_left_flag; in vepu540c_h265_set_slice_regs()
883 regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0; in vepu540c_h265_set_slice_regs()
885 regs->reg0239_synt_sli0.num_refidx_l1_act = syn->sp.num_refidx_l1_act; in vepu540c_h265_set_slice_regs()
886 regs->reg0239_synt_sli0.num_refidx_l0_act = syn->sp.num_refidx_l0_act; in vepu540c_h265_set_slice_regs()
888 regs->reg0239_synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd; in vepu540c_h265_set_slice_regs()
890 regs->reg0239_synt_sli0.sli_sao_chrm_flg = syn->sp.sli_sao_chrm_flg; in vepu540c_h265_set_slice_regs()
891 regs->reg0239_synt_sli0.sli_sao_luma_flg = syn->sp.sli_sao_luma_flg; in vepu540c_h265_set_slice_regs()
892 regs->reg0239_synt_sli0.sli_tmprl_mvp_e = syn->sp.sli_tmprl_mvp_en; in vepu540c_h265_set_slice_regs()
893 regs->reg0192_enc_pic.num_pic_tot_cur = syn->sp.tot_poc_num; in vepu540c_h265_set_slice_regs()
895 regs->reg0239_synt_sli0.pic_out_flg = syn->sp.pic_out_flg; in vepu540c_h265_set_slice_regs()
896 regs->reg0239_synt_sli0.sli_type = syn->sp.slice_type; in vepu540c_h265_set_slice_regs()
897 regs->reg0239_synt_sli0.sli_rsrv_flg = syn->sp.slice_rsrv_flg; in vepu540c_h265_set_slice_regs()
898 regs->reg0239_synt_sli0.dpdnt_sli_seg_flg = syn->sp.dpdnt_sli_seg_flg; in vepu540c_h265_set_slice_regs()
899 regs->reg0239_synt_sli0.sli_pps_id = syn->sp.sli_pps_id; in vepu540c_h265_set_slice_regs()
900 regs->reg0239_synt_sli0.no_out_pri_pic = syn->sp.no_out_pri_pic; in vepu540c_h265_set_slice_regs()
903 regs->reg0240_synt_sli1.sp_tc_ofst_div2 = syn->sp.sli_tc_ofst_div2;; in vepu540c_h265_set_slice_regs()
904 regs->reg0240_synt_sli1.sp_beta_ofst_div2 = syn->sp.sli_beta_ofst_div2; in vepu540c_h265_set_slice_regs()
905 regs->reg0240_synt_sli1.sli_lp_fltr_acrs_sli = syn->sp.sli_lp_fltr_acrs_sli; in vepu540c_h265_set_slice_regs()
906 regs->reg0240_synt_sli1.sp_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis; in vepu540c_h265_set_slice_regs()
907 regs->reg0240_synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg; in vepu540c_h265_set_slice_regs()
908 regs->reg0240_synt_sli1.sli_cb_qp_ofst = syn->sp.sli_cb_qp_ofst; in vepu540c_h265_set_slice_regs()
909 regs->reg0240_synt_sli1.max_mrg_cnd = syn->sp.max_mrg_cnd; in vepu540c_h265_set_slice_regs()
911 regs->reg0240_synt_sli1.col_ref_idx = syn->sp.col_ref_idx; in vepu540c_h265_set_slice_regs()
912 regs->reg0240_synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg; in vepu540c_h265_set_slice_regs()
913 regs->reg0241_synt_sli2.sli_poc_lsb = syn->sp.sli_poc_lsb; in vepu540c_h265_set_slice_regs()
914 regs->reg0241_synt_sli2.sli_hdr_ext_len = syn->sp.sli_hdr_ext_len; in vepu540c_h265_set_slice_regs()
918 static void vepu540c_h265_set_ref_regs(H265eSyntax_new *syn, hevc_vepu540c_base *regs) in vepu540c_h265_set_ref_regs() argument
920 regs->reg0242_synt_refm0.st_ref_pic_flg = syn->sp.st_ref_pic_flg; in vepu540c_h265_set_ref_regs()
921 regs->reg0242_synt_refm0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0; in vepu540c_h265_set_ref_regs()
922 regs->reg0242_synt_refm0.num_lt_pic = syn->sp.num_lt_pic; in vepu540c_h265_set_ref_regs()
924 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0; in vepu540c_h265_set_ref_regs()
925 regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0; in vepu540c_h265_set_ref_regs()
926 regs->reg0243_synt_refm1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0; in vepu540c_h265_set_ref_regs()
927 regs->reg0243_synt_refm1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1; in vepu540c_h265_set_ref_regs()
928 regs->reg0243_synt_refm1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2; in vepu540c_h265_set_ref_regs()
929 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0; in vepu540c_h265_set_ref_regs()
930 regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0; in vepu540c_h265_set_ref_regs()
931 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1; in vepu540c_h265_set_ref_regs()
932 regs->reg0243_synt_refm1.num_negative_pics = syn->sp.num_neg_pic; in vepu540c_h265_set_ref_regs()
933 regs->reg0243_synt_refm1.num_pos_pic = syn->sp.num_pos_pic; in vepu540c_h265_set_ref_regs()
935 regs->reg0243_synt_refm1.used_by_s0_flg = syn->sp.used_by_s0_flg; in vepu540c_h265_set_ref_regs()
936 regs->reg0244_synt_refm2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10; in vepu540c_h265_set_ref_regs()
937 regs->reg0244_synt_refm2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11; in vepu540c_h265_set_ref_regs()
938 regs->reg0245_synt_refm3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12; in vepu540c_h265_set_ref_regs()
939 regs->reg0245_synt_refm3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13; in vepu540c_h265_set_ref_regs()
941 regs->reg0246_synt_long_refm0.poc_lsb_lt1 = syn->sp.poc_lsb_lt1; in vepu540c_h265_set_ref_regs()
942 regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1; in vepu540c_h265_set_ref_regs()
943 regs->reg0246_synt_long_refm0.poc_lsb_lt2 = syn->sp.poc_lsb_lt2; in vepu540c_h265_set_ref_regs()
944 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2; in vepu540c_h265_set_ref_regs()
945 regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2; in vepu540c_h265_set_ref_regs()
946 regs->reg0240_synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0; in vepu540c_h265_set_ref_regs()
947 regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0; in vepu540c_h265_set_ref_regs()
951 …epu540c_h265_set_me_regs(H265eV540cHalContext *ctx, H265eSyntax_new *syn, hevc_vepu540c_base *regs) in vepu540c_h265_set_me_regs() argument
958 RK_S32 pic_wdt_align = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 31) / 32 ; in vepu540c_h265_set_me_regs()
961 regs->reg0220_me_rnge.cime_srch_dwnh = 15; in vepu540c_h265_set_me_regs()
962 regs->reg0220_me_rnge.cime_srch_uph = 14; in vepu540c_h265_set_me_regs()
963 regs->reg0220_me_rnge.cime_srch_rgtw = 12; in vepu540c_h265_set_me_regs()
964 regs->reg0220_me_rnge.cime_srch_lftw = 12; in vepu540c_h265_set_me_regs()
965 regs->reg0221_me_cfg.rme_srch_h = 3; in vepu540c_h265_set_me_regs()
966 regs->reg0221_me_cfg.rme_srch_v = 3; in vepu540c_h265_set_me_regs()
968 regs->reg0221_me_cfg.srgn_max_num = 72; in vepu540c_h265_set_me_regs()
969 regs->reg0221_me_cfg.cime_dist_thre = 1024; in vepu540c_h265_set_me_regs()
970 regs->reg0221_me_cfg.rme_dis = 0; in vepu540c_h265_set_me_regs()
971 regs->reg0221_me_cfg.fme_dis = 0; in vepu540c_h265_set_me_regs()
972 regs->reg0220_me_rnge.dlt_frm_num = 0x1; in vepu540c_h265_set_me_regs()
973 srch_lftw = regs->reg0220_me_rnge.cime_srch_lftw * 4; in vepu540c_h265_set_me_regs()
974 srch_rgtw = regs->reg0220_me_rnge.cime_srch_rgtw * 4; in vepu540c_h265_set_me_regs()
975 srch_uph = regs->reg0220_me_rnge.cime_srch_uph * 2; in vepu540c_h265_set_me_regs()
976 srch_dwnh = regs->reg0220_me_rnge.cime_srch_dwnh * 2; in vepu540c_h265_set_me_regs()
981 regs->reg0222_me_cach.colmv_load = 0; in vepu540c_h265_set_me_regs()
983 regs->reg0222_me_cach.colmv_load = 1; in vepu540c_h265_set_me_regs()
985 regs->reg0222_me_cach.colmv_stor = 1; in vepu540c_h265_set_me_regs()
1007 regs->reg0222_me_cach.cme_linebuf_w = pic_w / 32; in vepu540c_h265_set_me_regs()
1023 regs->reg0222_me_cach.cime_size_rama = (cur_srch_2_h + 3) / 4 * 4; in vepu540c_h265_set_me_regs()
1033 …while ((rama_size > ((cur_srch_h - ctu_2_h) * regs->reg0222_me_cach.cme_linebuf_w + (ramb_h * cur_… in vepu540c_h265_set_me_regs()
1034 && (cur_srch_h < regs->reg0222_me_cach.cime_size_rama)) { in vepu540c_h265_set_me_regs()
1048 …if (rama_size < ((cur_srch_h - ctu_2_h) * regs->reg0222_me_cach.cme_linebuf_w + (ramb_h * cur_srch… in vepu540c_h265_set_me_regs()
1052 …regs->reg0222_me_cach.cime_size_rama = ((cur_srch_h - ctu_2_h) * regs->reg0222_me_cach.cme_linebuf… in vepu540c_h265_set_me_regs()
1053 regs->reg0222_me_cach.cime_hgt_rama = cur_srch_h / 2; in vepu540c_h265_set_me_regs()
1054 regs->reg0222_me_cach.fme_prefsu_en = 1; in vepu540c_h265_set_me_regs()
1059 void vepu540c_h265_set_hw_address(H265eV540cHalContext *ctx, hevc_vepu540c_base *regs, HalEncTask *… in vepu540c_h265_set_hw_address() argument
1068 regs->reg0160_adr_src0 = mpp_buffer_get_fd(enc_task->input); in vepu540c_h265_set_hw_address()
1069 regs->reg0161_adr_src1 = regs->reg0160_adr_src0; in vepu540c_h265_set_hw_address()
1070 regs->reg0162_adr_src2 = regs->reg0160_adr_src0; in vepu540c_h265_set_hw_address()
1076 regs->reg0163_rfpw_h_addr = mpp_buffer_get_fd(recon_buf->buf[0]); in vepu540c_h265_set_hw_address()
1077 regs->reg0164_rfpw_b_addr = regs->reg0163_rfpw_h_addr; in vepu540c_h265_set_hw_address()
1080 regs->reg0165_rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]); in vepu540c_h265_set_hw_address()
1081 regs->reg0166_rfpr_b_addr = regs->reg0165_rfpr_h_addr; in vepu540c_h265_set_hw_address()
1082 regs->reg0167_cmvw_addr = mpp_buffer_get_fd(recon_buf->buf[2]); in vepu540c_h265_set_hw_address()
1083 regs->reg0168_cmvr_addr = mpp_buffer_get_fd(ref_buf->buf[2]); in vepu540c_h265_set_hw_address()
1084 regs->reg0169_dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]); in vepu540c_h265_set_hw_address()
1085 regs->reg0170_dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]); in vepu540c_h265_set_hw_address()
1090 regs->reg0192_enc_pic.mei_stor = 1; in vepu540c_h265_set_hw_address()
1091 regs->reg0171_meiw_addr = mpp_buffer_get_fd(md_info_buf); in vepu540c_h265_set_hw_address()
1093 regs->reg0192_enc_pic.mei_stor = 0; in vepu540c_h265_set_hw_address()
1094 regs->reg0171_meiw_addr = 0; in vepu540c_h265_set_hw_address()
1097 regs->reg0172_bsbt_addr = mpp_buffer_get_fd(enc_task->output); in vepu540c_h265_set_hw_address()
1099 regs->reg0173_bsbb_addr = regs->reg0172_bsbt_addr; in vepu540c_h265_set_hw_address()
1100 regs->reg0175_bsbr_addr = regs->reg0172_bsbt_addr; in vepu540c_h265_set_hw_address()
1101 regs->reg0174_adr_bsbs = regs->reg0172_bsbt_addr; in vepu540c_h265_set_hw_address()
1103 regs->reg0180_adr_rfpt_h = 0xffffffff; in vepu540c_h265_set_hw_address()
1104 regs->reg0181_adr_rfpb_h = 0; in vepu540c_h265_set_hw_address()
1105 regs->reg0182_adr_rfpt_b = 0xffffffff; in vepu540c_h265_set_hw_address()
1106 regs->reg0183_adr_rfpb_b = 0; in vepu540c_h265_set_hw_address()
1112 regs->reg0204_pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); in vepu540c_h265_set_hw_address()
1113 regs->reg0204_pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); in vepu540c_h265_set_hw_address()
1116 static void setup_vepu540c_ext_line_buf(H265eV540cHalContext *ctx, H265eV540cRegSet *regs) in setup_vepu540c_ext_line_buf() argument
1121 regs->reg_base.reg0179_adr_ebufb = fd; in setup_vepu540c_ext_line_buf()
1122 regs->reg_base.reg0178_adr_ebuft = fd; in setup_vepu540c_ext_line_buf()
1125 regs->reg_base.reg0179_adr_ebufb = 0; in setup_vepu540c_ext_line_buf()
1126 regs->reg_base.reg0178_adr_ebuft = 0; in setup_vepu540c_ext_line_buf()
1130 static void vepu540c_h265_set_split(H265eV540cRegSet *regs, MppEncCfgSet *enc_cfg, RK_U32 title_en) in vepu540c_h265_set_split() argument
1138 regs->reg_base.reg0216_sli_splt.sli_splt = 0; in vepu540c_h265_set_split()
1139 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 0; in vepu540c_h265_set_split()
1140 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0; in vepu540c_h265_set_split()
1141 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 0; in vepu540c_h265_set_split()
1142 regs->reg_base.reg0216_sli_splt.sli_flsh = 0; in vepu540c_h265_set_split()
1143 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = 0; in vepu540c_h265_set_split()
1145 regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0; in vepu540c_h265_set_split()
1146 regs->reg_base.reg0192_enc_pic.slen_fifo = 0; in vepu540c_h265_set_split()
1149 regs->reg_base.reg0216_sli_splt.sli_splt = 1; in vepu540c_h265_set_split()
1150 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 0; in vepu540c_h265_set_split()
1151 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0; in vepu540c_h265_set_split()
1152 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 500; in vepu540c_h265_set_split()
1153 regs->reg_base.reg0216_sli_splt.sli_flsh = 1; in vepu540c_h265_set_split()
1154 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = 0; in vepu540c_h265_set_split()
1156 regs->reg_base.reg0217_sli_byte.sli_splt_byte = cfg->split_arg; in vepu540c_h265_set_split()
1157 regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0; in vepu540c_h265_set_split()
1158 regs->reg_ctl.reg0008_int_en.vslc_done_en = regs->reg_base.reg0192_enc_pic.slen_fifo; in vepu540c_h265_set_split()
1170 regs->reg_base.reg0216_sli_splt.sli_splt = 1; in vepu540c_h265_set_split()
1171 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 1; in vepu540c_h265_set_split()
1172 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0; in vepu540c_h265_set_split()
1173 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 500; in vepu540c_h265_set_split()
1174 regs->reg_base.reg0216_sli_splt.sli_flsh = 1; in vepu540c_h265_set_split()
1175 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1; in vepu540c_h265_set_split()
1177 regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0; in vepu540c_h265_set_split()
1178 regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0; in vepu540c_h265_set_split()
1181 (regs->reg_base.reg0192_enc_pic.slen_fifo && (slice_num > VEPU540C_SLICE_FIFO_LEN))) in vepu540c_h265_set_split()
1182 regs->reg_ctl.reg0008_int_en.vslc_done_en = 1 ; in vepu540c_h265_set_split()
1197 H265eV540cRegSet *regs = ctx->regs; in hal_h265e_v540c_gen_regs() local
1201 hevc_vepu540c_control_cfg *reg_ctl = ®s->reg_ctl; in hal_h265e_v540c_gen_regs()
1202 hevc_vepu540c_base *reg_base = ®s->reg_base; in hal_h265e_v540c_gen_regs()
1203 hevc_vepu540c_rc_roi *reg_klut = ®s->reg_rc_roi; in hal_h265e_v540c_gen_regs()
1214 memset(regs, 0, sizeof(H265eV540cRegSet)); in hal_h265e_v540c_gen_regs()
1304 vepu540c_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep); in hal_h265e_v540c_gen_regs()
1305 vepu540c_h265_set_rc_regs(ctx, regs, task); in hal_h265e_v540c_gen_regs()
1309 setup_vepu540c_ext_line_buf(ctx, ctx->regs); in hal_h265e_v540c_gen_regs()
1310 vepu540c_h265_set_split(regs, ctx->cfg, syn->pp.tiles_enabled_flag); in hal_h265e_v540c_gen_regs()
1314 vepu540c_set_roi(®s->reg_rc_roi.roi_cfg, ctx->roi_data, in hal_h265e_v540c_gen_regs()
1317 vepu540c_h265_global_cfg_set(ctx, regs); in hal_h265e_v540c_gen_regs()
1329 RK_U32 *regs = (RK_U32*)ctx->regs; in hal_h265e_v540c_start() local
1330 H265eV540cRegSet *hw_regs = ctx->regs; in hal_h265e_v540c_start()
1354 regs = (RK_U32*)&hw_regs->reg_ctl; in hal_h265e_v540c_start()
1356 hal_h265e_dbg_ctl("ctl reg[%04x]: 0%08x\n", i * 4, regs[i]); in hal_h265e_v540c_start()
1371 regs = (RK_U32*)(&hw_regs->reg_base); in hal_h265e_v540c_start()
1373 hal_h265e_dbg_regs("hw add cfg reg[%04x]: 0%08x\n", i * 4, regs[i]); in hal_h265e_v540c_start()
1375 regs += 32; in hal_h265e_v540c_start()
1377 hal_h265e_dbg_regs("set reg[%04x]: 0%08x\n", i * 4, regs[i]); in hal_h265e_v540c_start()
1391 regs = (RK_U32*)&hw_regs->reg_rc_roi; in hal_h265e_v540c_start()
1393 hal_h265e_dbg_rckut("set reg[%04x]: 0%08x\n", i * 4, regs[i]); in hal_h265e_v540c_start()
1408 regs = (RK_U32*)&hw_regs->reg_wgt; in hal_h265e_v540c_start()
1410 hal_h265e_dbg_wgt("set reg[%04x]: 0%08x\n", i * 4, regs[i]); in hal_h265e_v540c_start()