67 #define SET_REF_INFO(regs, index, field, value)\  argument
70         case 0: regs.reg99.ref0_##field = value; break;\
71         case 1: regs.reg99.ref1_##field = value; break;\
72         case 2: regs.reg99.ref2_##field = value; break;\
73         case 3: regs.reg99.ref3_##field = value; break;\
74         case 4: regs.reg100.ref4_##field = value; break;\
75         case 5: regs.reg100.ref5_##field = value; break;\
76         case 6: regs.reg100.ref6_##field = value; break;\
77         case 7: regs.reg100.ref7_##field = value; break;\
78         case 8: regs.reg101.ref8_##field = value; break;\
79         case 9: regs.reg101.ref9_##field = value; break;\
80         case 10: regs.reg101.ref10_##field = value; break;\
81         case 11: regs.reg101.ref11_##field = value; break;\
82         case 12: regs.reg102.ref12_##field = value; break;\
83         case 13: regs.reg102.ref13_##field = value; break;\
84         case 14: regs.reg102.ref14_##field = value; break;\
85         case 15: regs.reg102.ref15_##field = value; break;\
89 #define SET_POC_HIGNBIT_INFO(regs, index, field, value)\  argument
92         case 0: regs.reg200.ref0_##field = value; break;\
93         case 1: regs.reg200.ref1_##field = value; break;\
94         case 2: regs.reg200.ref2_##field = value; break;\
95         case 3: regs.reg200.ref3_##field = value; break;\
96         case 4: regs.reg200.ref4_##field = value; break;\
97         case 5: regs.reg200.ref5_##field = value; break;\
98         case 6: regs.reg200.ref6_##field = value; break;\
99         case 7: regs.reg200.ref7_##field = value; break;\
100         case 8: regs.reg201.ref8_##field = value; break;\
101         case 9: regs.reg201.ref9_##field = value; break;\
102         case 10: regs.reg201.ref10_##field = value; break;\
103         case 11: regs.reg201.ref11_##field = value; break;\
104         case 12: regs.reg201.ref12_##field = value; break;\
105         case 13: regs.reg201.ref13_##field = value; break;\
106         case 14: regs.reg201.ref14_##field = value; break;\
107         case 15: regs.reg201.ref15_##field = value; break;\
108         case 16: regs.reg202.ref16_##field = value; break;\
109         case 17: regs.reg202.ref17_##field = value; break;\
110         case 18: regs.reg202.ref18_##field = value; break;\
111         case 19: regs.reg202.ref19_##field = value; break;\
112         case 20: regs.reg202.ref20_##field = value; break;\
113         case 21: regs.reg202.ref21_##field = value; break;\
114         case 22: regs.reg202.ref22_##field = value; break;\
115         case 23: regs.reg202.ref23_##field = value; break;\
116         case 24: regs.reg203.ref24_##field = value; break;\
117         case 25: regs.reg203.ref25_##field = value; break;\
118         case 26: regs.reg203.ref26_##field = value; break;\
119         case 27: regs.reg203.ref27_##field = value; break;\
120         case 28: regs.reg203.ref28_##field = value; break;\
121         case 29: regs.reg203.ref29_##field = value; break;\
122         case 30: regs.reg203.ref30_##field = value; break;\
123         case 31: regs.reg203.ref31_##field = value; break;\
131     Vdpu382H264dRegSet  *regs;  member
169     Vdpu382H264dRegSet  *regs;  member
538 static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu382H264dRegSet *regs, HalTaskInfo *task)  in set_registers()  argument
542     Vdpu382RegCommon *common = &regs->common;  in set_registers()
546     memset(&regs->h264d_highpoc, 0, sizeof(regs->h264d_highpoc));  in set_registers()
586         regs->h264d_param.reg65.cur_top_poc = pp->CurrFieldOrderCnt[0];  in set_registers()
587         regs->h264d_param.reg66.cur_bot_poc = pp->CurrFieldOrderCnt[1];  in set_registers()
590         regs->common_addr.reg130_decout_base = fd;  in set_registers()
594         regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);  in set_registers()
595         regs->common_addr.reg132_error_ref_base = fd;  in set_registers()
597 …       regs->h264d_highpoc.reg204.cur_poc_highbit = 1 << pp->CurrPic.AssociatedFlag; // top:1 bot:2  in set_registers()
599             regs->h264d_highpoc.reg204.cur_poc_highbit = 0; // frame  in set_registers()
617             regs->h264d_param.reg67_98_ref_poc[2 * i] = pp->FieldOrderCntList[i][0];  in set_registers()
618             regs->h264d_param.reg67_98_ref_poc[2 * i + 1] = pp->FieldOrderCntList[i][1];  in set_registers()
619             SET_REF_INFO(regs->h264d_param, i, field, field_flag);  in set_registers()
620             SET_REF_INFO(regs->h264d_param, i, topfield_used, top_used);  in set_registers()
621             SET_REF_INFO(regs->h264d_param, i, botfield_used, bot_used);  in set_registers()
622 …        SET_REF_INFO(regs->h264d_param, i, colmv_use_flag, (pp->RefPicColmvUsedFlags >> i) & 0x01);  in set_registers()
633                 SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i, poc_highbit, 3);  in set_registers()
634                 SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i + 1, poc_highbit, 3);  in set_registers()
643                 regs->common_addr.reg132_error_ref_base =  mpp_buffer_get_fd(mbuffer);  in set_registers()
655                 regs->h264d_param.reg67_98_ref_poc[2 * i] = 0;  in set_registers()
656                 regs->h264d_param.reg67_98_ref_poc[2 * i + 1] = 0;  in set_registers()
659             regs->h264d_addr.ref_base[i] = fd;  in set_registers()
661             regs->h264d_addr.colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);  in set_registers()
670         regs->common_addr.reg128_rlc_base = mpp_buffer_get_fd(mbuffer);  in set_registers()
671         regs->common_addr.reg129_rlcwrite_base = regs->common_addr.reg128_rlc_base;  in set_registers()
673         regs->h264d_addr.cabactbl_base = reg_ctx->bufs_fd;  in set_registers()
680 static MPP_RET init_common_regs(Vdpu382H264dRegSet *regs)  in init_common_regs()  argument
682     Vdpu382RegCommon *common = &regs->common;  in init_common_regs()
683     Vdpu382H264dHighPoc_t *highpoc = &regs->h264d_highpoc;  in init_common_regs()
749         reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu382H264dRegSet, 1);  in vdpu382_h264d_init()
750         init_common_regs(reg_ctx->reg_buf[i].regs);  in vdpu382_h264d_init()
757         reg_ctx->regs = reg_ctx->reg_buf[0].regs;  in vdpu382_h264d_init()
803         MPP_FREE(reg_ctx->reg_buf[i].regs);  in vdpu382_h264d_deinit()
824                                   Vdpu382H264dRegSet *regs,  in h264d_refine_rcb_size()  argument
874     if (regs->common.reg012.fbc_e) {  in h264d_refine_rcb_size()
884 static void hal_h264d_rcb_info_update(void *hal, Vdpu382H264dRegSet *regs)  in hal_h264d_rcb_info_update()  argument
903         h264d_refine_rcb_size(hal, ctx->rcb_info, regs, width, height);  in hal_h264d_rcb_info_update()
957     Vdpu382H264dRegSet *regs = ctx->regs;  in vdpu382_h264d_gen_regs()  local
971                 regs = ctx->reg_buf[i].regs;  in vdpu382_h264d_gen_regs()
986     set_registers(p_hal, regs, task);  in vdpu382_h264d_gen_regs()
1005     regs->h264d_addr.pps_base = ctx->bufs_fd;  in vdpu382_h264d_gen_regs()
1009     regs->h264d_addr.rps_base = ctx->bufs_fd;  in vdpu382_h264d_gen_regs()
1012     regs->common.reg012.scanlist_addr_valid_en = 1;  in vdpu382_h264d_gen_regs()
1015         regs->h264d_addr.scanlist_addr = ctx->bufs_fd;  in vdpu382_h264d_gen_regs()
1018         regs->h264d_addr.scanlist_addr = 0;  in vdpu382_h264d_gen_regs()
1021     hal_h264d_rcb_info_update(p_hal, regs);  in vdpu382_h264d_gen_regs()
1022     vdpu382_setup_rcb(&regs->common_addr, p_hal->dev, p_hal->fast_mode ?  in vdpu382_h264d_gen_regs()
1031             regs->h264d_addr.reg198_scale_down_luma_base =  in vdpu382_h264d_gen_regs()
1032                 regs->common_addr.reg130_decout_base;  in vdpu382_h264d_gen_regs()
1033             regs->h264d_addr.reg199_scale_down_chorme_base =  in vdpu382_h264d_gen_regs()
1034                 regs->common_addr.reg130_decout_base;  in vdpu382_h264d_gen_regs()
1035             vdpu382_setup_down_scale(mframe, p_hal->dev, &regs->common);  in vdpu382_h264d_gen_regs()
1037             regs->h264d_addr.reg198_scale_down_luma_base = 0;  in vdpu382_h264d_gen_regs()
1038             regs->h264d_addr.reg199_scale_down_chorme_base = 0;  in vdpu382_h264d_gen_regs()
1039             regs->common.reg012.scale_down_en = 0;  in vdpu382_h264d_gen_regs()
1051     vdpu382_setup_statistic(&regs->common, &regs->statistic);  in vdpu382_h264d_gen_regs()
1070     Vdpu382H264dRegSet *regs = p_hal->fast_mode ?  in vdpu382_h264d_start()  local
1071                                reg_ctx->reg_buf[task->dec.reg_index].regs :  in vdpu382_h264d_start()
1072                                reg_ctx->regs;  in vdpu382_h264d_start()
1079         wr_cfg.reg = &regs->common;  in vdpu382_h264d_start()
1080         wr_cfg.size = sizeof(regs->common);  in vdpu382_h264d_start()
1089         wr_cfg.reg = &regs->h264d_param;  in vdpu382_h264d_start()
1090         wr_cfg.size = sizeof(regs->h264d_param);  in vdpu382_h264d_start()
1099         wr_cfg.reg = &regs->common_addr;  in vdpu382_h264d_start()
1100         wr_cfg.size = sizeof(regs->common_addr);  in vdpu382_h264d_start()
1109         wr_cfg.reg = &regs->h264d_addr;  in vdpu382_h264d_start()
1110         wr_cfg.size = sizeof(regs->h264d_addr);  in vdpu382_h264d_start()
1119         wr_cfg.reg = &regs->h264d_highpoc;  in vdpu382_h264d_start()
1120         wr_cfg.size = sizeof(regs->h264d_highpoc);  in vdpu382_h264d_start()
1128         wr_cfg.reg = &regs->statistic;  in vdpu382_h264d_start()
1129         wr_cfg.size = sizeof(regs->statistic);  in vdpu382_h264d_start()
1138         rd_cfg.reg = &regs->irq_status;  in vdpu382_h264d_start()
1139         rd_cfg.size = sizeof(regs->irq_status);  in vdpu382_h264d_start()
1148         rd_cfg.reg = &regs->statistic;  in vdpu382_h264d_start()
1149         rd_cfg.size = sizeof(regs->statistic);  in vdpu382_h264d_start()
1177                                  reg_ctx->reg_buf[task->dec.reg_index].regs :  in vdpu382_h264_get_ref_used()
1178                                  reg_ctx->regs;  in vdpu382_h264_get_ref_used()
1234                                  reg_ctx->reg_buf[index].regs :  in vdpu382_h264d_wait()
1235                                  reg_ctx->regs;  in vdpu382_h264d_wait()
1263         param.regs = (RK_U32 *)p_regs;  in vdpu382_h264d_wait()