1 /*
2 * Copyright 2022 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_h264d_vdpu382"
18
19 #include <stdio.h>
20 #include <stdlib.h>
21 #include <string.h>
22
23 #include "rk_type.h"
24 #include "mpp_err.h"
25 #include "mpp_mem.h"
26 #include "mpp_common.h"
27 #include "mpp_bitput.h"
28 #include "mpp_service.h"
29
30 #include "mpp_device.h"
31 #include "mpp_frame_impl.h"
32
33 #include "hal_h264d_global.h"
34 #include "hal_h264d_vdpu382.h"
35 #include "vdpu382_h264d.h"
36 #include "mpp_dec_cb_param.h"
37
38 /* Number registers for the decoder */
39 #define DEC_VDPU382_REGISTERS 276
40
41 #define VDPU382_CABAC_TAB_SIZE (928*4 + 128) /* bytes */
42 #define VDPU382_SPSPPS_SIZE (256*48 + 128) /* bytes */
43 #define VDPU382_RPS_SIZE (128 + 128 + 128) /* bytes */
44 #define VDPU382_SCALING_LIST_SIZE (6*16+2*64 + 128) /* bytes */
45 #define VDPU382_ERROR_INFO_SIZE (256*144*4) /* bytes */
46 #define H264_CTU_SIZE 16
47
48 #define VDPU382_CABAC_TAB_ALIGNED_SIZE (MPP_ALIGN(VDPU382_CABAC_TAB_SIZE, SZ_4K))
49 #define VDPU382_ERROR_INFO_ALIGNED_SIZE (0)
50 #define VDPU382_SPSPPS_ALIGNED_SIZE (MPP_ALIGN(VDPU382_SPSPPS_SIZE, SZ_4K))
51 #define VDPU382_RPS_ALIGNED_SIZE (MPP_ALIGN(VDPU382_RPS_SIZE, SZ_4K))
52 #define VDPU382_SCALING_LIST_ALIGNED_SIZE (MPP_ALIGN(VDPU382_SCALING_LIST_SIZE, SZ_4K))
53 #define VDPU382_STREAM_INFO_SET_SIZE (VDPU382_SPSPPS_ALIGNED_SIZE + \
54 VDPU382_RPS_ALIGNED_SIZE + \
55 VDPU382_SCALING_LIST_ALIGNED_SIZE)
56
57 #define VDPU382_CABAC_TAB_OFFSET (0)
58 #define VDPU382_ERROR_INFO_OFFSET (VDPU382_CABAC_TAB_OFFSET + VDPU382_CABAC_TAB_ALIGNED_SIZE)
59 #define VDPU382_STREAM_INFO_OFFSET_BASE (VDPU382_ERROR_INFO_OFFSET + VDPU382_ERROR_INFO_ALIGNED_SIZE)
60 #define VDPU382_SPSPPS_OFFSET(pos) (VDPU382_STREAM_INFO_OFFSET_BASE + (VDPU382_STREAM_INFO_SET_SIZE * pos))
61 #define VDPU382_RPS_OFFSET(pos) (VDPU382_SPSPPS_OFFSET(pos) + VDPU382_SPSPPS_ALIGNED_SIZE)
62 #define VDPU382_SCALING_LIST_OFFSET(pos) (VDPU382_RPS_OFFSET(pos) + VDPU382_RPS_ALIGNED_SIZE)
63 #define VDPU382_INFO_BUFFER_SIZE(cnt) (VDPU382_STREAM_INFO_OFFSET_BASE + (VDPU382_STREAM_INFO_SET_SIZE * cnt))
64
65 #define VDPU382_SPS_PPS_LEN (43)
66
67 #define SET_REF_INFO(regs, index, field, value)\
68 do{ \
69 switch(index){\
70 case 0: regs.reg99.ref0_##field = value; break;\
71 case 1: regs.reg99.ref1_##field = value; break;\
72 case 2: regs.reg99.ref2_##field = value; break;\
73 case 3: regs.reg99.ref3_##field = value; break;\
74 case 4: regs.reg100.ref4_##field = value; break;\
75 case 5: regs.reg100.ref5_##field = value; break;\
76 case 6: regs.reg100.ref6_##field = value; break;\
77 case 7: regs.reg100.ref7_##field = value; break;\
78 case 8: regs.reg101.ref8_##field = value; break;\
79 case 9: regs.reg101.ref9_##field = value; break;\
80 case 10: regs.reg101.ref10_##field = value; break;\
81 case 11: regs.reg101.ref11_##field = value; break;\
82 case 12: regs.reg102.ref12_##field = value; break;\
83 case 13: regs.reg102.ref13_##field = value; break;\
84 case 14: regs.reg102.ref14_##field = value; break;\
85 case 15: regs.reg102.ref15_##field = value; break;\
86 default: break;}\
87 }while(0)
88
89 #define SET_POC_HIGNBIT_INFO(regs, index, field, value)\
90 do{ \
91 switch(index){\
92 case 0: regs.reg200.ref0_##field = value; break;\
93 case 1: regs.reg200.ref1_##field = value; break;\
94 case 2: regs.reg200.ref2_##field = value; break;\
95 case 3: regs.reg200.ref3_##field = value; break;\
96 case 4: regs.reg200.ref4_##field = value; break;\
97 case 5: regs.reg200.ref5_##field = value; break;\
98 case 6: regs.reg200.ref6_##field = value; break;\
99 case 7: regs.reg200.ref7_##field = value; break;\
100 case 8: regs.reg201.ref8_##field = value; break;\
101 case 9: regs.reg201.ref9_##field = value; break;\
102 case 10: regs.reg201.ref10_##field = value; break;\
103 case 11: regs.reg201.ref11_##field = value; break;\
104 case 12: regs.reg201.ref12_##field = value; break;\
105 case 13: regs.reg201.ref13_##field = value; break;\
106 case 14: regs.reg201.ref14_##field = value; break;\
107 case 15: regs.reg201.ref15_##field = value; break;\
108 case 16: regs.reg202.ref16_##field = value; break;\
109 case 17: regs.reg202.ref17_##field = value; break;\
110 case 18: regs.reg202.ref18_##field = value; break;\
111 case 19: regs.reg202.ref19_##field = value; break;\
112 case 20: regs.reg202.ref20_##field = value; break;\
113 case 21: regs.reg202.ref21_##field = value; break;\
114 case 22: regs.reg202.ref22_##field = value; break;\
115 case 23: regs.reg202.ref23_##field = value; break;\
116 case 24: regs.reg203.ref24_##field = value; break;\
117 case 25: regs.reg203.ref25_##field = value; break;\
118 case 26: regs.reg203.ref26_##field = value; break;\
119 case 27: regs.reg203.ref27_##field = value; break;\
120 case 28: regs.reg203.ref28_##field = value; break;\
121 case 29: regs.reg203.ref29_##field = value; break;\
122 case 30: regs.reg203.ref30_##field = value; break;\
123 case 31: regs.reg203.ref31_##field = value; break;\
124 default: break;}\
125 }while(0)
126
127 #define VDPU382_FAST_REG_SET_CNT 3
128
129 typedef struct h264d_rkv_buf_t {
130 RK_U32 valid;
131 Vdpu382H264dRegSet *regs;
132 DXVA_PicEntry_H264 RefFrameList[16];
133 DXVA_PicEntry_H264 RefPicList[3][32];
134 } H264dRkvBuf_t;
135
136 typedef struct Vdpu382H264dRegCtx_t {
137 RK_U8 spspps[48];
138 RK_U8 rps[VDPU382_RPS_SIZE];
139 RK_U8 sclst[VDPU382_SCALING_LIST_SIZE];
140
141 MppBuffer bufs;
142 RK_S32 bufs_fd;
143 void *bufs_ptr;
144 RK_U32 offset_cabac;
145 RK_U32 offset_errinfo;
146 RK_U32 offset_spspps[VDPU382_FAST_REG_SET_CNT];
147 RK_U32 offset_rps[VDPU382_FAST_REG_SET_CNT];
148 RK_U32 offset_sclst[VDPU382_FAST_REG_SET_CNT];
149
150 H264dRkvBuf_t reg_buf[VDPU382_FAST_REG_SET_CNT];
151
152 RK_U32 spspps_offset;
153 RK_U32 rps_offset;
154 RK_U32 sclst_offset;
155
156 RK_S32 width;
157 RK_S32 height;
158 /* rcb buffers info */
159 RK_U32 bit_depth;
160 RK_U32 mbaff;
161 RK_U32 chroma_format_idc;
162
163 RK_S32 rcb_buf_size;
164 Vdpu382RcbInfo rcb_info[RCB_BUF_COUNT];
165 MppBuffer rcb_buf[VDPU382_FAST_REG_SET_CNT];
166
167 RK_U32 err_ref_hack;
168
169 Vdpu382H264dRegSet *regs;
170 } Vdpu382H264dRegCtx;
171
172 const RK_U32 rkv_cabac_table_v382[928] = {
173 0x3602f114, 0xf1144a03, 0x4a033602, 0x68e97fe4, 0x36ff35fa, 0x21173307,
174 0x00150217, 0x31000901, 0x390576db, 0x41f54ef3, 0x310c3e01, 0x321149fc,
175 0x2b094012, 0x431a001d, 0x68095a10, 0x68ec7fd2, 0x4ef34301, 0x3e0141f5,
176 0x5fef56fa, 0x2d093dfa, 0x51fa45fd, 0x370660f5, 0x56fb4307, 0x3a005802,
177 0x5ef64cfd, 0x45043605, 0x580051fd, 0x4afb43f9, 0x50fb4afc, 0x3a0148f9,
178 0x3f002900, 0x3f003f00, 0x560453f7, 0x48f96100, 0x3e03290d, 0x4efc2d00,
179 0x7ee560fd, 0x65e762e4, 0x52e443e9, 0x53f05eec, 0x5beb6eea, 0x5df366ee,
180 0x5cf97fe3, 0x60f959fb, 0x2efd6cf3, 0x39ff41ff, 0x4afd5df7, 0x57f85cf7,
181 0x36057ee9, 0x3b063c06, 0x30ff4506, 0x45fc4400, 0x55fe58f8, 0x4bff4efa,
182 0x36024df9, 0x44fd3205, 0x2a063201, 0x3f0151fc, 0x430046fc, 0x4cfe3902,
183 0x4004230b, 0x230b3d01, 0x180c1912, 0x240d1d0d, 0x49f95df6, 0x2e0d49fe,
184 0x64f93109, 0x35023509, 0x3dfe3505, 0x38003800, 0x3cfb3ff3, 0x39043eff,
185 0x390445fa, 0x3304270e, 0x4003440d, 0x3f093d01, 0x27103207, 0x34042c05,
186 0x3cfb300b, 0x3b003bff, 0x2c052116, 0x4eff2b0e, 0x45093c00, 0x28021c0b,
187 0x31002c03, 0x2c022e00, 0x2f003302, 0x3e022704, 0x36002e06, 0x3a023603,
188 0x33063f04, 0x35073906, 0x37063406, 0x240e2d0b, 0x52ff3508, 0x4efd3707,
189 0x1f162e0f, 0x071954ff, 0x031cf91e, 0x0020041c, 0x061eff22, 0x0920061e,
190 0x1b1a131f, 0x14251e1a, 0x4611221c, 0x3b054301, 0x1e104309, 0x23122012,
191 0x1f181d16, 0x2b122617, 0x3f0b2914, 0x40093b09, 0x59fe5eff, 0x4cfa6cf7,
192 0x2d002cfe, 0x40fd3400, 0x46fc3bfe, 0x52f84bfc, 0x4df766ef, 0x2a001803,
193 0x37003000, 0x47f93bfa, 0x57f553f4, 0x3a0177e2, 0x24ff1dfd, 0x2b022601,
194 0x3a0037fa, 0x4afd4000, 0x46005af6, 0x1f051dfc, 0x3b012a07, 0x48fd3afe,
195 0x61f551fd, 0x05083a00, 0x120e0e0a, 0x28021b0d, 0x46fd3a00, 0x55f84ffa,
196 0x6af30000, 0x57f66af0, 0x6eee72eb, 0x6eea62f2, 0x67ee6aeb, 0x6ce96beb,
197 0x60f670e6, 0x5bfb5ff4, 0x5eea5df7, 0x430956fb, 0x55f650fc, 0x3c0746ff,
198 0x3d053a09, 0x320f320c, 0x36113112, 0x2e07290a, 0x310733ff, 0x29093408,
199 0x37022f06, 0x2c0a290d, 0x35053206, 0x3f04310d, 0x45fe4006, 0x46063bfe,
200 0x1f092c0a, 0x35032b0c, 0x260a220e, 0x280d34fd, 0x2c072011, 0x320d2607,
201 0x2b1a390a, 0x0e0b0b0e, 0x0b120b09, 0xfe170915, 0xf120f120, 0xe927eb22,
202 0xe129df2a, 0xf426e42e, 0xe82d1d15, 0xe630d335, 0xed2bd541, 0x091ef627,
203 0x1b141a12, 0x52f23900, 0x61ed4bfb, 0x001b7ddd, 0xfc1f001c, 0x0822061b,
204 0x16180a1e, 0x20161321, 0x29151f1a, 0x2f172c1a, 0x470e4110, 0x3f063c08,
205 0x18154111, 0x171a1417, 0x171c201b, 0x2817181c, 0x1d1c2018, 0x39132a17,
206 0x3d163516, 0x280c560b, 0x3b0e330b, 0x47f94ffc, 0x46f745fb, 0x44f642f8,
207 0x45f449ed, 0x43f146f0, 0x46ed3eec, 0x41ea42f0, 0xfe093fec, 0xf721f71a,
208 0xfe29f927, 0x0931032d, 0x3b241b2d, 0x23f942fa, 0x2df82af9, 0x38f430fb,
209 0x3efb3cfa, 0x4cf842f8, 0x51fa55fb, 0x51f94df6, 0x49ee50ef, 0x53f64afc,
210 0x43f747f7, 0x42f83dff, 0x3b0042f2, 0xf3153b02, 0xf927f221, 0x0233fe2e,
211 0x113d063c, 0x3e2a2237, 0x00000000, 0x00000000, 0x3602f114, 0xf1144a03,
212 0x4a033602, 0x68e97fe4, 0x36ff35fa, 0x19163307, 0x00100022, 0x290409fe,
213 0x410276e3, 0x4ff347fa, 0x32093405, 0x360a46fd, 0x1613221a, 0x02390028,
214 0x451a2429, 0x65f17fd3, 0x47fa4cfc, 0x34054ff3, 0x5af34506, 0x2b083400,
215 0x52fb45fe, 0x3b0260f6, 0x57fd4b02, 0x380164fd, 0x55fa4afd, 0x51fd3b00,
216 0x5ffb56f9, 0x4dff42ff, 0x56fe4601, 0x3d0048fb, 0x3f002900, 0x3f003f00,
217 0x560453f7, 0x48f96100, 0x3e03290d, 0x33070f0d, 0x7fd95002, 0x60ef5bee,
218 0x62dd51e6, 0x61e966e8, 0x63e877e5, 0x66ee6eeb, 0x50007fdc, 0x5ef959fb,
219 0x27005cfc, 0x54f14100, 0x49fe7fdd, 0x5bf768f4, 0x37037fe1, 0x37073807,
220 0x35fd3d08, 0x4af94400, 0x67f358f7, 0x59f75bf3, 0x4cf85cf2, 0x6ee957f4,
221 0x4ef669e8, 0x63ef70ec, 0x7fba7fb2, 0x7fd27fce, 0x4efb42fc, 0x48f847fc,
222 0x37ff3b02, 0x4bfa46f9, 0x77de59f8, 0x14204bfd, 0x7fd4161e, 0x3dfb3600,
223 0x3cff3a00, 0x43f83dfd, 0x4af254e7, 0x340541fb, 0x3d003902, 0x46f545f7,
224 0x47fc3712, 0x3d073a00, 0x19122909, 0x2b052009, 0x2c002f09, 0x2e023300,
225 0x42fc2613, 0x2a0c260f, 0x59002209, 0x1c0a2d04, 0xf5211f0a, 0x0f12d534,
226 0xea23001c, 0x0022e726, 0xf420ee27, 0x0000a266, 0xfc21f138, 0xfb250a1d,
227 0xf727e333, 0xc645de34, 0xfb2cc143, 0xe3370720, 0x00000120, 0xe721241b,
228 0xe424e222, 0xe526e426, 0xf023ee22, 0xf820f222, 0x0023fa25, 0x121c0a1e,
229 0x291d191a, 0x48024b00, 0x230e4d08, 0x23111f12, 0x2d111e15, 0x2d122a14,
230 0x36101a1b, 0x38104207, 0x430a490b, 0x70e974f6, 0x3df947f1, 0x42fb3500,
231 0x50f74df5, 0x57f654f7, 0x65eb7fde, 0x35fb27fd, 0x4bf53df9, 0x5bef4df1,
232 0x6fe76be7, 0x4cf57ae4, 0x34f62cf6, 0x3af739f6, 0x45f948f0, 0x4afb45fc,
233 0x420256f7, 0x200122f7, 0x34051f0b, 0x43fe37fe, 0x59f84900, 0x04073403,
234 0x0811080a, 0x25031310, 0x49fb3dff, 0x4efc46ff, 0x7eeb0000, 0x6eec7ce9,
235 0x7ce77ee6, 0x79e569ef, 0x66ef75e5, 0x74e575e6, 0x5ff67adf, 0x5ff864f2,
236 0x72e46fef, 0x50fe59fa, 0x55f752fc, 0x48ff51f8, 0x43014005, 0x45003809,
237 0x45074501, 0x43fa45f9, 0x40fe4df0, 0x43fa3d02, 0x390240fd, 0x42fd41fd,
238 0x33093e00, 0x47fe42ff, 0x46ff4bfe, 0x3c0e48f7, 0x2f002510, 0x250b2312,
239 0x290a290c, 0x290c3002, 0x3b00290d, 0x28133203, 0x32124203, 0xfa12fa13,
240 0xf41a000e, 0xe721f01f, 0xe425ea21, 0xe22ae227, 0xdc2dd62f, 0xef29de31,
241 0xb9450920, 0xc042c13f, 0xd936b64d, 0xf629dd34, 0xff280024, 0x1a1c0e1e,
242 0x370c2517, 0xdf25410b, 0xdb28dc27, 0xdf2ee226, 0xe828e22a, 0xf426e331,
243 0xfd26f628, 0x141ffb2e, 0x2c191e1d, 0x310b300c, 0x16162d1a, 0x151b1617,
244 0x1c1a1421, 0x221b181e, 0x27192a12, 0x460c3212, 0x470e3615, 0x2019530b,
245 0x36153115, 0x51fa55fb, 0x51f94df6, 0x49ee50ef, 0x53f64afc, 0x43f747f7,
246 0x42f83dff, 0x3b0042f2, 0xf6113b02, 0xf72af320, 0x0035fb31, 0x0a440340,
247 0x392f1b42, 0x180047fb, 0x2afe24ff, 0x39f734fe, 0x41fc3ffa, 0x52f943fc,
248 0x4cfd51fd, 0x4efa48f9, 0x44f248f4, 0x4cfa46fd, 0x3efb42fb, 0x3dfc3900,
249 0x36013cf7, 0xf6113a02, 0xf72af320, 0x0035fb31, 0x0a440340, 0x392f1b42,
250 0x00000000, 0x00000000, 0x3602f114, 0xf1144a03, 0x4a033602, 0x68e97fe4,
251 0x36ff35fa, 0x101d3307, 0x000e0019, 0x3efd33f6, 0x101a63e5, 0x66e855fc,
252 0x39063905, 0x390e49ef, 0x0a142814, 0x0036001d, 0x610c2a25, 0x75ea7fe0,
253 0x55fc4afe, 0x390566e8, 0x58f25dfa, 0x37042cfa, 0x67f159f5, 0x391374eb,
254 0x54043a14, 0x3f016006, 0x6af355fb, 0x4b063f05, 0x65ff5afd, 0x4ffc3703,
255 0x61f44bfe, 0x3c0132f9, 0x3f002900, 0x3f003f00, 0x560453f7, 0x48f96100,
256 0x3e03290d, 0x58f72207, 0x7fdc7fec, 0x5ff25bef, 0x56e754e7, 0x5bef59f4,
257 0x4cf27fe1, 0x5af367ee, 0x500b7fdb, 0x54024c05, 0x37fa4e05, 0x53f23d04,
258 0x4ffb7fdb, 0x5bf568f5, 0x41007fe2, 0x48004ffe, 0x38fa5cfc, 0x47f84403,
259 0x56fc62f3, 0x52fb58f4, 0x43fc48fd, 0x59f048f8, 0x3bff45f7, 0x39044205,
260 0x47fe47fc, 0x4aff3a02, 0x45ff2cfc, 0x33f93e00, 0x2afa2ffc, 0x35fa29fd,
261 0x4ef74c08, 0x340953f5, 0x5afb4300, 0x48f14301, 0x50f84bfb, 0x40eb53eb,
262 0x40e71ff3, 0x4b095ee3, 0x4af83f11, 0x1bfe23fb, 0x41035b0d, 0x4d0845f9,
263 0x3e0342f6, 0x51ec44fd, 0x07011e00, 0x4aeb17fd, 0x7ce94210, 0xee2c2511,
264 0x7feade32, 0x2a002704, 0x1d0b2207, 0x25061f08, 0x28032a07, 0x2b0d2108,
265 0x2f04240d, 0x3a023703, 0x2c083c06, 0x2a0e2c0b, 0x38043007, 0x250d3404,
266 0x3a133109, 0x2d0c300a, 0x21144500, 0xee233f08, 0xfd1ce721, 0x001b0a18,
267 0xd434f222, 0x1113e827, 0x1d24191f, 0x0f222118, 0x4916141e, 0x1f132214,
268 0x10132c1b, 0x240f240f, 0x15191c15, 0x0c1f141e, 0x2a18101b, 0x380e5d00,
269 0x261a390f, 0x73e87fe8, 0x3ef752ea, 0x3b003500, 0x59f355f2, 0x5cf55ef3,
270 0x64eb7fe3, 0x43f439f2, 0x4df647f5, 0x58f055eb, 0x62f168e9, 0x52f67fdb,
271 0x3df830f8, 0x46f942f8, 0x4ff64bf2, 0x5cf453f7, 0x4ffc6cee, 0x4bf045ea,
272 0x3a013afe, 0x53f74ef3, 0x63f351fc, 0x26fa51f3, 0x3afa3ef3, 0x49f03bfe,
273 0x56f34cf6, 0x57f653f7, 0x7fea0000, 0x78e77fe7, 0x72ed7fe5, 0x76e775e9,
274 0x71e875e6, 0x78e176e4, 0x5ef67cdb, 0x63f666f1, 0x7fce6af3, 0x39115cfb,
275 0x5ef356fb, 0x4dfe5bf4, 0x49ff4700, 0x51f94004, 0x390f4005, 0x44004301,
276 0x440143f6, 0x40024d00, 0x4efb4400, 0x3b053707, 0x360e4102, 0x3c052c0f,
277 0x4cfe4602, 0x460c56ee, 0x46f44005, 0x3805370b, 0x41024500, 0x36054afa,
278 0x4cfa3607, 0x4dfe52f5, 0x2a194dfe, 0xf710f311, 0xeb1bf411, 0xd829e225,
279 0xd130d72a, 0xd82ee027, 0xd72ecd34, 0xed2bd934, 0xc93d0b20, 0xce3ed238,
280 0xec2dbd51, 0x0f1cfe23, 0x01270122, 0x2614111e, 0x360f2d12, 0xf0244f00,
281 0xef25f225, 0x0f220120, 0x19180f1d, 0x101f1622, 0x1c1f1223, 0x1c242921,
282 0x3e152f1b, 0x1a131f12, 0x17181824, 0x1e18101b, 0x29161d1f, 0x3c102a16,
283 0x3c0e340f, 0x7bf04e03, 0x38163515, 0x21153d19, 0x3d113213, 0x4af84efd,
284 0x48f648f7, 0x47f44bee, 0x46fb3ff5, 0x48f24bef, 0x35f843f0, 0x34f73bf2,
285 0xfe0944f5, 0xfc1ff61e, 0x0721ff21, 0x17250c1f, 0x4014261f, 0x25f947f7,
286 0x31f52cf8, 0x3bf438f6, 0x43f73ff8, 0x4ff644fa, 0x4af84efd, 0x48f648f7,
287 0x47f44bee, 0x46fb3ff5, 0x48f24bef, 0x35f843f0, 0x34f73bf2, 0xfe0944f5,
288 0xfc1ff61e, 0x0721ff21, 0x17250c1f, 0x4014261f, 0x00000000, 0x00000000,
289 0x3602f114, 0xf1144a03, 0x4a033602, 0x68e97fe4, 0x36ff35fa, 0x00003307,
290 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
291 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
292 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
293 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
294 0x3f002900, 0x3f003f00, 0x560453f7, 0x48f96100, 0x3e03290d, 0x37010b00,
295 0x7fef4500, 0x520066f3, 0x6beb4af9, 0x7fe17fe5, 0x5fee7fe8, 0x72eb7fe5,
296 0x7bef7fe2, 0x7af073f4, 0x3ff473f5, 0x54f144fe, 0x46fd68f3, 0x5af65df8,
297 0x4aff7fe2, 0x5bf961fa, 0x38fc7fec, 0x4cf952fb, 0x5df97dea, 0x4dfd57f5,
298 0x3ffc47fb, 0x54f444fc, 0x41f93ef9, 0x38053d08, 0x400142fe, 0x4efe3d00,
299 0x34073201, 0x2c00230a, 0x2d01260b, 0x2c052e00, 0x3301111f, 0x131c3207,
300 0x3e0e2110, 0x64f16cf3, 0x5bf365f3, 0x58f65ef4, 0x56f654f0, 0x57f353f9,
301 0x46015eed, 0x4afb4800, 0x66f83b12, 0x5f0064f1, 0x48024bfc, 0x47fd4bf5,
302 0x45f32e0f, 0x41003e00, 0x48f12515, 0x36103909, 0x480c3e00, 0x090f0018,
303 0x120d1908, 0x130d090f, 0x120c250a, 0x21141d06, 0x2d041e0f, 0x3e003a01,
304 0x260c3d07, 0x270f2d0b, 0x2c0d2a0b, 0x290c2d10, 0x221e310a, 0x370a2a12,
305 0x2e113311, 0xed1a5900, 0xef1aef16, 0xec1ce71e, 0xe525e921, 0xe428e921,
306 0xf521ef26, 0xfa29f128, 0x11290126, 0x031bfa1e, 0xf025161a, 0xf826fc23,
307 0x0325fd26, 0x002a0526, 0x16271023, 0x251b300e, 0x440c3c15, 0x47fd6102,
308 0x32fb2afa, 0x3efe36fd, 0x3f013a00, 0x4aff48fe, 0x43fb5bf7, 0x27fd1bfb,
309 0x2e002cfe, 0x44f840f0, 0x4dfa4ef6, 0x5cf456f6, 0x3cf637f1, 0x41fc3efa,
310 0x4cf849f4, 0x58f750f9, 0x61f56eef, 0x4ff554ec, 0x4afc49fa, 0x60f356f3,
311 0x75ed61f5, 0x21fb4ef8, 0x35fe30fc, 0x47f33efd, 0x56f44ff6, 0x61f25af3,
312 0x5dfa0000, 0x4ff854fa, 0x47ff4200, 0x3cfe3e00, 0x4bfb3bfe, 0x3afc3efd,
313 0x4fff42f7, 0x44034700, 0x3ef92c0a, 0x280e240f, 0x1d0c1b10, 0x24142c01,
314 0x2a052012, 0x3e0a3001, 0x40092e11, 0x61f568f4, 0x58f960f0, 0x55f955f8,
315 0x58f355f7, 0x4dfd4204, 0x4cfa4cfd, 0x4cff3a0a, 0x63f953ff, 0x5f025ff2,
316 0x4afb4c00, 0x4bf54600, 0x41004401, 0x3e0349f2, 0x44ff3e04, 0x370b4bf3,
317 0x460c4005, 0x1306060f, 0x0e0c1007, 0x0b0d0d12, 0x100f0f0d, 0x170d170c,
318 0x1a0e140f, 0x28112c0e, 0x11182f11, 0x16191515, 0x1d161b1f, 0x320e2313,
319 0x3f07390a, 0x52fc4dfe, 0x45095efd, 0xdd246df4, 0xe620de24, 0xe02ce225,
320 0xf122ee22, 0xf921f128, 0x0021fb23, 0x0d210226, 0x3a0d2317, 0x001afd1d,
321 0xf91f1e16, 0xfd22f123, 0xff240322, 0x0b200522, 0x0c220523, 0x1d1e0b27,
322 0x271d1a22, 0x151f4213, 0x32191f1f, 0x70ec78ef, 0x55f572ee, 0x59f25cf1,
323 0x51f147e6, 0x440050f2, 0x38e846f2, 0x32e844e9, 0xf3174af5, 0xf128f31a,
324 0x032cf231, 0x222c062d, 0x52133621, 0x17ff4bfd, 0x2b012201, 0x37fe3600,
325 0x40013d00, 0x5cf74400, 0x61f36af2, 0x5af45af1, 0x49f658ee, 0x56f24ff7,
326 0x46f649f6, 0x42fb45f6, 0x3afb40f7, 0xf6153b02, 0xf81cf518, 0x031dff1c,
327 0x1423091d, 0x430e241d, 0x00000000, 0x00000000
328 };
329
330 MPP_RET vdpu382_h264d_deinit(void *hal);
rkv_ver_align(RK_U32 val)331 static RK_U32 rkv_ver_align(RK_U32 val)
332 {
333 return MPP_ALIGN(val, 16);
334 }
335
rkv_hor_align(RK_U32 val)336 static RK_U32 rkv_hor_align(RK_U32 val)
337 {
338 return MPP_ALIGN(val, 16);
339 }
340
rkv_hor_align_256_odds(RK_U32 val)341 static RK_U32 rkv_hor_align_256_odds(RK_U32 val)
342 {
343 return (MPP_ALIGN(val, 256) | 256);
344 }
345
rkv_len_align(RK_U32 val)346 static RK_U32 rkv_len_align(RK_U32 val)
347 {
348 return (2 * MPP_ALIGN(val, 16));
349 }
350
rkv_len_align_422(RK_U32 val)351 static RK_U32 rkv_len_align_422(RK_U32 val)
352 {
353 return ((5 * MPP_ALIGN(val, 16)) / 2);
354 }
355
prepare_spspps(H264dHalCtx_t * p_hal,RK_U64 * data,RK_U32 len)356 static MPP_RET prepare_spspps(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len)
357 {
358 RK_S32 i = 0;
359 RK_S32 is_long_term = 0, voidx = 0;
360 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
361 RK_U32 tmp = 0;
362 BitputCtx_t bp;
363
364 mpp_set_bitput_ctx(&bp, data, len);
365
366 if (!p_hal->fast_mode && !pp->spspps_update) {
367 bp.index = VDPU382_SPS_PPS_LEN >> 3;
368 bp.bitpos = (VDPU382_SPS_PPS_LEN & 0x7) << 3;
369 } else {
370 //!< sps syntax
371 mpp_put_bits(&bp, -1, 13); //!< sps_id 4bit && profile_idc 8bit && constraint_set3_flag 1bit
372 mpp_put_bits(&bp, pp->chroma_format_idc, 2);
373 mpp_put_bits(&bp, pp->bit_depth_luma_minus8, 3);
374 mpp_put_bits(&bp, pp->bit_depth_chroma_minus8, 3);
375 mpp_put_bits(&bp, 0, 1); //!< qpprime_y_zero_transform_bypass_flag
376 mpp_put_bits(&bp, pp->log2_max_frame_num_minus4, 4);
377 mpp_put_bits(&bp, pp->num_ref_frames, 5);
378 mpp_put_bits(&bp, pp->pic_order_cnt_type, 2);
379 mpp_put_bits(&bp, pp->log2_max_pic_order_cnt_lsb_minus4, 4);
380 mpp_put_bits(&bp, pp->delta_pic_order_always_zero_flag, 1);
381 mpp_put_bits(&bp, (pp->wFrameWidthInMbsMinus1 + 1), 12);
382 mpp_put_bits(&bp, (pp->wFrameHeightInMbsMinus1 + 1), 12);
383 mpp_put_bits(&bp, pp->frame_mbs_only_flag, 1);
384 mpp_put_bits(&bp, pp->MbaffFrameFlag, 1);
385 mpp_put_bits(&bp, pp->direct_8x8_inference_flag, 1);
386
387 mpp_put_bits(&bp, 1, 1); //!< mvc_extension_enable
388 mpp_put_bits(&bp, (pp->num_views_minus1 + 1), 2);
389 mpp_put_bits(&bp, pp->view_id[0], 10);
390 mpp_put_bits(&bp, pp->view_id[1], 10);
391 mpp_put_bits(&bp, pp->num_anchor_refs_l0[0], 1);
392 if (pp->num_anchor_refs_l0[0]) {
393 mpp_put_bits(&bp, pp->anchor_ref_l0[0][0], 10);
394 } else {
395 mpp_put_bits(&bp, 0, 10);
396 }
397 mpp_put_bits(&bp, pp->num_anchor_refs_l1[0], 1);
398 if (pp->num_anchor_refs_l1[0]) {
399 mpp_put_bits(&bp, pp->anchor_ref_l1[0][0], 10);
400 } else {
401 mpp_put_bits(&bp, 0, 10); //!< anchor_ref_l1
402 }
403 mpp_put_bits(&bp, pp->num_non_anchor_refs_l0[0], 1);
404 if (pp->num_non_anchor_refs_l0[0]) {
405 mpp_put_bits(&bp, pp->non_anchor_ref_l0[0][0], 10);
406 } else {
407 mpp_put_bits(&bp, 0, 10); //!< non_anchor_ref_l0
408 }
409 mpp_put_bits(&bp, pp->num_non_anchor_refs_l1[0], 1);
410 if (pp->num_non_anchor_refs_l1[0]) {
411 mpp_put_bits(&bp, pp->non_anchor_ref_l1[0][0], 10);
412 } else {
413 mpp_put_bits(&bp, 0, 10);//!< non_anchor_ref_l1
414 }
415 mpp_put_align(&bp, 128, 0);
416 //!< pps syntax
417 mpp_put_bits(&bp, -1, 13); //!< pps_id 8bit && sps_id 5bit
418 mpp_put_bits(&bp, pp->entropy_coding_mode_flag, 1);
419 mpp_put_bits(&bp, pp->pic_order_present_flag, 1);
420 mpp_put_bits(&bp, pp->num_ref_idx_l0_active_minus1, 5);
421 mpp_put_bits(&bp, pp->num_ref_idx_l1_active_minus1, 5);
422 mpp_put_bits(&bp, pp->weighted_pred_flag, 1);
423 mpp_put_bits(&bp, pp->weighted_bipred_idc, 2);
424 mpp_put_bits(&bp, pp->pic_init_qp_minus26, 7);
425 mpp_put_bits(&bp, pp->pic_init_qs_minus26, 6);
426 mpp_put_bits(&bp, pp->chroma_qp_index_offset, 5);
427 mpp_put_bits(&bp, pp->deblocking_filter_control_present_flag, 1);
428 mpp_put_bits(&bp, pp->constrained_intra_pred_flag, 1);
429 mpp_put_bits(&bp, pp->redundant_pic_cnt_present_flag, 1);
430 mpp_put_bits(&bp, pp->transform_8x8_mode_flag, 1);
431 mpp_put_bits(&bp, pp->second_chroma_qp_index_offset, 5);
432 mpp_put_bits(&bp, pp->scaleing_list_enable_flag, 1);
433 mpp_put_bits(&bp, 0, 32);// scanlist buffer has another addr
434 }
435
436 //!< set dpb
437 for (i = 0; i < 16; i++) {
438 is_long_term = (pp->RefFrameList[i].bPicEntry != 0xff) ? pp->RefFrameList[i].AssociatedFlag : 0;
439 tmp |= (RK_U32)(is_long_term & 0x1) << i;
440 }
441 for (i = 0; i < 16; i++) {
442 voidx = (pp->RefFrameList[i].bPicEntry != 0xff) ? pp->RefPicLayerIdList[i] : 0;
443 tmp |= (RK_U32)(voidx & 0x1) << (i + 16);
444 }
445 mpp_put_bits(&bp, tmp, 32);
446 mpp_put_align(&bp, 64, 0);
447
448 return MPP_OK;
449 }
450
prepare_framerps(H264dHalCtx_t * p_hal,RK_U64 * data,RK_U32 len)451 static MPP_RET prepare_framerps(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len)
452 {
453 RK_S32 i = 0, j = 0;
454 RK_S32 dpb_idx = 0, voidx = 0;
455 RK_S32 dpb_valid = 0, bottom_flag = 0;
456 RK_U32 max_frame_num = 0;
457 RK_U16 frame_num_wrap = 0;
458 RK_U32 tmp = 0;
459
460 BitputCtx_t bp;
461 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
462
463 mpp_set_bitput_ctx(&bp, data, len);
464 mpp_put_align(&bp, 128, 0);
465 max_frame_num = 1 << (pp->log2_max_frame_num_minus4 + 4);
466 for (i = 0; i < 16; i++) {
467 if ((pp->NonExistingFrameFlags >> i) & 0x01) {
468 frame_num_wrap = 0;
469 } else {
470 if (pp->RefFrameList[i].AssociatedFlag) {
471 frame_num_wrap = pp->FrameNumList[i];
472 } else {
473 frame_num_wrap = (pp->FrameNumList[i] > pp->frame_num) ?
474 (pp->FrameNumList[i] - max_frame_num) : pp->FrameNumList[i];
475 }
476 }
477
478 mpp_put_bits(&bp, frame_num_wrap, 16);
479 }
480
481 mpp_put_bits(&bp, 0, 16);//!< NULL
482 tmp = 0;
483 for (i = 0; i < 16; i++) {
484 tmp |= (RK_U32)pp->RefPicLayerIdList[i] << i;
485 }
486 mpp_put_bits(&bp, tmp, 16);
487
488 for (i = 0; i < 32; i++) {
489 tmp = 0;
490 dpb_valid = (p_hal->slice_long[0].RefPicList[0][i].bPicEntry == 0xff) ? 0 : 1;
491 dpb_idx = dpb_valid ? p_hal->slice_long[0].RefPicList[0][i].Index7Bits : 0;
492 bottom_flag = dpb_valid ? p_hal->slice_long[0].RefPicList[0][i].AssociatedFlag : 0;
493 voidx = dpb_valid ? pp->RefPicLayerIdList[dpb_idx] : 0;
494 tmp |= (RK_U32)(dpb_idx | (dpb_valid << 4)) & 0x1f;
495 tmp |= (RK_U32)(bottom_flag & 0x1) << 5;
496 tmp |= (RK_U32)(voidx & 0x1) << 6;
497 mpp_put_bits(&bp, tmp, 7);
498 }
499 for (j = 1; j < 3; j++) {
500 for (i = 0; i < 32; i++) {
501 tmp = 0;
502 dpb_valid = (p_hal->slice_long[0].RefPicList[j][i].bPicEntry == 0xff) ? 0 : 1;
503 dpb_idx = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].Index7Bits : 0;
504 bottom_flag = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].AssociatedFlag : 0;
505 voidx = dpb_valid ? pp->RefPicLayerIdList[dpb_idx] : 0;
506 tmp |= (RK_U32)(dpb_idx | (dpb_valid << 4)) & 0x1f;
507 tmp |= (RK_U32)(bottom_flag & 0x1) << 5;
508 tmp |= (RK_U32)(voidx & 0x1) << 6;
509 mpp_put_bits(&bp, tmp, 7);
510 }
511 }
512 mpp_put_align(&bp, 128, 0);
513
514 return MPP_OK;
515 }
516
prepare_scanlist(H264dHalCtx_t * p_hal,RK_U8 * data,RK_U32 len)517 static MPP_RET prepare_scanlist(H264dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
518 {
519 RK_U32 i = 0, j = 0, n = 0;
520
521 if (p_hal->pp->scaleing_list_enable_flag) {
522 for (i = 0; i < 6; i++) { //!< 4x4, 6 lists
523 for (j = 0; j < 16; j++) {
524 data[n++] = p_hal->qm->bScalingLists4x4[i][j];
525 }
526 }
527 for (i = 0; i < 2; i++) { //!< 8x8, 2 lists
528 for (j = 0; j < 64; j++) {
529 data[n++] = p_hal->qm->bScalingLists8x8[i][j];
530 }
531 }
532 }
533 mpp_assert(n <= len);
534
535 return MPP_OK;
536 }
537
set_registers(H264dHalCtx_t * p_hal,Vdpu382H264dRegSet * regs,HalTaskInfo * task)538 static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu382H264dRegSet *regs, HalTaskInfo *task)
539 {
540 Vdpu382H264dRegCtx *ctx = (Vdpu382H264dRegCtx *)p_hal->reg_ctx;
541 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
542 Vdpu382RegCommon *common = ®s->common;
543 HalBuf *mv_buf = NULL;
544
545 // memset(regs, 0, sizeof(Vdpu382H264dRegSet));
546 memset(®s->h264d_highpoc, 0, sizeof(regs->h264d_highpoc));
547 common->reg016_str_len = p_hal->strm_len;
548 common->reg013.cur_pic_is_idr = p_hal->slice_long->idr_flag;
549 common->reg012.colmv_compress_en =
550 (p_hal->hw_info && p_hal->hw_info->cap_colmv_compress && pp->frame_mbs_only_flag) ? 1 : 0;
551 common->reg012.info_collect_en = 1;
552 common->reg013.h26x_error_mode = ctx->err_ref_hack ? 0 : 1;
553
554 //!< caculate the yuv_frame_size
555 {
556 MppFrame mframe = NULL;
557 RK_U32 hor_virstride = 0;
558 RK_U32 ver_virstride = 0;
559 RK_U32 y_virstride = 0;
560
561 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe);
562 hor_virstride = mpp_frame_get_hor_stride(mframe);
563 ver_virstride = mpp_frame_get_ver_stride(mframe);
564 y_virstride = hor_virstride * ver_virstride;
565
566 if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
567 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
568 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K);
569
570 common->reg012.fbc_e = 1;
571 common->reg018.y_hor_virstride = fbc_hdr_stride / 16;
572 common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;
573 common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
574 } else {
575 common->reg012.fbc_e = 0;
576 common->reg018.y_hor_virstride = hor_virstride / 16;
577 common->reg019.uv_hor_virstride = hor_virstride / 16;
578 common->reg020_y_virstride.y_virstride = y_virstride / 16;
579 }
580 }
581 //!< set current
582 {
583 MppBuffer mbuffer = NULL;
584 RK_S32 fd = -1;
585
586 regs->h264d_param.reg65.cur_top_poc = pp->CurrFieldOrderCnt[0];
587 regs->h264d_param.reg66.cur_bot_poc = pp->CurrFieldOrderCnt[1];
588 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &mbuffer);
589 fd = mpp_buffer_get_fd(mbuffer);
590 regs->common_addr.reg130_decout_base = fd;
591
592 //colmv_cur_base
593 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, pp->CurrPic.Index7Bits);
594 regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
595 regs->common_addr.reg132_error_ref_base = fd;
596 if (pp->field_pic_flag)
597 regs->h264d_highpoc.reg204.cur_poc_highbit = 1 << pp->CurrPic.AssociatedFlag; // top:1 bot:2
598 else
599 regs->h264d_highpoc.reg204.cur_poc_highbit = 0; // frame
600 }
601 //!< set reference
602 {
603 RK_S32 i = 0;
604 RK_S32 ref_index = -1;
605 RK_S32 near_index = -1;
606 MppBuffer mbuffer = NULL;
607 RK_U32 min_frame_num = 0;
608 MppFrame mframe = NULL;
609
610 task->dec.flags.ref_miss = 0;
611
612 for (i = 0; i <= 15; i++) {
613 RK_U32 field_flag = (pp->RefPicFiledFlags >> i) & 0x01;
614 RK_U32 top_used = (pp->UsedForReferenceFlags >> (2 * i + 0)) & 0x01;
615 RK_U32 bot_used = (pp->UsedForReferenceFlags >> (2 * i + 1)) & 0x01;
616
617 regs->h264d_param.reg67_98_ref_poc[2 * i] = pp->FieldOrderCntList[i][0];
618 regs->h264d_param.reg67_98_ref_poc[2 * i + 1] = pp->FieldOrderCntList[i][1];
619 SET_REF_INFO(regs->h264d_param, i, field, field_flag);
620 SET_REF_INFO(regs->h264d_param, i, topfield_used, top_used);
621 SET_REF_INFO(regs->h264d_param, i, botfield_used, bot_used);
622 SET_REF_INFO(regs->h264d_param, i, colmv_use_flag, (pp->RefPicColmvUsedFlags >> i) & 0x01);
623
624 if (pp->RefFrameList[i].bPicEntry != 0xff) {
625 ref_index = pp->RefFrameList[i].Index7Bits;
626 near_index = pp->RefFrameList[i].Index7Bits;
627 } else {
628 ref_index = (near_index < 0) ? pp->CurrPic.Index7Bits : near_index;
629 task->dec.flags.ref_miss |= (1 << i);
630 }
631 /* mark 3 to differ from current frame */
632 if (ref_index == pp->CurrPic.Index7Bits) {
633 SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i, poc_highbit, 3);
634 SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i + 1, poc_highbit, 3);
635 }
636 mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer);
637 mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_FRAME_PTR, &mframe);
638
639 if (pp->FrameNumList[i] < pp->frame_num &&
640 pp->FrameNumList[i] > min_frame_num &&
641 (!mpp_frame_get_errinfo(mframe))) {
642 min_frame_num = pp->FrameNumList[i];
643 regs->common_addr.reg132_error_ref_base = mpp_buffer_get_fd(mbuffer);
644 common->reg021.error_intra_mode = 0;
645 }
646
647 RK_S32 fd = mpp_buffer_get_fd(mbuffer);
648 /*
649 * if ref is err frame, set fd = 0,
650 * in order for trigger pagefault if the cur frame use the err ref.
651 * This makes it possible to accurately identify whether an err ref
652 * frame is being used.
653 */
654 if (ctx->err_ref_hack && mpp_frame_get_errinfo(mframe)) {
655 regs->h264d_param.reg67_98_ref_poc[2 * i] = 0;
656 regs->h264d_param.reg67_98_ref_poc[2 * i + 1] = 0;
657 fd = 0;
658 }
659 regs->h264d_addr.ref_base[i] = fd;
660 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index);
661 regs->h264d_addr.colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
662
663 }
664 }
665 {
666 MppBuffer mbuffer = NULL;
667 Vdpu382H264dRegCtx *reg_ctx = (Vdpu382H264dRegCtx *)p_hal->reg_ctx;
668
669 mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &mbuffer);
670 regs->common_addr.reg128_rlc_base = mpp_buffer_get_fd(mbuffer);
671 regs->common_addr.reg129_rlcwrite_base = regs->common_addr.reg128_rlc_base;
672
673 regs->h264d_addr.cabactbl_base = reg_ctx->bufs_fd;
674 mpp_dev_set_reg_offset(p_hal->dev, 197, reg_ctx->offset_cabac);
675 }
676
677 return MPP_OK;
678 }
679
init_common_regs(Vdpu382H264dRegSet * regs)680 static MPP_RET init_common_regs(Vdpu382H264dRegSet *regs)
681 {
682 Vdpu382RegCommon *common = ®s->common;
683 Vdpu382H264dHighPoc_t *highpoc = ®s->h264d_highpoc;
684
685 common->reg009.dec_mode = 1; //!< h264
686 common->reg015.rlc_mode = 0;
687
688 common->reg011.buf_empty_en = 1;
689 common->reg011.err_head_fill_e = 1;
690 common->reg011.err_colmv_fill_e = 1;
691
692 common->reg010.dec_e = 1;
693 common->reg017.slice_num = 0x3fff;
694
695 common->reg013.h26x_error_mode = 1;
696 common->reg013.strmd_zero_rm_en = 1;
697
698 common->reg021.error_deb_en = 1;
699 common->reg021.inter_error_prc_mode = 0;
700 common->reg021.error_intra_mode = 1;
701
702 common->reg024.cabac_err_en_lowbits = 0xffffffff;
703 common->reg025.cabac_err_en_highbits = 0x3ff3ffff;
704
705 common->reg026.inter_auto_gating_e = 1;
706 common->reg026.filterd_auto_gating_e = 1;
707 common->reg026.strmd_auto_gating_e = 1;
708 common->reg026.mcp_auto_gating_e = 1;
709 common->reg026.busifd_auto_gating_e = 1;
710 common->reg026.dec_ctrl_auto_gating_e = 1;
711 common->reg026.intra_auto_gating_e = 1;
712 common->reg026.mc_auto_gating_e = 1;
713 common->reg026.transd_auto_gating_e = 1;
714 common->reg026.sram_auto_gating_e = 1;
715 common->reg026.cru_auto_gating_e = 1;
716 common->reg026.reg_cfg_gating_en = 1;
717
718 common->reg032_timeout_threshold = 0x3ffff;
719
720 common->reg011.dec_clkgate_e = 1;
721
722 //highpoc_t205
723 memset(&highpoc->reg205, 0, sizeof(RK_U32));
724
725
726 return MPP_OK;
727 }
728
vdpu382_h264d_init(void * hal,MppHalCfg * cfg)729 MPP_RET vdpu382_h264d_init(void *hal, MppHalCfg *cfg)
730 {
731 MPP_RET ret = MPP_ERR_UNKNOW;
732 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
733
734 INP_CHECK(ret, NULL == p_hal);
735
736 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu382H264dRegCtx)));
737 Vdpu382H264dRegCtx *reg_ctx = (Vdpu382H264dRegCtx *)p_hal->reg_ctx;
738 RK_U32 max_cnt = p_hal->fast_mode ? VDPU382_FAST_REG_SET_CNT : 1;
739 RK_U32 i = 0;
740
741 //!< malloc buffers
742 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->bufs,
743 VDPU382_INFO_BUFFER_SIZE(max_cnt)));
744 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs);
745 reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs);
746 reg_ctx->offset_cabac = VDPU382_CABAC_TAB_OFFSET;
747 reg_ctx->offset_errinfo = VDPU382_ERROR_INFO_OFFSET;
748 for (i = 0; i < max_cnt; i++) {
749 reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu382H264dRegSet, 1);
750 init_common_regs(reg_ctx->reg_buf[i].regs);
751 reg_ctx->offset_spspps[i] = VDPU382_SPSPPS_OFFSET(i);
752 reg_ctx->offset_rps[i] = VDPU382_RPS_OFFSET(i);
753 reg_ctx->offset_sclst[i] = VDPU382_SCALING_LIST_OFFSET(i);
754 }
755
756 if (!p_hal->fast_mode) {
757 reg_ctx->regs = reg_ctx->reg_buf[0].regs;
758 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0];
759 reg_ctx->rps_offset = reg_ctx->offset_rps[0];
760 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0];
761 }
762
763 //!< copy cabac table bytes
764 memcpy((char *)reg_ctx->bufs_ptr + reg_ctx->offset_cabac,
765 (void *)rkv_cabac_table_v382, sizeof(rkv_cabac_table_v382));
766
767 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, rkv_hor_align);
768 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align);
769 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align);
770
771 {
772 /* check kernel support err ref hack process */
773 const MppServiceCmdCap *cap = mpp_get_mpp_service_cmd_cap();
774
775 reg_ctx->err_ref_hack = cap->ctrl_cmd > MPP_CMD_SET_ERR_REF_HACK;
776 if (reg_ctx->err_ref_hack)
777 mpp_dev_ioctl(p_hal->dev, MPP_DEV_SET_ERR_REF_HACK, ®_ctx->err_ref_hack);
778 }
779 if (cfg->hal_fbc_adj_cfg) {
780 cfg->hal_fbc_adj_cfg->func = vdpu382_afbc_align_calc;
781 cfg->hal_fbc_adj_cfg->expand = 16;
782 }
783
784 __RETURN:
785 return MPP_OK;
786 __FAILED:
787 vdpu382_h264d_deinit(hal);
788
789 return ret;
790 }
791
vdpu382_h264d_deinit(void * hal)792 MPP_RET vdpu382_h264d_deinit(void *hal)
793 {
794 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
795 Vdpu382H264dRegCtx *reg_ctx = (Vdpu382H264dRegCtx *)p_hal->reg_ctx;
796
797 RK_U32 i = 0;
798 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
799
800 mpp_buffer_put(reg_ctx->bufs);
801
802 for (i = 0; i < loop; i++)
803 MPP_FREE(reg_ctx->reg_buf[i].regs);
804
805 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1;
806 for (i = 0; i < loop; i++) {
807 if (reg_ctx->rcb_buf[i]) {
808 mpp_buffer_put(reg_ctx->rcb_buf[i]);
809 reg_ctx->rcb_buf[i] = NULL;
810 }
811 }
812
813 if (p_hal->cmv_bufs) {
814 hal_bufs_deinit(p_hal->cmv_bufs);
815 p_hal->cmv_bufs = NULL;
816 }
817
818 MPP_FREE(p_hal->reg_ctx);
819
820 return MPP_OK;
821 }
822
h264d_refine_rcb_size(H264dHalCtx_t * p_hal,Vdpu382RcbInfo * rcb_info,Vdpu382H264dRegSet * regs,RK_S32 width,RK_S32 height)823 static void h264d_refine_rcb_size(H264dHalCtx_t *p_hal, Vdpu382RcbInfo *rcb_info,
824 Vdpu382H264dRegSet *regs,
825 RK_S32 width, RK_S32 height)
826 {
827 RK_U32 rcb_bits = 0;
828 RK_U32 mbaff = p_hal->pp->MbaffFrameFlag;
829 RK_U32 bit_depth = p_hal->pp->bit_depth_luma_minus8 + 8;
830 RK_U32 chroma_format_idc = p_hal->pp->chroma_format_idc;
831
832 width = MPP_ALIGN(width, H264_CTU_SIZE);
833 height = MPP_ALIGN(height, H264_CTU_SIZE);
834
835 /* RCB_STRMD_ROW */
836 if (width >= 4096)
837 rcb_bits = ((width + 15) / 16) * 154 * (mbaff ? 2 : 1);
838 else
839 rcb_bits = 0;
840 rcb_info[RCB_STRMD_ROW].size = MPP_RCB_BYTES(rcb_bits);
841
842 /* RCB_TRANSD_ROW */
843 if (width >= 8192)
844 rcb_bits = ((width - 8192 + 3) / 4) * 2;
845 else
846 rcb_bits = 0;
847 rcb_info[RCB_TRANSD_ROW].size = MPP_RCB_BYTES(rcb_bits);
848
849 /* RCB_TRANSD_COL */
850 rcb_info[RCB_TRANSD_COL].size = 0;
851
852 /* RCB_INTER_ROW */
853 rcb_bits = width * 42;
854 rcb_info[RCB_INTER_ROW].size = MPP_RCB_BYTES(rcb_bits);
855
856 /* RCB_INTER_COL */
857 rcb_info[RCB_INTER_COL].size = 0;
858
859 /* RCB_INTRA_ROW */
860 if (mbaff)
861 rcb_bits = width * 44;
862 else
863 rcb_bits = width * ((chroma_format_idc ? 1 : 0) + 1) * 11;
864 rcb_info[RCB_INTRA_ROW].size = MPP_RCB_BYTES(rcb_bits);
865
866 /* RCB_DBLK_ROW */
867 rcb_bits = width * (2 + (mbaff ? 12 : 6) * bit_depth);
868 rcb_info[RCB_DBLK_ROW].size = MPP_RCB_BYTES(rcb_bits);
869
870 /* RCB_SAO_ROW */
871 rcb_info[RCB_SAO_ROW].size = 0;
872
873 /* RCB_FBC_ROW */
874 if (regs->common.reg012.fbc_e) {
875 rcb_bits = (chroma_format_idc > 1) ? (2 * width * bit_depth) : 0;
876 } else
877 rcb_bits = 0;
878 rcb_info[RCB_FBC_ROW].size = MPP_RCB_BYTES(rcb_bits);
879
880 /* RCB_FILT_COL */
881 rcb_info[RCB_FILT_COL].size = 0;
882 }
883
hal_h264d_rcb_info_update(void * hal,Vdpu382H264dRegSet * regs)884 static void hal_h264d_rcb_info_update(void *hal, Vdpu382H264dRegSet *regs)
885 {
886 H264dHalCtx_t *p_hal = (H264dHalCtx_t*)hal;
887 RK_U32 mbaff = p_hal->pp->MbaffFrameFlag;
888 RK_U32 bit_depth = p_hal->pp->bit_depth_luma_minus8 + 8;
889 RK_U32 chroma_format_idc = p_hal->pp->chroma_format_idc;
890 Vdpu382H264dRegCtx *ctx = (Vdpu382H264dRegCtx *)p_hal->reg_ctx;
891 RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);
892 RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);
893
894 if ( ctx->bit_depth != bit_depth ||
895 ctx->chroma_format_idc != chroma_format_idc ||
896 ctx->mbaff != mbaff ||
897 ctx->width != width ||
898 ctx->height != height) {
899 RK_U32 i;
900 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(ctx->reg_buf) : 1;
901
902 ctx->rcb_buf_size = vdpu382_get_rcb_buf_size(ctx->rcb_info, width, height);
903 h264d_refine_rcb_size(hal, ctx->rcb_info, regs, width, height);
904 for (i = 0; i < loop; i++) {
905 MppBuffer rcb_buf = ctx->rcb_buf[i];
906
907 if (rcb_buf) {
908 mpp_buffer_put(rcb_buf);
909 ctx->rcb_buf[i] = NULL;
910 }
911 mpp_buffer_get(p_hal->buf_group, &rcb_buf, ctx->rcb_buf_size);
912 ctx->rcb_buf[i] = rcb_buf;
913 }
914 ctx->bit_depth = bit_depth;
915 ctx->width = width;
916 ctx->height = height;
917 ctx->mbaff = mbaff;
918 ctx->chroma_format_idc = chroma_format_idc;
919 }
920 }
921
vdpu382_h264d_setup_colmv_buf(void * hal)922 static MPP_RET vdpu382_h264d_setup_colmv_buf(void *hal)
923 {
924 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
925 RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);
926 RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);
927 RK_U32 ctu_size = 16, colmv_size = 4, colmv_byte = 16;
928 RK_S32 mv_size;
929
930 mv_size = vdpu382_get_colmv_size(width, height, ctu_size, colmv_byte, colmv_size, 1);
931 if (p_hal->cmv_bufs == NULL || p_hal->mv_size < mv_size) {
932 size_t size = mv_size;
933
934 if (p_hal->cmv_bufs) {
935 hal_bufs_deinit(p_hal->cmv_bufs);
936 p_hal->cmv_bufs = NULL;
937 }
938
939 hal_bufs_init(&p_hal->cmv_bufs);
940 if (p_hal->cmv_bufs == NULL) {
941 mpp_err_f("colmv bufs init fail");
942 return MPP_OK;
943 }
944 p_hal->mv_size = mv_size;
945 p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots);
946 hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size);
947 }
948
949 return MPP_OK;
950 }
951
vdpu382_h264d_gen_regs(void * hal,HalTaskInfo * task)952 MPP_RET vdpu382_h264d_gen_regs(void *hal, HalTaskInfo *task)
953 {
954 MPP_RET ret = MPP_ERR_UNKNOW;
955 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
956 Vdpu382H264dRegCtx *ctx = (Vdpu382H264dRegCtx *)p_hal->reg_ctx;
957 Vdpu382H264dRegSet *regs = ctx->regs;
958 INP_CHECK(ret, NULL == p_hal);
959
960 if (task->dec.flags.parse_err ||
961 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
962 goto __RETURN;
963 }
964
965 task->dec.reg_index = 0;
966 if (p_hal->fast_mode) {
967 RK_U32 i = 0;
968 for (i = 0; i < MPP_ARRAY_ELEMS(ctx->reg_buf); i++) {
969 if (!ctx->reg_buf[i].valid) {
970 task->dec.reg_index = i;
971 regs = ctx->reg_buf[i].regs;
972
973 ctx->spspps_offset = ctx->offset_spspps[i];
974 ctx->rps_offset = ctx->offset_rps[i];
975 ctx->sclst_offset = ctx->offset_sclst[i];
976 ctx->reg_buf[i].valid = 1;
977 break;
978 }
979 }
980 }
981 if (vdpu382_h264d_setup_colmv_buf(hal))
982 goto __RETURN;
983 prepare_spspps(p_hal, (RK_U64 *)&ctx->spspps, sizeof(ctx->spspps));
984 prepare_framerps(p_hal, (RK_U64 *)&ctx->rps, sizeof(ctx->rps));
985 prepare_scanlist(p_hal, ctx->sclst, sizeof(ctx->sclst));
986 set_registers(p_hal, regs, task);
987
988 //!< copy datas
989 RK_U32 i = 0;
990 if (!p_hal->fast_mode && !p_hal->pp->spspps_update) {
991 RK_U32 offset = 0;
992 RK_U32 len = VDPU382_SPS_PPS_LEN; //!< sps+pps data length
993 for (i = 0; i < 256; i++) {
994 offset = ctx->spspps_offset + (sizeof(ctx->spspps) * i) + len;
995 memcpy((char *)ctx->bufs_ptr + offset, (char *)ctx->spspps + len, sizeof(ctx->spspps) - len);
996 }
997 } else {
998 RK_U32 offset = 0;
999 for (i = 0; i < 256; i++) {
1000 offset = ctx->spspps_offset + (sizeof(ctx->spspps) * i);
1001 memcpy((char *)ctx->bufs_ptr + offset, (void *)ctx->spspps, sizeof(ctx->spspps));
1002 }
1003 }
1004
1005 regs->h264d_addr.pps_base = ctx->bufs_fd;
1006 mpp_dev_set_reg_offset(p_hal->dev, 161, ctx->spspps_offset);
1007
1008 memcpy((char *)ctx->bufs_ptr + ctx->rps_offset, (void *)ctx->rps, sizeof(ctx->rps));
1009 regs->h264d_addr.rps_base = ctx->bufs_fd;
1010 mpp_dev_set_reg_offset(p_hal->dev, 163, ctx->rps_offset);
1011
1012 regs->common.reg012.scanlist_addr_valid_en = 1;
1013 if (p_hal->pp->scaleing_list_enable_flag) {
1014 memcpy((char *)ctx->bufs_ptr + ctx->sclst_offset, (void *)ctx->sclst, sizeof(ctx->sclst));
1015 regs->h264d_addr.scanlist_addr = ctx->bufs_fd;
1016 mpp_dev_set_reg_offset(p_hal->dev, 180, ctx->sclst_offset);
1017 } else {
1018 regs->h264d_addr.scanlist_addr = 0;
1019 }
1020
1021 hal_h264d_rcb_info_update(p_hal, regs);
1022 vdpu382_setup_rcb(®s->common_addr, p_hal->dev, p_hal->fast_mode ?
1023 ctx->rcb_buf[task->dec.reg_index] : ctx->rcb_buf[0],
1024 ctx->rcb_info);
1025 {
1026 MppFrame mframe = NULL;
1027 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
1028 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe);
1029
1030 if (mpp_frame_get_thumbnail_en(mframe)) {
1031 regs->h264d_addr.reg198_scale_down_luma_base =
1032 regs->common_addr.reg130_decout_base;
1033 regs->h264d_addr.reg199_scale_down_chorme_base =
1034 regs->common_addr.reg130_decout_base;
1035 vdpu382_setup_down_scale(mframe, p_hal->dev, ®s->common);
1036 } else {
1037 regs->h264d_addr.reg198_scale_down_luma_base = 0;
1038 regs->h264d_addr.reg199_scale_down_chorme_base = 0;
1039 regs->common.reg012.scale_down_en = 0;
1040 }
1041 }
1042 /* back up ref infos */
1043 {
1044 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
1045 RK_S32 index = task->dec.reg_index;
1046
1047 memcpy(ctx->reg_buf[index].RefFrameList, pp->RefFrameList, sizeof(pp->RefFrameList));
1048 memcpy(ctx->reg_buf[index].RefPicList, p_hal->slice_long->RefPicList,
1049 sizeof(p_hal->slice_long->RefPicList));
1050 }
1051 vdpu382_setup_statistic(®s->common, ®s->statistic);
1052 mpp_buffer_sync_end(ctx->bufs);
1053
1054 __RETURN:
1055 return ret = MPP_OK;
1056 }
1057
vdpu382_h264d_start(void * hal,HalTaskInfo * task)1058 MPP_RET vdpu382_h264d_start(void *hal, HalTaskInfo *task)
1059 {
1060 MPP_RET ret = MPP_ERR_UNKNOW;
1061 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1062 INP_CHECK(ret, NULL == p_hal);
1063
1064 if (task->dec.flags.parse_err ||
1065 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
1066 goto __RETURN;
1067 }
1068
1069 Vdpu382H264dRegCtx *reg_ctx = (Vdpu382H264dRegCtx *)p_hal->reg_ctx;
1070 Vdpu382H264dRegSet *regs = p_hal->fast_mode ?
1071 reg_ctx->reg_buf[task->dec.reg_index].regs :
1072 reg_ctx->regs;
1073 MppDev dev = p_hal->dev;
1074
1075 do {
1076 MppDevRegWrCfg wr_cfg;
1077 MppDevRegRdCfg rd_cfg;
1078
1079 wr_cfg.reg = ®s->common;
1080 wr_cfg.size = sizeof(regs->common);
1081 wr_cfg.offset = OFFSET_COMMON_REGS;
1082
1083 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
1084 if (ret) {
1085 mpp_err_f("set register write failed %d\n", ret);
1086 break;
1087 }
1088
1089 wr_cfg.reg = ®s->h264d_param;
1090 wr_cfg.size = sizeof(regs->h264d_param);
1091 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS;
1092
1093 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
1094 if (ret) {
1095 mpp_err_f("set register write failed %d\n", ret);
1096 break;
1097 }
1098
1099 wr_cfg.reg = ®s->common_addr;
1100 wr_cfg.size = sizeof(regs->common_addr);
1101 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS;
1102
1103 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
1104 if (ret) {
1105 mpp_err_f("set register write failed %d\n", ret);
1106 break;
1107 }
1108
1109 wr_cfg.reg = ®s->h264d_addr;
1110 wr_cfg.size = sizeof(regs->h264d_addr);
1111 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS;
1112
1113 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
1114 if (ret) {
1115 mpp_err_f("set register write failed %d\n", ret);
1116 break;
1117 }
1118
1119 wr_cfg.reg = ®s->h264d_highpoc;
1120 wr_cfg.size = sizeof(regs->h264d_highpoc);
1121 wr_cfg.offset = OFFSET_POC_HIGHBIT_REGS;
1122 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
1123 if (ret) {
1124 mpp_err_f("set register write failed %d\n", ret);
1125 break;
1126 }
1127
1128 wr_cfg.reg = ®s->statistic;
1129 wr_cfg.size = sizeof(regs->statistic);
1130 wr_cfg.offset = OFFSET_STATISTIC_REGS;
1131
1132 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
1133 if (ret) {
1134 mpp_err_f("set register write failed %d\n", ret);
1135 break;
1136 }
1137
1138 rd_cfg.reg = ®s->irq_status;
1139 rd_cfg.size = sizeof(regs->irq_status);
1140 rd_cfg.offset = OFFSET_INTERRUPT_REGS;
1141
1142 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
1143 if (ret) {
1144 mpp_err_f("set register read failed %d\n", ret);
1145 break;
1146 }
1147
1148 rd_cfg.reg = ®s->statistic;
1149 rd_cfg.size = sizeof(regs->statistic);
1150 rd_cfg.offset = OFFSET_STATISTIC_REGS;
1151
1152 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
1153 if (ret) {
1154 mpp_err_f("set register read failed %d\n", ret);
1155 break;
1156 }
1157
1158 /* rcb info for sram */
1159 vdpu382_set_rcbinfo(dev, reg_ctx->rcb_info);
1160 /* send request to hardware */
1161 ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
1162 if (ret) {
1163 mpp_err_f("send cmd failed %d\n", ret);
1164 break;
1165 }
1166 } while (0);
1167
1168 __RETURN:
1169 return ret = MPP_OK;
1170 }
1171
vdpu382_h264_get_ref_used(void * hal,HalTaskInfo * task)1172 RK_U32 vdpu382_h264_get_ref_used(void *hal, HalTaskInfo *task)
1173 {
1174 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1175 Vdpu382H264dRegCtx *reg_ctx = (Vdpu382H264dRegCtx *)p_hal->reg_ctx;
1176 Vdpu382H264dRegSet *p_regs = p_hal->fast_mode ?
1177 reg_ctx->reg_buf[task->dec.reg_index].regs :
1178 reg_ctx->regs;
1179 RK_U32 hw_ref_used;
1180 RK_U32 ref_used = 0;;
1181
1182 memcpy(&hw_ref_used, &p_regs->statistic.reg265, sizeof(RK_U32));
1183
1184 {
1185 H264dRkvBuf_t *cur_buf = ®_ctx->reg_buf[task->dec.reg_index];
1186 RK_U32 i, j;
1187 MppFrame cur_frame = NULL;
1188 MppFrameStatus *status;
1189
1190 mpp_buf_slot_get_prop(p_hal->frame_slots, task->dec.output,
1191 SLOT_FRAME_PTR, &cur_frame);
1192 status = mpp_frame_get_status(cur_frame);
1193
1194 if (status->is_intra)
1195 return ref_used;
1196
1197 for (i = 0; i < 32; i++) {
1198 RK_U32 mask = 1 << i;
1199 RK_U32 dpb_idx;
1200
1201 if (!(hw_ref_used & mask))
1202 continue;
1203
1204 if (status->is_b_frame) {
1205 for (j = 1; j < 3; j++) {
1206 dpb_idx = cur_buf->RefPicList[j][i].Index7Bits;
1207 if (cur_buf->RefPicList[j][i].bPicEntry != 0xff && dpb_idx < 16)
1208 ref_used |= (1 << dpb_idx);
1209 }
1210 } else {
1211 j = 1;
1212 dpb_idx = cur_buf->RefPicList[j][i].Index7Bits;
1213 if (cur_buf->RefPicList[j][i].bPicEntry != 0xff && dpb_idx < 16)
1214 ref_used |= (1 << dpb_idx);
1215 }
1216 }
1217 }
1218 H264D_LOG("hw_ref_used 0x%08x ref_used %08x\n", hw_ref_used, ref_used);
1219
1220 return ref_used;
1221 }
1222
vdpu382_h264d_wait(void * hal,HalTaskInfo * task)1223 MPP_RET vdpu382_h264d_wait(void *hal, HalTaskInfo *task)
1224 {
1225 MPP_RET ret = MPP_ERR_UNKNOW;
1226 RK_S32 index = task->dec.reg_index;
1227 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1228 RK_U32 hw_err = 0;
1229 RK_U32 ref_used = 0;
1230
1231 INP_CHECK(ret, NULL == p_hal);
1232 Vdpu382H264dRegCtx *reg_ctx = (Vdpu382H264dRegCtx *)p_hal->reg_ctx;
1233 Vdpu382H264dRegSet *p_regs = p_hal->fast_mode ?
1234 reg_ctx->reg_buf[index].regs :
1235 reg_ctx->regs;
1236
1237 if (task->dec.flags.parse_err ||
1238 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
1239 goto __SKIP_HARD;
1240 }
1241
1242 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
1243 if (ret)
1244 mpp_err_f("poll cmd failed %d\n", ret);
1245
1246 hw_err = p_regs->irq_status.reg224.dec_error_sta ||
1247 (!p_regs->irq_status.reg224.dec_rdy_sta) ||
1248 p_regs->irq_status.reg224.buf_empty_sta ||
1249 p_regs->irq_status.reg226.strmd_error_status ||
1250 p_regs->irq_status.reg227.colmv_error_ref_picidx ||
1251 p_regs->irq_status.reg226.strmd_detect_error_flag;
1252
1253 /* the hw ref may not correct*/
1254 ref_used = reg_ctx->err_ref_hack ? 0 : vdpu382_h264_get_ref_used(hal, task);
1255 task->dec.flags.ref_info_valid = 1;
1256 task->dec.flags.ref_used = ref_used;
1257
1258 __SKIP_HARD:
1259 if (p_hal->dec_cb) {
1260 DecCbHalDone param;
1261
1262 param.task = (void *)&task->dec;
1263 param.regs = (RK_U32 *)p_regs;
1264 param.hard_err = hw_err;
1265
1266 mpp_callback(p_hal->dec_cb, ¶m);
1267 }
1268
1269 if (p_hal->fast_mode)
1270 reg_ctx->reg_buf[index].valid = 0;
1271
1272 (void)task;
1273 __RETURN:
1274 return ret = MPP_OK;
1275 }
1276
vdpu382_h264d_reset(void * hal)1277 MPP_RET vdpu382_h264d_reset(void *hal)
1278 {
1279 MPP_RET ret = MPP_ERR_UNKNOW;
1280 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1281
1282 INP_CHECK(ret, NULL == p_hal);
1283
1284 __RETURN:
1285 return ret = MPP_OK;
1286 }
1287
vdpu382_h264d_flush(void * hal)1288 MPP_RET vdpu382_h264d_flush(void *hal)
1289 {
1290 MPP_RET ret = MPP_ERR_UNKNOW;
1291 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1292
1293 INP_CHECK(ret, NULL == p_hal);
1294
1295 __RETURN:
1296 return ret = MPP_OK;
1297 }
1298
vdpu382_h264d_control(void * hal,MpiCmd cmd_type,void * param)1299 MPP_RET vdpu382_h264d_control(void *hal, MpiCmd cmd_type, void *param)
1300 {
1301 MPP_RET ret = MPP_ERR_UNKNOW;
1302 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1303
1304 INP_CHECK(ret, NULL == p_hal);
1305
1306 switch ((MpiCmd)cmd_type) {
1307 case MPP_DEC_SET_FRAME_INFO: {
1308 MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param);
1309 RK_U32 imgwidth = mpp_frame_get_width((MppFrame)param);
1310 RK_U32 imgheight = mpp_frame_get_height((MppFrame)param);
1311
1312 mpp_log("control info: fmt %d, w %d, h %d\n", fmt, imgwidth, imgheight);
1313 if (fmt == MPP_FMT_YUV422SP) {
1314 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
1315 }
1316 if (MPP_FRAME_FMT_IS_FBC(fmt)) {
1317 vdpu382_afbc_align_calc(p_hal->frame_slots, (MppFrame)param, 16);
1318 } else if (imgwidth > 1920 || imgheight > 1088) {
1319 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, rkv_hor_align_256_odds);
1320 }
1321 break;
1322 }
1323 case MPP_DEC_SET_OUTPUT_FORMAT: {
1324
1325 } break;
1326 default:
1327 break;
1328 }
1329
1330 __RETURN:
1331 return ret = MPP_OK;
1332 }
1333
1334 const MppHalApi hal_h264d_vdpu382 = {
1335 .name = "h264d_vdpu382",
1336 .type = MPP_CTX_DEC,
1337 .coding = MPP_VIDEO_CodingAVC,
1338 .ctx_size = sizeof(Vdpu382H264dRegCtx),
1339 .flag = 0,
1340 .init = vdpu382_h264d_init,
1341 .deinit = vdpu382_h264d_deinit,
1342 .reg_gen = vdpu382_h264d_gen_regs,
1343 .start = vdpu382_h264d_start,
1344 .wait = vdpu382_h264d_wait,
1345 .reset = vdpu382_h264d_reset,
1346 .flush = vdpu382_h264d_flush,
1347 .control = vdpu382_h264d_control,
1348 };
1349