Lines Matching refs:regs
53 if (NULL == ctx->regs) { in hal_vp8d_vdpu1_init()
54 ctx->regs = mpp_calloc_size(void, sizeof(VP8DRegSet_t)); in hal_vp8d_vdpu1_init()
55 if (NULL == ctx->regs) { in hal_vp8d_vdpu1_init()
94 if (ctx->regs) { in hal_vp8d_vdpu1_init()
95 mpp_free(ctx->regs); in hal_vp8d_vdpu1_init()
96 ctx->regs = NULL; in hal_vp8d_vdpu1_init()
150 if (ctx->regs) { in hal_vp8d_vdpu1_deinit()
151 mpp_free(ctx->regs); in hal_vp8d_vdpu1_deinit()
152 ctx->regs = NULL; in hal_vp8d_vdpu1_deinit()
162 VP8DRegSet_t *reg = (VP8DRegSet_t *)ctx->regs; in hal_vp8_init_hwcfg()
202 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs; in hal_vp8d_pre_filter_tap_set() local
205 regs->reg49.sw_pred_bc_tap_0_0 = mcFilter[0][1]; in hal_vp8d_pre_filter_tap_set()
206 regs->reg49.sw_pred_bc_tap_0_1 = mcFilter[0][2]; in hal_vp8d_pre_filter_tap_set()
207 regs->reg49.sw_pred_bc_tap_0_2 = mcFilter[0][3]; in hal_vp8d_pre_filter_tap_set()
208 regs->reg34.sw_pred_bc_tap_0_3 = mcFilter[0][4]; in hal_vp8d_pre_filter_tap_set()
209 regs->reg34.sw_pred_bc_tap_1_0 = mcFilter[1][1]; in hal_vp8d_pre_filter_tap_set()
210 regs->reg34.sw_pred_bc_tap_1_1 = mcFilter[1][2]; in hal_vp8d_pre_filter_tap_set()
211 regs->reg35.sw_pred_bc_tap_1_2 = mcFilter[1][3]; in hal_vp8d_pre_filter_tap_set()
212 regs->reg35.sw_pred_bc_tap_1_3 = mcFilter[1][4]; in hal_vp8d_pre_filter_tap_set()
213 regs->reg35.sw_pred_bc_tap_2_0 = mcFilter[2][1]; in hal_vp8d_pre_filter_tap_set()
214 regs->reg36.sw_pred_bc_tap_2_1 = mcFilter[2][2]; in hal_vp8d_pre_filter_tap_set()
215 regs->reg36.sw_pred_bc_tap_2_2 = mcFilter[2][3]; in hal_vp8d_pre_filter_tap_set()
216 regs->reg36.sw_pred_bc_tap_2_3 = mcFilter[2][4]; in hal_vp8d_pre_filter_tap_set()
218 regs->reg37.sw_pred_bc_tap_3_0 = mcFilter[3][1]; in hal_vp8d_pre_filter_tap_set()
219 regs->reg37.sw_pred_bc_tap_3_1 = mcFilter[3][2]; in hal_vp8d_pre_filter_tap_set()
220 regs->reg37.sw_pred_bc_tap_3_2 = mcFilter[3][3]; in hal_vp8d_pre_filter_tap_set()
221 regs->reg38.sw_pred_bc_tap_3_3 = mcFilter[3][4]; in hal_vp8d_pre_filter_tap_set()
222 regs->reg38.sw_pred_bc_tap_4_0 = mcFilter[4][1]; in hal_vp8d_pre_filter_tap_set()
223 regs->reg38.sw_pred_bc_tap_4_1 = mcFilter[4][2]; in hal_vp8d_pre_filter_tap_set()
224 regs->reg39.sw_pred_bc_tap_4_2 = mcFilter[4][3]; in hal_vp8d_pre_filter_tap_set()
225 regs->reg39.sw_pred_bc_tap_4_3 = mcFilter[4][4]; in hal_vp8d_pre_filter_tap_set()
226 regs->reg39.sw_pred_bc_tap_5_0 = mcFilter[5][1]; in hal_vp8d_pre_filter_tap_set()
228 regs->reg42.sw_pred_bc_tap_5_1 = mcFilter[5][2]; in hal_vp8d_pre_filter_tap_set()
229 regs->reg42.sw_pred_bc_tap_5_2 = mcFilter[5][3]; in hal_vp8d_pre_filter_tap_set()
230 regs->reg42.sw_pred_bc_tap_5_3 = mcFilter[5][4]; in hal_vp8d_pre_filter_tap_set()
232 regs->reg43.sw_pred_bc_tap_6_0 = mcFilter[6][1]; in hal_vp8d_pre_filter_tap_set()
233 regs->reg43.sw_pred_bc_tap_6_1 = mcFilter[6][2]; in hal_vp8d_pre_filter_tap_set()
234 regs->reg43.sw_pred_bc_tap_6_2 = mcFilter[6][3]; in hal_vp8d_pre_filter_tap_set()
236 regs->reg44.sw_pred_bc_tap_6_3 = mcFilter[6][4]; in hal_vp8d_pre_filter_tap_set()
237 regs->reg44.sw_pred_bc_tap_7_0 = mcFilter[7][1]; in hal_vp8d_pre_filter_tap_set()
238 regs->reg44.sw_pred_bc_tap_7_1 = mcFilter[7][2]; in hal_vp8d_pre_filter_tap_set()
240 regs->reg45.sw_pred_bc_tap_7_2 = mcFilter[7][3]; in hal_vp8d_pre_filter_tap_set()
241 regs->reg45.sw_pred_bc_tap_7_3 = mcFilter[7][4]; in hal_vp8d_pre_filter_tap_set()
243 regs->reg45.sw_pred_tap_2_M1 = mcFilter[2][0]; in hal_vp8d_pre_filter_tap_set()
244 regs->reg45.sw_pred_tap_2_4 = mcFilter[2][5]; in hal_vp8d_pre_filter_tap_set()
245 regs->reg45.sw_pred_tap_4_M1 = mcFilter[4][0]; in hal_vp8d_pre_filter_tap_set()
246 regs->reg45.sw_pred_tap_4_4 = mcFilter[4][5]; in hal_vp8d_pre_filter_tap_set()
247 regs->reg45.sw_pred_tap_6_M1 = mcFilter[6][0]; in hal_vp8d_pre_filter_tap_set()
248 regs->reg45.sw_pred_tap_6_4 = mcFilter[6][5]; in hal_vp8d_pre_filter_tap_set()
262 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs; in hal_vp8d_dct_partition_cfg() local
271 regs->reg27_bitpl_ctrl_base = fd; in hal_vp8d_dct_partition_cfg()
274 regs->reg5.sw_strm1_start_bit = pic_param->stream_start_bit; in hal_vp8d_dct_partition_cfg()
285 regs->reg6.sw_stream_len = len; in hal_vp8d_dct_partition_cfg()
291 regs->reg9.sw_stream1_len = len; in hal_vp8d_dct_partition_cfg()
292 regs->reg9.sw_coeffs_part_am = (1 << pic_param->log2_nbr_of_dct_partitions); in hal_vp8d_dct_partition_cfg()
293 regs->reg9.sw_coeffs_part_am--; in hal_vp8d_dct_partition_cfg()
300 regs->reg12_input_stream_base = fd; in hal_vp8d_dct_partition_cfg()
305 regs->reg_dct_strm0_base[i - 1] = fd; in hal_vp8d_dct_partition_cfg()
310 regs->reg_dct_strm1_base[i - 6] = fd; in hal_vp8d_dct_partition_cfg()
318 regs->reg5.sw_strm0_start_bit = byte_offset * 8; in hal_vp8d_dct_partition_cfg()
321 regs->reg7.sw_dct1_start_bit = byte_offset * 8; in hal_vp8d_dct_partition_cfg()
324 regs->reg7.sw_dct2_start_bit = byte_offset * 8; in hal_vp8d_dct_partition_cfg()
327 regs->reg11.sw_dct_start_bit_3 = byte_offset * 8; in hal_vp8d_dct_partition_cfg()
330 regs->reg11.sw_dct_start_bit_4 = byte_offset * 8; in hal_vp8d_dct_partition_cfg()
333 regs->reg11.sw_dct_start_bit_5 = byte_offset * 8; in hal_vp8d_dct_partition_cfg()
336 regs->reg11.sw_dct_start_bit_6 = byte_offset * 8; in hal_vp8d_dct_partition_cfg()
339 regs->reg11.sw_dct_start_bit_7 = byte_offset * 8; in hal_vp8d_dct_partition_cfg()
455 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs; in hal_vp8d_vdpu1_gen_regs() local
464 regs->reg4.sw_pic_mb_width = mb_width & 0x1FF; in hal_vp8d_vdpu1_gen_regs()
465 regs->reg4.sw_pic_mb_hight_p = mb_height & 0xFF; in hal_vp8d_vdpu1_gen_regs()
466 regs->reg4.sw_pic_mb_w_ext = mb_width >> 9; in hal_vp8d_vdpu1_gen_regs()
467 regs->reg4.sw_pic_mb_h_ext = mb_height >> 8; in hal_vp8d_vdpu1_gen_regs()
481 regs->reg13_cur_pic_base = mpp_buffer_get_fd(framebuf); in hal_vp8d_vdpu1_gen_regs()
486 regs->reg14_ref0_base = regs->reg13_cur_pic_base; in hal_vp8d_vdpu1_gen_regs()
490 regs->reg14_ref0_base = mpp_buffer_get_fd(framebuf); in hal_vp8d_vdpu1_gen_regs()
492 regs->reg14_ref0_base = regs->reg13_cur_pic_base; in hal_vp8d_vdpu1_gen_regs()
498 regs->reg18_golden_ref_base = mpp_buffer_get_fd(framebuf); in hal_vp8d_vdpu1_gen_regs()
500 regs->reg18_golden_ref_base = regs->reg13_cur_pic_base; in hal_vp8d_vdpu1_gen_regs()
510 regs->reg19.alternate_ref_base = mpp_buffer_get_fd(framebuf); in hal_vp8d_vdpu1_gen_regs()
512 regs->reg19.alternate_ref_base = regs->reg13_cur_pic_base; in hal_vp8d_vdpu1_gen_regs()
524 regs->reg3.sw_pic_inter_e = pic_param->frame_type; in hal_vp8d_vdpu1_gen_regs()
525 regs->reg3.sw_skip_mode = !pic_param->mb_no_coeff_skip; in hal_vp8d_vdpu1_gen_regs()
528 regs->reg32.sw_filt_level_0 = pic_param->filter_level; in hal_vp8d_vdpu1_gen_regs()
530 regs->reg32.sw_filt_level_0 = in hal_vp8d_vdpu1_gen_regs()
532 regs->reg32.sw_filt_level_1 = in hal_vp8d_vdpu1_gen_regs()
534 regs->reg32.sw_filt_level_2 = in hal_vp8d_vdpu1_gen_regs()
536 regs->reg32.sw_filt_level_3 = in hal_vp8d_vdpu1_gen_regs()
539 regs->reg32.sw_filt_level_0 = CLIP3(0, 63, in hal_vp8d_vdpu1_gen_regs()
542 regs->reg32.sw_filt_level_1 = CLIP3(0, 63, in hal_vp8d_vdpu1_gen_regs()
545 regs->reg32.sw_filt_level_2 = CLIP3(0, 63, in hal_vp8d_vdpu1_gen_regs()
548 regs->reg32.sw_filt_level_3 = CLIP3(0, 63, in hal_vp8d_vdpu1_gen_regs()
553 regs->reg30.sw_filt_type = pic_param->filter_type; in hal_vp8d_vdpu1_gen_regs()
554 regs->reg30.sw_filt_sharpness = pic_param->sharpness; in hal_vp8d_vdpu1_gen_regs()
557 regs->reg3.sw_filtering_dis = 1; in hal_vp8d_vdpu1_gen_regs()
560 regs->reg7.sw_ch_mv_res = 1; in hal_vp8d_vdpu1_gen_regs()
563 regs->reg7.sw_bilin_mc_e = 1; in hal_vp8d_vdpu1_gen_regs()
565 regs->reg5.sw_boolean_value = pic_param->bool_value; in hal_vp8d_vdpu1_gen_regs()
566 regs->reg5.sw_boolean_range = pic_param->bool_range; in hal_vp8d_vdpu1_gen_regs()
570 regs->reg33.sw_quant_0 = pic_param->y1ac_delta_q; in hal_vp8d_vdpu1_gen_regs()
572 regs->reg33.sw_quant_0 = in hal_vp8d_vdpu1_gen_regs()
574 regs->reg33.sw_quant_1 = in hal_vp8d_vdpu1_gen_regs()
576 regs->reg46.sw_quant_2 = pic_param->stVP8Segments.segment_feature_data[0][2]; in hal_vp8d_vdpu1_gen_regs()
577 regs->reg46.sw_quant_3 = pic_param->stVP8Segments.segment_feature_data[0][3]; in hal_vp8d_vdpu1_gen_regs()
579 regs->reg33.sw_quant_0 = CLIP3(0, 127, in hal_vp8d_vdpu1_gen_regs()
582 regs->reg33.sw_quant_1 = CLIP3(0, 127, in hal_vp8d_vdpu1_gen_regs()
585 regs->reg46.sw_quant_2 = CLIP3(0, 127, in hal_vp8d_vdpu1_gen_regs()
588 regs->reg46.sw_quant_3 = CLIP3(0, 127, in hal_vp8d_vdpu1_gen_regs()
593 regs->reg33.sw_quant_delta_0 = pic_param->y1dc_delta_q; in hal_vp8d_vdpu1_gen_regs()
594 regs->reg33.sw_quant_delta_1 = pic_param->y2dc_delta_q; in hal_vp8d_vdpu1_gen_regs()
595 regs->reg46.sw_quant_delta_2 = pic_param->y2ac_delta_q; in hal_vp8d_vdpu1_gen_regs()
596 regs->reg46.sw_quant_delta_3 = pic_param->uvdc_delta_q; in hal_vp8d_vdpu1_gen_regs()
597 regs->reg47.sw_quant_delta_4 = pic_param->uvac_delta_q; in hal_vp8d_vdpu1_gen_regs()
600 regs->reg31.sw_filt_ref_adj_0 = pic_param->ref_lf_deltas[0]; in hal_vp8d_vdpu1_gen_regs()
601 regs->reg31.sw_filt_ref_adj_1 = pic_param->ref_lf_deltas[1]; in hal_vp8d_vdpu1_gen_regs()
602 regs->reg31.sw_filt_ref_adj_2 = pic_param->ref_lf_deltas[2]; in hal_vp8d_vdpu1_gen_regs()
603 regs->reg31.sw_filt_ref_adj_3 = pic_param->ref_lf_deltas[3]; in hal_vp8d_vdpu1_gen_regs()
604 regs->reg30.sw_filt_mb_adj_0 = pic_param->mode_lf_deltas[0]; in hal_vp8d_vdpu1_gen_regs()
605 regs->reg30.sw_filt_mb_adj_1 = pic_param->mode_lf_deltas[1]; in hal_vp8d_vdpu1_gen_regs()
606 regs->reg30.sw_filt_mb_adj_2 = pic_param->mode_lf_deltas[2]; in hal_vp8d_vdpu1_gen_regs()
607 regs->reg30.sw_filt_mb_adj_3 = pic_param->mode_lf_deltas[3]; in hal_vp8d_vdpu1_gen_regs()
627 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs; in hal_vp8d_vdpu1_start() local
632 RK_U32 *p = ctx->regs; in hal_vp8d_vdpu1_start()
644 wr_cfg.reg = regs; in hal_vp8d_vdpu1_start()
654 rd_cfg.reg = regs; in hal_vp8d_vdpu1_start()