1 /*
2 * Copyright 2022 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_h265e_v540c"
18
19 #include <linux/string.h>
20
21 #include <string.h>
22 #include <math.h>
23 #include <limits.h>
24
25 #include "mpp_env.h"
26 #include "mpp_mem.h"
27 #include "mpp_soc.h"
28 #include "mpp_common.h"
29 #include "mpp_frame_impl.h"
30
31 #include "hal_h265e_debug.h"
32 #include "h265e_syntax_new.h"
33 #include "hal_h265e_stream_amend.h"
34 #include "hal_bufs.h"
35 #include "rkv_enc_def.h"
36 #include "vepu5xx_common.h"
37 #include "vepu540c_common.h"
38 #include "hal_h265e_vepu540c.h"
39 #include "hal_h265e_vepu540c_reg.h"
40
41 #define MAX_TITLE_NUM 2
42
43 #define hal_h265e_err(fmt, ...) \
44 do {\
45 mpp_err_f(fmt, ## __VA_ARGS__);\
46 } while (0)
47
48 typedef struct vepu540c_h265_fbk_t {
49 vepu540c_hw_status hw_status;
50 RK_U32 qp_sum;
51 RK_U32 out_strm_size;
52 RK_U32 out_hw_strm_size;
53 RK_S64 sse_sum;
54 RK_U32 st_lvl64_inter_num;
55 RK_U32 st_lvl32_inter_num;
56 RK_U32 st_lvl16_inter_num;
57 RK_U32 st_lvl8_inter_num;
58 RK_U32 st_lvl32_intra_num;
59 RK_U32 st_lvl16_intra_num;
60 RK_U32 st_lvl8_intra_num;
61 RK_U32 st_lvl4_intra_num;
62 RK_U32 st_cu_num_qp[52];
63 RK_U32 st_madp;
64 RK_U32 st_madi;
65 RK_U32 st_mb_num;
66 RK_U32 st_ctu_num;
67 } vepu540c_h265_fbk;
68
69 typedef struct H265eV540cHalContext_t {
70 MppEncHalApi api;
71 MppDev dev;
72 void *regs;
73 void *reg_out[MAX_TITLE_NUM];
74
75 vepu540c_h265_fbk feedback;
76 void *dump_files;
77 RK_U32 frame_cnt_gen_ready;
78
79 RK_S32 frame_type;
80 RK_S32 last_frame_type;
81
82 /* @frame_cnt starts from ZERO */
83 RK_U32 frame_cnt;
84 void *roi_data;
85 MppEncCfgSet *cfg;
86
87 RK_U32 enc_mode;
88 RK_U32 frame_size;
89 RK_S32 max_buf_cnt;
90 RK_S32 hdr_status;
91 void *input_fmt;
92 RK_U8 *src_buf;
93 RK_U8 *dst_buf;
94 RK_S32 buf_size;
95 RK_U32 frame_num;
96 HalBufs dpb_bufs;
97 RK_S32 fbc_header_len;
98 RK_U32 title_num;
99
100 /* external line buffer over 3K */
101 MppBufferGroup ext_line_buf_grp;
102 RK_S32 ext_line_buf_size;
103 MppBuffer ext_line_buf;
104 } H265eV540cHalContext;
105
106 #define TILE_BUF_SIZE MPP_ALIGN(128 * 1024, 256)
107
108 static RK_U32 aq_thd_default[16] = {
109 0, 0, 0, 0,
110 3, 3, 5, 5,
111 8, 8, 8, 15,
112 15, 20, 25, 25
113 };
114
115 static RK_S32 aq_qp_dealt_default[16] = {
116 -8, -7, -6, -5,
117 -4, -3, -2, -1,
118 0, 1, 2, 3,
119 4, 5, 6, 8,
120 };
121
vepu540c_h265_setup_hal_bufs(H265eV540cHalContext * ctx)122 static MPP_RET vepu540c_h265_setup_hal_bufs(H265eV540cHalContext *ctx)
123 {
124 MPP_RET ret = MPP_OK;
125 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
126 RK_U32 frame_size;
127 VepuFmt input_fmt = VEPU5xx_FMT_YUV420P;
128 RK_S32 mb_wd64, mb_h64;
129 MppEncRefCfg ref_cfg = ctx->cfg->ref_cfg;
130 MppEncPrepCfg *prep = &ctx->cfg->prep;
131 RK_S32 old_max_cnt = ctx->max_buf_cnt;
132 RK_S32 new_max_cnt = 2;
133 RK_S32 alignment = 32;
134 RK_S32 aligned_w = MPP_ALIGN(prep->width, alignment);
135
136 hal_h265e_enter();
137
138 mb_wd64 = (prep->width + 63) / 64;
139 mb_h64 = (prep->height + 63) / 64;
140
141 frame_size = MPP_ALIGN(prep->width, 16) * MPP_ALIGN(prep->height, 16);
142 vepu5xx_set_fmt(fmt, ctx->cfg->prep.format);
143 input_fmt = (VepuFmt)fmt->format;
144 switch (input_fmt) {
145 case VEPU5xx_FMT_YUV400:
146 break;
147 case VEPU5xx_FMT_YUV420P:
148 case VEPU5xx_FMT_YUV420SP: {
149 frame_size = frame_size * 3 / 2;
150 } break;
151 case VEPU5xx_FMT_YUV422P:
152 case VEPU5xx_FMT_YUV422SP:
153 case VEPU5xx_FMT_YUYV422:
154 case VEPU5xx_FMT_UYVY422:
155 case VEPU5xx_FMT_BGR565: {
156 frame_size *= 2;
157 } break;
158 case VEPU5xx_FMT_BGR888: {
159 frame_size *= 3;
160 } break;
161 case VEPU5xx_FMT_BGRA8888: {
162 frame_size *= 4;
163 } break;
164 default: {
165 hal_h265e_err("invalid src color space: %d\n", input_fmt);
166 return MPP_NOK;
167 }
168 }
169
170 if (ref_cfg) {
171 MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
172 new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1);
173 }
174
175 if (aligned_w > (3 * SZ_1K)) {
176 RK_S32 ext_line_buf_size = (aligned_w / 32 - 91) * 26 * 16;
177
178 if (NULL == ctx->ext_line_buf_grp)
179 mpp_buffer_group_get_internal(&ctx->ext_line_buf_grp, MPP_BUFFER_TYPE_ION);
180 else if (ext_line_buf_size != ctx->ext_line_buf_size) {
181 mpp_buffer_put(ctx->ext_line_buf);
182 ctx->ext_line_buf = NULL;
183 mpp_buffer_group_clear(ctx->ext_line_buf_grp);
184 }
185
186 mpp_assert(ctx->ext_line_buf_grp);
187
188 if (NULL == ctx->ext_line_buf)
189 mpp_buffer_get(ctx->ext_line_buf_grp, &ctx->ext_line_buf, ext_line_buf_size);
190
191 ctx->ext_line_buf_size = ext_line_buf_size;
192 } else {
193 if (ctx->ext_line_buf) {
194 mpp_buffer_put(ctx->ext_line_buf);
195 ctx->ext_line_buf = NULL;
196 }
197
198 if (ctx->ext_line_buf_grp) {
199 mpp_buffer_group_clear(ctx->ext_line_buf_grp);
200 mpp_buffer_group_put(ctx->ext_line_buf_grp);
201 ctx->ext_line_buf_grp = NULL;
202 }
203 ctx->ext_line_buf_size = 0;
204 }
205
206 if (frame_size > ctx->frame_size || new_max_cnt > old_max_cnt) {
207 size_t size[3] = {0};
208
209 hal_bufs_deinit(ctx->dpb_bufs);
210 hal_bufs_init(&ctx->dpb_bufs);
211
212 ctx->fbc_header_len = MPP_ALIGN(((mb_wd64 * mb_h64) << 6), SZ_8K);
213 size[0] = ctx->fbc_header_len + ((mb_wd64 * mb_h64) << 12) * 3 / 2; //fbc_h + fbc_b
214 size[1] = (mb_wd64 * mb_h64 << 8);
215 size[2] = MPP_ALIGN(mb_wd64 * mb_h64 * 16 * 4, 256) * 16;
216 new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
217
218 hal_h265e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
219 ctx->frame_size, frame_size, old_max_cnt, new_max_cnt);
220
221 hal_bufs_setup(ctx->dpb_bufs, new_max_cnt, 3, size);
222
223 ctx->frame_size = frame_size;
224 ctx->max_buf_cnt = new_max_cnt;
225 }
226 hal_h265e_leave();
227 return ret;
228 }
229
vepu540c_h265_rdo_cfg(vepu540c_rdo_cfg * reg)230 static void vepu540c_h265_rdo_cfg (vepu540c_rdo_cfg *reg)
231 {
232 rdo_skip_par *p_rdo_skip = NULL;
233 rdo_noskip_par *p_rdo_noskip = NULL;
234 pre_cst_par *p_pre_cst = NULL;
235
236 reg->rdo_segment_cfg.rdo_segment_multi = 28;
237 reg->rdo_segment_cfg.rdo_segment_en = 1;
238 reg->rdo_smear_cfg_comb.rdo_smear_en = 0;
239 reg->rdo_smear_cfg_comb.rdo_smear_lvl16_multi = 9;
240 reg->rdo_segment_cfg.rdo_smear_lvl8_multi = 8;
241 reg->rdo_segment_cfg.rdo_smear_lvl4_multi = 8;
242 reg->rdo_smear_cfg_comb.rdo_smear_dlt_qp = 0 ;
243 reg->rdo_smear_cfg_comb.rdo_smear_order_state = 0;
244 reg->rdo_smear_cfg_comb.stated_mode = 0;
245 reg->rdo_smear_cfg_comb.online_en = 0;
246 reg->rdo_smear_cfg_comb.smear_stride = 0;
247 reg->rdo_smear_madp_thd0_comb.rdo_smear_madp_cur_thd0 = 0 ;
248 reg->rdo_smear_madp_thd0_comb.rdo_smear_madp_cur_thd1 = 24;
249 reg->rdo_smear_madp_thd1_comb.rdo_smear_madp_cur_thd2 = 48;
250 reg->rdo_smear_madp_thd1_comb.rdo_smear_madp_cur_thd3 = 64;
251 reg->rdo_smear_madp_thd2_comb.rdo_smear_madp_around_thd0 = 16;
252 reg->rdo_smear_madp_thd2_comb.rdo_smear_madp_around_thd1 = 32;
253 reg->rdo_smear_madp_thd3_comb.rdo_smear_madp_around_thd2 = 48;
254 reg->rdo_smear_madp_thd3_comb.rdo_smear_madp_around_thd3 = 96;
255 reg->rdo_smear_madp_thd4_comb.rdo_smear_madp_around_thd4 = 48;
256 reg->rdo_smear_madp_thd4_comb.rdo_smear_madp_around_thd5 = 24;
257 reg->rdo_smear_madp_thd5_comb.rdo_smear_madp_ref_thd0 = 96;
258 reg->rdo_smear_madp_thd5_comb.rdo_smear_madp_ref_thd1 = 48;
259 reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd0 = 1 ;
260 reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd1 = 3;
261 reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd2 = 1 ;
262 reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd3 = 3;
263 reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd0 = 1 ;
264 reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd1 = 4 ;
265 reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd2 = 1 ;
266 reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd3 = 4 ;
267 reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd4 = 0;
268 reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd5 = 3;
269 reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd6 = 0;
270 reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd7 = 3;
271 reg->rdo_smear_cnt_thd3_comb.rdo_smear_cnt_ref_thd0 = 1;
272 reg->rdo_smear_cnt_thd3_comb.rdo_smear_cnt_ref_thd1 = 3;
273 reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_small_cur_th0 = 6;
274 reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_big_cur_th0 = 9;
275 reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_small_cur_th1 = 6;
276 reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_big_cur_th1 = 9;
277 reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_small_around_th0 = 6;
278 reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_big_around_th0 = 11;
279 reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_small_around_th1 = 6;
280 reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_big_around_th1 = 8;
281 reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_small_around_th2 = 9;
282 reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_big_around_th2 = 20;
283 reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_small_around_th3 = 6;
284 reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_big_around_th3 = 20;
285 reg->rdo_smear_resi_thd3_comb.rdo_smear_resi_small_ref_th0 = 7;
286 reg->rdo_smear_resi_thd3_comb.rdo_smear_resi_big_ref_th0 = 16;
287 reg->rdo_smear_st_thd0_comb.rdo_smear_resi_th0 = 9;
288 reg->rdo_smear_st_thd0_comb.rdo_smear_resi_th1 = 6;
289 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th0 = 1;
290 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th1 = 5;
291 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th2 = 1;
292 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th3 = 3;
293 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th4 = 1;
294 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th5 = 2;
295
296 p_rdo_skip = ®->rdo_b32_skip;
297 p_rdo_skip->atf_thd0.madp_thd0 = 5 ;
298 p_rdo_skip->atf_thd0.madp_thd1 = 10 ;
299 p_rdo_skip->atf_thd1.madp_thd2 = 15 ;
300 p_rdo_skip->atf_thd1.madp_thd3 = 72;
301 p_rdo_skip->atf_wgt0.wgt0 = 20;
302 p_rdo_skip->atf_wgt0.wgt1 = 16;
303 p_rdo_skip->atf_wgt0.wgt2 = 16;
304 p_rdo_skip->atf_wgt0.wgt3 = 16;
305 p_rdo_skip->atf_wgt1.wgt4 = 16;
306
307 p_rdo_noskip = ®->rdo_b32_inter;
308 p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
309 p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
310 p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
311 p_rdo_noskip->atf_wgt.wgt0 = 16;
312 p_rdo_noskip->atf_wgt.wgt1 = 16;
313 p_rdo_noskip->atf_wgt.wgt2 = 16;
314 p_rdo_noskip->atf_wgt.wgt3 = 16;
315
316 p_rdo_noskip = ®->rdo_b32_intra;
317 p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
318 p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
319 p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
320 p_rdo_noskip->atf_wgt.wgt0 = 27;
321 p_rdo_noskip->atf_wgt.wgt1 = 25;
322 p_rdo_noskip->atf_wgt.wgt2 = 20;
323 p_rdo_noskip->atf_wgt.wgt3 = 19;
324
325 p_rdo_skip = ®->rdo_b16_skip;
326 p_rdo_skip->atf_thd0.madp_thd0 = 1;
327 p_rdo_skip->atf_thd0.madp_thd1 = 10 ;
328 p_rdo_skip->atf_thd1.madp_thd2 = 15 ;
329 p_rdo_skip->atf_thd1.madp_thd3 = 25 ;
330 p_rdo_skip->atf_wgt0.wgt0 = 20 ;
331 p_rdo_skip->atf_wgt0.wgt1 = 16;
332 p_rdo_skip->atf_wgt0.wgt2 = 16;
333 p_rdo_skip->atf_wgt0.wgt3 = 16;
334 p_rdo_skip->atf_wgt1.wgt4 = 16;
335
336 p_rdo_noskip = ®->rdo_b16_inter;
337 p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
338 p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
339 p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
340 p_rdo_noskip->atf_wgt.wgt0 = 16;
341 p_rdo_noskip->atf_wgt.wgt1 = 16;
342 p_rdo_noskip->atf_wgt.wgt2 = 16;
343 p_rdo_noskip->atf_wgt.wgt3 = 16;
344
345 p_rdo_noskip = ®->rdo_b16_intra;
346 p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
347 p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
348 p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
349 p_rdo_noskip->atf_wgt.wgt0 = 27;
350 p_rdo_noskip->atf_wgt.wgt1 = 25;
351 p_rdo_noskip->atf_wgt.wgt2 = 20;
352 p_rdo_noskip->atf_wgt.wgt3 = 16;
353
354 reg->rdo_b32_intra_atf_cnt_thd.thd0 = 1;
355 reg->rdo_b32_intra_atf_cnt_thd.thd1 = 4;
356 reg->rdo_b32_intra_atf_cnt_thd.thd2 = 1;
357 reg->rdo_b32_intra_atf_cnt_thd.thd3 = 4;
358
359 reg->rdo_b16_intra_atf_cnt_thd_comb.thd0 = 1;
360 reg->rdo_b16_intra_atf_cnt_thd_comb.thd1 = 4;
361 reg->rdo_b16_intra_atf_cnt_thd_comb.thd2 = 1;
362 reg->rdo_b16_intra_atf_cnt_thd_comb.thd3 = 4;
363 reg->rdo_atf_resi_thd_comb.big_th0 = 16;
364 reg->rdo_atf_resi_thd_comb.big_th1 = 16;
365 reg->rdo_atf_resi_thd_comb.small_th0 = 8;
366 reg->rdo_atf_resi_thd_comb.small_th1 = 8;
367
368 p_pre_cst = ®->preintra32_cst;
369 p_pre_cst->cst_madi_thd0.madi_thd0 = 5;
370 p_pre_cst->cst_madi_thd0.madi_thd1 = 3;
371 p_pre_cst->cst_madi_thd0.madi_thd2 = 3;
372 p_pre_cst->cst_madi_thd0.madi_thd3 = 6;
373 p_pre_cst->cst_madi_thd1.madi_thd4 = 7;
374 p_pre_cst->cst_madi_thd1.madi_thd5 = 10;
375 p_pre_cst->cst_wgt0.wgt0 = 20;
376 p_pre_cst->cst_wgt0.wgt1 = 18;
377 p_pre_cst->cst_wgt0.wgt2 = 19;
378 p_pre_cst->cst_wgt0.wgt3 = 18;
379 p_pre_cst->cst_wgt1.wgt4 = 6;
380 p_pre_cst->cst_wgt1.wgt5 = 9;
381 p_pre_cst->cst_wgt1.wgt6 = 14;
382 p_pre_cst->cst_wgt1.wgt7 = 18;
383 p_pre_cst->cst_wgt2.wgt8 = 17;
384 p_pre_cst->cst_wgt2.wgt9 = 17;
385 p_pre_cst->cst_wgt2.mode_th = 5;
386
387 p_pre_cst = ®->preintra16_cst;
388 p_pre_cst->cst_madi_thd0.madi_thd0 = 5;
389 p_pre_cst->cst_madi_thd0.madi_thd1 = 3;
390 p_pre_cst->cst_madi_thd0.madi_thd2 = 3;
391 p_pre_cst->cst_madi_thd0.madi_thd3 = 6;
392 p_pre_cst->cst_madi_thd1.madi_thd4 = 5;
393 p_pre_cst->cst_madi_thd1.madi_thd5 = 7;
394 p_pre_cst->cst_wgt0.wgt0 = 20;
395 p_pre_cst->cst_wgt0.wgt1 = 18;
396 p_pre_cst->cst_wgt0.wgt2 = 19;
397 p_pre_cst->cst_wgt0.wgt3 = 18;
398 p_pre_cst->cst_wgt1.wgt4 = 6;
399 p_pre_cst->cst_wgt1.wgt5 = 9;
400 p_pre_cst->cst_wgt1.wgt6 = 14;
401 p_pre_cst->cst_wgt1.wgt7 = 18;
402 p_pre_cst->cst_wgt2.wgt8 = 17;
403 p_pre_cst->cst_wgt2.wgt9 = 17;
404 p_pre_cst->cst_wgt2.mode_th = 5;
405
406 reg->preintra_sqi_cfg.pre_intra_qp_thd = 28;
407 reg->preintra_sqi_cfg.pre_intra4_lambda_mv_bit = 3;
408 reg->preintra_sqi_cfg.pre_intra8_lambda_mv_bit = 4;
409 reg->preintra_sqi_cfg.pre_intra16_lambda_mv_bit = 4;
410 reg->preintra_sqi_cfg.pre_intra32_lambda_mv_bit = 5;
411 reg->rdo_atr_i_cu32_madi_cfg0.i_cu32_madi_thd0 = 3;
412 reg->rdo_atr_i_cu32_madi_cfg0.i_cu32_madi_thd1 = 35;
413 reg->rdo_atr_i_cu32_madi_cfg0.i_cu32_madi_thd2 = 25;
414 reg->rdo_atr_i_cu32_madi_cfg1.i_cu32_madi_cnt_thd3 = 0;
415 reg->rdo_atr_i_cu32_madi_cfg1.i_cu32_madi_thd4 = 20;
416 reg->rdo_atr_i_cu32_madi_cfg1.i_cu32_madi_cost_multi = 24;
417 reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_thd0 = 4;
418 reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_thd1 = 6;
419 reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_cost_multi = 24;
420
421 }
422
vepu540c_h265_global_cfg_set(H265eV540cHalContext * ctx,H265eV540cRegSet * regs)423 static void vepu540c_h265_global_cfg_set(H265eV540cHalContext *ctx, H265eV540cRegSet *regs)
424 {
425 MppEncHwCfg *hw = &ctx->cfg->hw;
426 RK_U32 i;
427 hevc_vepu540c_rc_roi *rc_regs = ®s->reg_rc_roi;
428 hevc_vepu540c_wgt *reg_wgt = ®s->reg_wgt;
429 vepu540c_rdo_cfg *reg_rdo = ®s->reg_rdo;
430 vepu540c_h265_rdo_cfg(reg_rdo);
431
432 if (ctx->frame_type == INTRA_FRAME) {
433 for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
434 rc_regs->aq_tthd[i] = hw->aq_thrd_i[i];
435 rc_regs->aq_step[i] = hw->aq_step_i[i] & 0x3f;
436 }
437 reg_wgt->iprd_lamb_satd_ofst.lambda_satd_offset = 11;
438 memcpy(®_wgt->rdo_wgta_qp_grpa_0_51[0], lamd_moda_qp, sizeof(lamd_moda_qp));
439 } else {
440 for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
441 rc_regs->aq_tthd[i] = hw->aq_thrd_p[i];
442 rc_regs->aq_step[i] = hw->aq_step_p[i] & 0x3f;
443 }
444 reg_wgt->iprd_lamb_satd_ofst.lambda_satd_offset = 11;
445 memcpy(®_wgt->rdo_wgta_qp_grpa_0_51[0], lamd_modb_qp, sizeof(lamd_modb_qp));
446 }
447 reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = 171;
448 reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = 85;
449 if (hw->qbias_en) {
450 reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = hw->qbias_i;
451 reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = hw->qbias_p;
452 }
453 /* CIME */
454 {
455 /* 0x1760 */
456 regs->reg_wgt.me_sqi_cfg.cime_pmv_num = 1;
457 regs->reg_wgt.me_sqi_cfg.cime_fuse = 1;
458 regs->reg_wgt.me_sqi_cfg.itp_mode = 0;
459 regs->reg_wgt.me_sqi_cfg.move_lambda = 2;
460 regs->reg_wgt.me_sqi_cfg.rime_lvl_mrg = 0;
461 regs->reg_wgt.me_sqi_cfg.rime_prelvl_en = 3;
462 regs->reg_wgt.me_sqi_cfg.rime_prersu_en = 3;
463
464 /* 0x1764 */
465 regs->reg_wgt.cime_mvd_th.cime_mvd_th0 = 8;
466 regs->reg_wgt.cime_mvd_th.cime_mvd_th1 = 20;
467 regs->reg_wgt.cime_mvd_th.cime_mvd_th2 = 32;
468
469 /* 0x1768 */
470 regs->reg_wgt.cime_madp_th.cime_madp_th = 16;
471
472 /* 0x176c */
473 regs->reg_wgt.cime_multi.cime_multi0 = 8;
474 regs->reg_wgt.cime_multi.cime_multi1 = 12;
475 regs->reg_wgt.cime_multi.cime_multi2 = 16;
476 regs->reg_wgt.cime_multi.cime_multi3 = 20;
477 }
478
479 /* RIME && FME */
480 {
481 /* 0x1770 */
482 regs->reg_wgt.rime_mvd_th.rime_mvd_th0 = 1;
483 regs->reg_wgt.rime_mvd_th.rime_mvd_th1 = 2;
484 regs->reg_wgt.rime_mvd_th.fme_madp_th = 0;
485
486 /* 0x1774 */
487 regs->reg_wgt.rime_madp_th.rime_madp_th0 = 8;
488 regs->reg_wgt.rime_madp_th.rime_madp_th1 = 16;
489
490 /* 0x1778 */
491 regs->reg_wgt.rime_multi.rime_multi0 = 4;
492 regs->reg_wgt.rime_multi.rime_multi1 = 8;
493 regs->reg_wgt.rime_multi.rime_multi2 = 12;
494
495 /* 0x177C */
496 regs->reg_wgt.cmv_st_th.cmv_th0 = 64;
497 regs->reg_wgt.cmv_st_th.cmv_th1 = 96;
498 regs->reg_wgt.cmv_st_th.cmv_th2 = 128;
499 }
500 }
501
hal_h265e_v540c_init(void * hal,MppEncHalCfg * cfg)502 MPP_RET hal_h265e_v540c_init(void *hal, MppEncHalCfg *cfg)
503 {
504 MPP_RET ret = MPP_OK;
505 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
506 RK_U32 i = 0;
507
508 mpp_env_get_u32("hal_h265e_debug", &hal_h265e_debug, 0);
509
510 hal_h265e_enter();
511
512 for ( i = 0; i < MAX_TITLE_NUM; i++) {
513 ctx->reg_out[i] = mpp_calloc(H265eV540cStatusElem, 1);
514 }
515
516 ctx->regs = mpp_calloc(H265eV540cRegSet, 1);
517 ctx->input_fmt = mpp_calloc(VepuFmtCfg, 1);
518 ctx->cfg = cfg->cfg;
519 hal_bufs_init(&ctx->dpb_bufs);
520
521 ctx->frame_cnt = 0;
522 ctx->frame_cnt_gen_ready = 0;
523 ctx->enc_mode = 1;
524 cfg->type = VPU_CLIENT_RKVENC;
525 ret = mpp_dev_init(&cfg->dev, cfg->type);
526 if (ret) {
527 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
528 return ret;
529 }
530
531 ctx->dev = cfg->dev;
532 ctx->frame_type = INTRA_FRAME;
533
534 { /* setup default hardware config */
535 MppEncHwCfg *hw = &cfg->cfg->hw;
536
537 hw->qp_delta_row_i = 2;
538 hw->qp_delta_row = 2;
539 hw->qbias_i = 171;
540 hw->qbias_p = 85;
541 hw->qbias_en = 0;
542
543 memcpy(hw->aq_thrd_i, aq_thd_default, sizeof(hw->aq_thrd_i));
544 memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p));
545 memcpy(hw->aq_step_i, aq_qp_dealt_default, sizeof(hw->aq_step_i));
546 memcpy(hw->aq_step_p, aq_qp_dealt_default, sizeof(hw->aq_step_p));
547 }
548
549 hal_h265e_leave();
550 return ret;
551 }
552
hal_h265e_v540c_deinit(void * hal)553 MPP_RET hal_h265e_v540c_deinit(void *hal)
554 {
555 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
556 RK_U32 i = 0;
557
558 hal_h265e_enter();
559 MPP_FREE(ctx->regs);
560
561 for ( i = 0; i < MAX_TITLE_NUM; i++) {
562 MPP_FREE(ctx->reg_out[i]);
563 }
564
565 MPP_FREE(ctx->input_fmt);
566 hal_bufs_deinit(ctx->dpb_bufs);
567
568 if (ctx->ext_line_buf) {
569 mpp_buffer_put(ctx->ext_line_buf);
570 ctx->ext_line_buf = NULL;
571 }
572
573 if (ctx->ext_line_buf_grp) {
574 mpp_buffer_group_put(ctx->ext_line_buf_grp);
575 ctx->ext_line_buf_grp = NULL;
576 }
577
578 if (ctx->dev) {
579 mpp_dev_deinit(ctx->dev);
580 ctx->dev = NULL;
581 }
582 hal_h265e_leave();
583 return MPP_OK;
584 }
585
hal_h265e_vepu540c_prepare(void * hal)586 static MPP_RET hal_h265e_vepu540c_prepare(void *hal)
587 {
588 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
589 MppEncPrepCfg *prep = &ctx->cfg->prep;
590
591 hal_h265e_dbg_func("enter %p\n", hal);
592
593 if (prep->change_res) {
594 RK_S32 i;
595
596 // pre-alloc required buffers to reduce first frame delay
597 vepu540c_h265_setup_hal_bufs(ctx);
598 for (i = 0; i < ctx->max_buf_cnt; i++)
599 hal_bufs_get_buf(ctx->dpb_bufs, i);
600
601 prep->change_res = 0;
602 }
603
604 hal_h265e_dbg_func("leave %p\n", hal);
605
606 return MPP_OK;
607 }
608
609 static MPP_RET
vepu540c_h265_set_patch_info(MppDev dev,H265eSyntax_new * syn,VepuFmt input_fmt,HalEncTask * task)610 vepu540c_h265_set_patch_info(MppDev dev, H265eSyntax_new *syn, VepuFmt input_fmt, HalEncTask *task)
611 {
612 RK_U32 hor_stride = syn->pp.hor_stride;
613 RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height;
614 RK_U32 frame_size = hor_stride * ver_stride;
615 RK_U32 u_offset = 0, v_offset = 0;
616 MPP_RET ret = MPP_OK;
617
618
619 if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
620 u_offset = mpp_frame_get_fbc_offset(task->frame);
621 v_offset = 0;
622 mpp_log("fbc case u_offset = %d", u_offset);
623 } else {
624 switch (input_fmt) {
625 case VEPU5xx_FMT_YUV420P: {
626 u_offset = frame_size;
627 v_offset = frame_size * 5 / 4;
628 } break;
629 case VEPU5xx_FMT_YUV420SP:
630 case VEPU5xx_FMT_YUV422SP: {
631 u_offset = frame_size;
632 v_offset = frame_size;
633 } break;
634 case VEPU5xx_FMT_YUV422P: {
635 u_offset = frame_size;
636 v_offset = frame_size * 3 / 2;
637 } break;
638 case VEPU5xx_FMT_YUV400:
639 case VEPU5xx_FMT_YUYV422:
640 case VEPU5xx_FMT_UYVY422: {
641 u_offset = 0;
642 v_offset = 0;
643 } break;
644 case VEPU5xx_FMT_BGR565:
645 case VEPU5xx_FMT_BGR888:
646 case VEPU5xx_FMT_BGRA8888: {
647 u_offset = 0;
648 v_offset = 0;
649 } break;
650 default: {
651 hal_h265e_err("unknown color space: %d\n", input_fmt);
652 u_offset = frame_size;
653 v_offset = frame_size * 5 / 4;
654 }
655 }
656 }
657
658 /* input cb addr */
659 if (u_offset) {
660 ret = mpp_dev_set_reg_offset(dev, 161, u_offset);
661 if (ret)
662 mpp_err_f("set input cb addr offset failed %d\n", ret);
663 }
664
665 /* input cr addr */
666 if (v_offset) {
667 ret = mpp_dev_set_reg_offset(dev, 162, v_offset);
668 if (ret)
669 mpp_err_f("set input cr addr offset failed %d\n", ret);
670 }
671
672 return ret;
673 }
674
675
676 #if 0
677 static MPP_RET vepu540c_h265_set_roi_regs(H265eV540cHalContext *ctx, hevc_vepu540c_base *regs)
678 {
679 /* memset register on start so do not clear registers again here */
680 if (ctx->roi_data) {
681 /* roi setup */
682 MppEncROICfg2 *cfg = ( MppEncROICfg2 *)ctx->roi_data;
683
684 regs->reg0192_enc_pic.roi_en = 1;
685 regs->reg0178_roi_addr = mpp_dev_get_iova_address(ctx->dev, cfg->base_cfg_buf, 0);
686 if (cfg->roi_qp_en) {
687 regs->reg0179_roi_qp_addr = mpp_dev_get_iova_address(ctx->dev, cfg->qp_cfg_buf, 0);
688 regs->reg0228_roi_en.roi_qp_en = 1;
689 }
690
691 if (cfg->roi_amv_en) {
692 regs->reg0180_roi_amv_addr = mpp_dev_get_iova_address(ctx->dev, cfg->amv_cfg_buf, 0);
693 regs->reg0228_roi_en.roi_amv_en = 1;
694 }
695
696 if (cfg->roi_mv_en) {
697 regs->reg0181_roi_mv_addr = mpp_dev_get_iova_address(ctx->dev, cfg->mv_cfg_buf, 0);
698 regs->reg0228_roi_en.roi_mv_en = 1;
699 }
700 }
701
702 return MPP_OK;
703 }
704 #endif
705
vepu540c_h265_set_rc_regs(H265eV540cHalContext * ctx,H265eV540cRegSet * regs,HalEncTask * task)706 static MPP_RET vepu540c_h265_set_rc_regs(H265eV540cHalContext *ctx, H265eV540cRegSet *regs, HalEncTask *task)
707 {
708 H265eSyntax_new *syn = (H265eSyntax_new *)task->syntax.data;
709 EncRcTaskInfo *rc_cfg = &task->rc_task->info;
710 hevc_vepu540c_base *reg_base = ®s->reg_base;
711 hevc_vepu540c_rc_roi *reg_rc = ®s->reg_rc_roi;
712 MppEncCfgSet *cfg = ctx->cfg;
713 MppEncRcCfg *rc = &cfg->rc;
714 MppEncHwCfg *hw = &cfg->hw;
715 MppEncH265Cfg *h265 = &cfg->h265;
716 RK_S32 mb_wd32 = (syn->pp.pic_width + 31) / 32;
717 RK_S32 mb_h32 = (syn->pp.pic_height + 31) / 32;
718
719 RK_U32 ctu_target_bits_mul_16 = (rc_cfg->bit_target << 4) / (mb_wd32 * mb_h32);
720 RK_U32 ctu_target_bits;
721 RK_S32 negative_bits_thd, positive_bits_thd;
722
723 if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
724 reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target;
725 reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target;
726
727 reg_base->reg213_rc_qp.rc_max_qp = rc_cfg->quality_target;
728 reg_base->reg213_rc_qp.rc_min_qp = rc_cfg->quality_target;
729 } else {
730 if (ctu_target_bits_mul_16 >= 0x100000) {
731 ctu_target_bits_mul_16 = 0x50000;
732 }
733 ctu_target_bits = (ctu_target_bits_mul_16 * mb_wd32) >> 4;
734 negative_bits_thd = 0 - 5 * ctu_target_bits / 16;
735 positive_bits_thd = 5 * ctu_target_bits / 16;
736
737 reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target;
738 reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target;
739 reg_base->reg212_rc_cfg.rc_en = 1;
740 reg_base->reg212_rc_cfg.aq_en = 1;
741 reg_base->reg212_rc_cfg.aq_mode = 0;
742 reg_base->reg212_rc_cfg.rc_ctu_num = mb_wd32;
743 reg_base->reg213_rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ?
744 hw->qp_delta_row_i : hw->qp_delta_row;
745 reg_base->reg213_rc_qp.rc_max_qp = rc_cfg->quality_max;
746 reg_base->reg213_rc_qp.rc_min_qp = rc_cfg->quality_min;
747 reg_base->reg214_rc_tgt.ctu_ebit = ctu_target_bits_mul_16;
748
749 reg_rc->rc_dthd_0_8[0] = 4 * negative_bits_thd;
750 reg_rc->rc_dthd_0_8[1] = negative_bits_thd;
751 reg_rc->rc_dthd_0_8[2] = positive_bits_thd;
752 reg_rc->rc_dthd_0_8[3] = 4 * positive_bits_thd;
753 reg_rc->rc_dthd_0_8[4] = 0x7FFFFFFF;
754 reg_rc->rc_dthd_0_8[5] = 0x7FFFFFFF;
755 reg_rc->rc_dthd_0_8[6] = 0x7FFFFFFF;
756 reg_rc->rc_dthd_0_8[7] = 0x7FFFFFFF;
757 reg_rc->rc_dthd_0_8[8] = 0x7FFFFFFF;
758
759 reg_rc->rc_adj0.qp_adj0 = -2;
760 reg_rc->rc_adj0.qp_adj1 = -1;
761 reg_rc->rc_adj0.qp_adj2 = 0;
762 reg_rc->rc_adj0.qp_adj3 = 1;
763 reg_rc->rc_adj0.qp_adj4 = 2;
764 reg_rc->rc_adj1.qp_adj5 = 0;
765 reg_rc->rc_adj1.qp_adj6 = 0;
766 reg_rc->rc_adj1.qp_adj7 = 0;
767 reg_rc->rc_adj1.qp_adj8 = 0;
768 }
769
770 reg_rc->roi_qthd0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
771 reg_rc->roi_qthd0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
772 reg_rc->roi_qthd0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
773 reg_rc->roi_qthd0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
774 reg_rc->roi_qthd0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;
775 reg_rc->roi_qthd1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
776 reg_rc->roi_qthd1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;
777 reg_rc->roi_qthd1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
778 reg_rc->roi_qthd1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;
779 reg_rc->roi_qthd1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
780 reg_rc->roi_qthd2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;
781 reg_rc->roi_qthd2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
782 reg_rc->roi_qthd2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;
783 reg_rc->roi_qthd2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
784 reg_rc->roi_qthd2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;
785 reg_rc->roi_qthd3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
786 reg_rc->roi_qthd3.qpmap_mode = h265->qpmap_mode;
787
788 return MPP_OK;
789 }
790
vepu540c_h265_set_pp_regs(H265eV540cRegSet * regs,VepuFmtCfg * fmt,MppEncPrepCfg * prep_cfg)791 static MPP_RET vepu540c_h265_set_pp_regs(H265eV540cRegSet *regs, VepuFmtCfg *fmt, MppEncPrepCfg *prep_cfg)
792 {
793 hevc_vepu540c_control_cfg *reg_ctl = ®s->reg_ctl;
794 hevc_vepu540c_base *reg_base = ®s->reg_base;
795 RK_S32 stridey = 0;
796 RK_S32 stridec = 0;
797
798 reg_ctl->reg0012_dtrns_map.src_bus_edin = fmt->src_endian;
799 reg_base->reg0198_src_fmt.src_cfmt = fmt->format;
800 reg_base->reg0198_src_fmt.alpha_swap = fmt->alpha_swap;
801 reg_base->reg0198_src_fmt.rbuv_swap = fmt->rbuv_swap;
802
803 reg_base->reg0198_src_fmt.out_fmt = (prep_cfg->format == MPP_FMT_YUV400) ? 0 : 1;
804 reg_base->reg0203_src_proc.src_mirr = prep_cfg->mirroring > 0;
805 reg_base->reg0203_src_proc.src_rot = prep_cfg->rotation;
806
807 if (prep_cfg->hor_stride) {
808 stridey = prep_cfg->hor_stride;
809 } else {
810 if (reg_base->reg0198_src_fmt.src_cfmt == VEPU5xx_FMT_BGRA8888 )
811 stridey = prep_cfg->width * 4;
812 else if (reg_base->reg0198_src_fmt.src_cfmt == VEPU5xx_FMT_BGR888 )
813 stridey = prep_cfg->width * 3;
814 else if (reg_base->reg0198_src_fmt.src_cfmt == VEPU5xx_FMT_BGR565 ||
815 reg_base->reg0198_src_fmt.src_cfmt == VEPU5xx_FMT_YUYV422 ||
816 reg_base->reg0198_src_fmt.src_cfmt == VEPU5xx_FMT_UYVY422)
817 stridey = prep_cfg->width * 2;
818 }
819
820 stridec = (reg_base->reg0198_src_fmt.src_cfmt == VEPU5xx_FMT_YUV422SP ||
821 reg_base->reg0198_src_fmt.src_cfmt == VEPU5xx_FMT_YUV420SP) ?
822 stridey : stridey / 2;
823
824 if (reg_base->reg0198_src_fmt.src_cfmt < VEPU5xx_FMT_ARGB1555) {
825 const VepuRgb2YuvCfg *cfg_coeffs = cfg_coeffs = get_rgb2yuv_cfg(prep_cfg->range, prep_cfg->color);
826
827 hal_h265e_dbg_simple("input color range %d colorspace %d", prep_cfg->range, prep_cfg->color);
828
829 reg_base->reg0199_src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff;
830 reg_base->reg0199_src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff;
831 reg_base->reg0199_src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff;
832
833 reg_base->reg0200_src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff;
834 reg_base->reg0200_src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff;
835 reg_base->reg0200_src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff;
836
837 reg_base->reg0201_src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff;
838 reg_base->reg0201_src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff;
839 reg_base->reg0201_src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff;
840
841 reg_base->reg0202_src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset;
842 reg_base->reg0202_src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset;
843 reg_base->reg0202_src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset;
844
845 hal_h265e_dbg_simple("use color range %d colorspace %d", cfg_coeffs->dst_range, cfg_coeffs->color);
846 }
847
848 reg_base->reg0205_src_strd0.src_strd0 = stridey;
849 reg_base->reg0206_src_strd1.src_strd1 = stridec;
850
851 return MPP_OK;
852 }
853
vepu540c_h265_set_slice_regs(H265eSyntax_new * syn,hevc_vepu540c_base * regs)854 static void vepu540c_h265_set_slice_regs(H265eSyntax_new *syn, hevc_vepu540c_base *regs)
855 {
856 regs->reg0237_synt_sps.smpl_adpt_ofst_e = syn->pp.sample_adaptive_offset_enabled_flag;
857 regs->reg0237_synt_sps.num_st_ref_pic = syn->pp.num_short_term_ref_pic_sets;
858 regs->reg0237_synt_sps.num_lt_ref_pic = syn->pp.num_long_term_ref_pics_sps;
859 regs->reg0237_synt_sps.lt_ref_pic_prsnt = syn->pp.long_term_ref_pics_present_flag;
860 regs->reg0237_synt_sps.tmpl_mvp_e = syn->pp.sps_temporal_mvp_enabled_flag;
861 regs->reg0237_synt_sps.log2_max_poc_lsb = syn->pp.log2_max_pic_order_cnt_lsb_minus4;
862 regs->reg0237_synt_sps.strg_intra_smth = syn->pp.strong_intra_smoothing_enabled_flag;
863
864 regs->reg0238_synt_pps.dpdnt_sli_seg_en = syn->pp.dependent_slice_segments_enabled_flag;
865 regs->reg0238_synt_pps.out_flg_prsnt_flg = syn->pp.output_flag_present_flag;
866 regs->reg0238_synt_pps.num_extr_sli_hdr = syn->pp.num_extra_slice_header_bits;
867 regs->reg0238_synt_pps.sgn_dat_hid_en = syn->pp.sign_data_hiding_enabled_flag;
868 regs->reg0238_synt_pps.cbc_init_prsnt_flg = syn->pp.cabac_init_present_flag;
869 regs->reg0238_synt_pps.pic_init_qp = syn->pp.init_qp_minus26 + 26;
870 regs->reg0238_synt_pps.cu_qp_dlt_en = syn->pp.cu_qp_delta_enabled_flag;
871 regs->reg0238_synt_pps.chrm_qp_ofst_prsn = syn->pp.pps_slice_chroma_qp_offsets_present_flag;
872 regs->reg0238_synt_pps.lp_fltr_acrs_sli = syn->pp.pps_loop_filter_across_slices_enabled_flag;
873 regs->reg0238_synt_pps.dblk_fltr_ovrd_en = syn->pp.deblocking_filter_override_enabled_flag;
874 regs->reg0238_synt_pps.lst_mdfy_prsnt_flg = syn->pp.lists_modification_present_flag;
875 regs->reg0238_synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag;
876 regs->reg0238_synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth;
877 regs->reg0238_synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag;
878
879 regs->reg0239_synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg;
880 regs->reg0239_synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg;
881 regs->reg0239_synt_sli0.mrg_up_flg = syn->sp.merge_up_flag;
882 regs->reg0239_synt_sli0.mrg_lft_flg = syn->sp.merge_left_flag;
883 regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
884
885 regs->reg0239_synt_sli0.num_refidx_l1_act = syn->sp.num_refidx_l1_act;
886 regs->reg0239_synt_sli0.num_refidx_l0_act = syn->sp.num_refidx_l0_act;
887
888 regs->reg0239_synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd;
889
890 regs->reg0239_synt_sli0.sli_sao_chrm_flg = syn->sp.sli_sao_chrm_flg;
891 regs->reg0239_synt_sli0.sli_sao_luma_flg = syn->sp.sli_sao_luma_flg;
892 regs->reg0239_synt_sli0.sli_tmprl_mvp_e = syn->sp.sli_tmprl_mvp_en;
893 regs->reg0192_enc_pic.num_pic_tot_cur = syn->sp.tot_poc_num;
894
895 regs->reg0239_synt_sli0.pic_out_flg = syn->sp.pic_out_flg;
896 regs->reg0239_synt_sli0.sli_type = syn->sp.slice_type;
897 regs->reg0239_synt_sli0.sli_rsrv_flg = syn->sp.slice_rsrv_flg;
898 regs->reg0239_synt_sli0.dpdnt_sli_seg_flg = syn->sp.dpdnt_sli_seg_flg;
899 regs->reg0239_synt_sli0.sli_pps_id = syn->sp.sli_pps_id;
900 regs->reg0239_synt_sli0.no_out_pri_pic = syn->sp.no_out_pri_pic;
901
902
903 regs->reg0240_synt_sli1.sp_tc_ofst_div2 = syn->sp.sli_tc_ofst_div2;;
904 regs->reg0240_synt_sli1.sp_beta_ofst_div2 = syn->sp.sli_beta_ofst_div2;
905 regs->reg0240_synt_sli1.sli_lp_fltr_acrs_sli = syn->sp.sli_lp_fltr_acrs_sli;
906 regs->reg0240_synt_sli1.sp_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis;
907 regs->reg0240_synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg;
908 regs->reg0240_synt_sli1.sli_cb_qp_ofst = syn->sp.sli_cb_qp_ofst;
909 regs->reg0240_synt_sli1.max_mrg_cnd = syn->sp.max_mrg_cnd;
910
911 regs->reg0240_synt_sli1.col_ref_idx = syn->sp.col_ref_idx;
912 regs->reg0240_synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg;
913 regs->reg0241_synt_sli2.sli_poc_lsb = syn->sp.sli_poc_lsb;
914 regs->reg0241_synt_sli2.sli_hdr_ext_len = syn->sp.sli_hdr_ext_len;
915
916 }
917
vepu540c_h265_set_ref_regs(H265eSyntax_new * syn,hevc_vepu540c_base * regs)918 static void vepu540c_h265_set_ref_regs(H265eSyntax_new *syn, hevc_vepu540c_base *regs)
919 {
920 regs->reg0242_synt_refm0.st_ref_pic_flg = syn->sp.st_ref_pic_flg;
921 regs->reg0242_synt_refm0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0;
922 regs->reg0242_synt_refm0.num_lt_pic = syn->sp.num_lt_pic;
923
924 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
925 regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
926 regs->reg0243_synt_refm1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0;
927 regs->reg0243_synt_refm1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1;
928 regs->reg0243_synt_refm1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2;
929 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
930 regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
931 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1;
932 regs->reg0243_synt_refm1.num_negative_pics = syn->sp.num_neg_pic;
933 regs->reg0243_synt_refm1.num_pos_pic = syn->sp.num_pos_pic;
934
935 regs->reg0243_synt_refm1.used_by_s0_flg = syn->sp.used_by_s0_flg;
936 regs->reg0244_synt_refm2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10;
937 regs->reg0244_synt_refm2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11;
938 regs->reg0245_synt_refm3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12;
939 regs->reg0245_synt_refm3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13;
940
941 regs->reg0246_synt_long_refm0.poc_lsb_lt1 = syn->sp.poc_lsb_lt1;
942 regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1;
943 regs->reg0246_synt_long_refm0.poc_lsb_lt2 = syn->sp.poc_lsb_lt2;
944 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2;
945 regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2;
946 regs->reg0240_synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0;
947 regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
948
949 return;
950 }
vepu540c_h265_set_me_regs(H265eV540cHalContext * ctx,H265eSyntax_new * syn,hevc_vepu540c_base * regs)951 static void vepu540c_h265_set_me_regs(H265eV540cHalContext *ctx, H265eSyntax_new *syn, hevc_vepu540c_base *regs)
952 {
953
954 RK_S32 x_gmv = 0;
955 RK_S32 y_gmv = 0;
956 RK_S32 srch_lftw, srch_rgtw, srch_uph, srch_dwnh;
957 RK_S32 frm_sta = 0, frm_end = 0, pic_w = 0;
958 RK_S32 pic_wdt_align = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 31) / 32 ;
959
960
961 regs->reg0220_me_rnge.cime_srch_dwnh = 15;
962 regs->reg0220_me_rnge.cime_srch_uph = 14;
963 regs->reg0220_me_rnge.cime_srch_rgtw = 12;
964 regs->reg0220_me_rnge.cime_srch_lftw = 12;
965 regs->reg0221_me_cfg.rme_srch_h = 3;
966 regs->reg0221_me_cfg.rme_srch_v = 3;
967
968 regs->reg0221_me_cfg.srgn_max_num = 72;
969 regs->reg0221_me_cfg.cime_dist_thre = 1024;
970 regs->reg0221_me_cfg.rme_dis = 0;
971 regs->reg0221_me_cfg.fme_dis = 0;
972 regs->reg0220_me_rnge.dlt_frm_num = 0x1;
973 srch_lftw = regs->reg0220_me_rnge.cime_srch_lftw * 4;
974 srch_rgtw = regs->reg0220_me_rnge.cime_srch_rgtw * 4;
975 srch_uph = regs->reg0220_me_rnge.cime_srch_uph * 2;
976 srch_dwnh = regs->reg0220_me_rnge.cime_srch_dwnh * 2;
977
978 if (syn->pp.sps_temporal_mvp_enabled_flag &&
979 (ctx->frame_type != INTRA_FRAME)) {
980 if (ctx->last_frame_type == INTRA_FRAME) {
981 regs->reg0222_me_cach.colmv_load = 0;
982 } else {
983 regs->reg0222_me_cach.colmv_load = 1;
984 }
985 regs->reg0222_me_cach.colmv_stor = 1;
986 }
987 // calc cme_linebuf_w
988 {
989 if (x_gmv - srch_lftw < 0) {
990 frm_sta = (x_gmv - srch_lftw - 15) / 16;
991 } else {
992 frm_sta = (x_gmv - srch_lftw) / 16;
993 }
994 if (x_gmv + srch_rgtw < 0) {
995 frm_end = pic_wdt_align - 1 + (x_gmv + srch_rgtw) / 16;
996 } else {
997 frm_end = pic_wdt_align - 1 + (x_gmv + srch_rgtw + 15) / 16;
998 }
999
1000 if (frm_sta < 0) {
1001 frm_sta = 0;
1002 } else if (frm_sta > pic_wdt_align - 1) {
1003 frm_sta = pic_wdt_align - 1;
1004 }
1005 frm_end = mpp_clip(frm_end, 0, pic_wdt_align - 1);
1006 pic_w = (frm_end - frm_sta + 1) * 32;
1007 regs->reg0222_me_cach.cme_linebuf_w = pic_w / 32;
1008 }
1009
1010 // calc cime_hgt_rama and cime_size_rama
1011 {
1012 RK_U32 rama_size = 1796;
1013 RK_U32 ramb_h;
1014 RK_U32 ctu_2_h = 4;
1015 RK_U32 ctu_8_w = 1 ;
1016 RK_U32 cur_srch_8_w, cur_srch_2_h, cur_srch_h;
1017
1018 if ((y_gmv % 8 - srch_uph % 8) < 0) {
1019 cur_srch_2_h = (8 + (y_gmv % 8 - srch_uph % 8) % 8 + srch_uph + srch_dwnh) / 2 + ctu_2_h;
1020 } else {
1021 cur_srch_2_h = ((y_gmv % 8 - srch_uph % 8) % 8 + srch_uph + srch_dwnh) / 2 + ctu_2_h;
1022 }
1023 regs->reg0222_me_cach.cime_size_rama = (cur_srch_2_h + 3) / 4 * 4;
1024
1025 if ((x_gmv % 8 - srch_lftw % 8) < 0) {
1026 cur_srch_8_w = (8 + (x_gmv % 8 - srch_lftw % 8) % 8 + srch_lftw + srch_rgtw + 7) / 8 + ctu_8_w;
1027 } else {
1028 cur_srch_8_w = ((x_gmv % 8 - srch_lftw % 8) % 8 + srch_lftw + srch_rgtw + 7) / 8 + ctu_8_w;
1029 }
1030
1031 cur_srch_h = ctu_2_h;
1032 ramb_h = cur_srch_2_h;
1033 while ((rama_size > ((cur_srch_h - ctu_2_h) * regs->reg0222_me_cach.cme_linebuf_w + (ramb_h * cur_srch_8_w)))
1034 && (cur_srch_h < regs->reg0222_me_cach.cime_size_rama)) {
1035 cur_srch_h = cur_srch_h + ctu_2_h;
1036 if (ramb_h > ctu_2_h * 2) {
1037 ramb_h = ramb_h - ctu_2_h;
1038 } else {
1039 ramb_h = ctu_2_h;
1040 }
1041 }
1042
1043 if (cur_srch_2_h == ctu_2_h * 2) {
1044 cur_srch_h = cur_srch_h + ctu_2_h;
1045 ramb_h = ctu_2_h;
1046 }
1047
1048 if (rama_size < ((cur_srch_h - ctu_2_h) * regs->reg0222_me_cach.cme_linebuf_w + (ramb_h * cur_srch_8_w))) {
1049 cur_srch_h = cur_srch_h - ctu_2_h;
1050 }
1051
1052 regs->reg0222_me_cach.cime_size_rama = ((cur_srch_h - ctu_2_h) * regs->reg0222_me_cach.cme_linebuf_w + ctu_2_h * cur_srch_8_w) / 4;
1053 regs->reg0222_me_cach.cime_hgt_rama = cur_srch_h / 2;
1054 regs->reg0222_me_cach.fme_prefsu_en = 1;
1055 }
1056
1057 }
1058
vepu540c_h265_set_hw_address(H265eV540cHalContext * ctx,hevc_vepu540c_base * regs,HalEncTask * task)1059 void vepu540c_h265_set_hw_address(H265eV540cHalContext *ctx, hevc_vepu540c_base *regs, HalEncTask *task)
1060 {
1061 HalEncTask *enc_task = task;
1062 HalBuf *recon_buf, *ref_buf;
1063 MppBuffer md_info_buf = enc_task->md_info;
1064 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
1065
1066 hal_h265e_enter();
1067
1068 regs->reg0160_adr_src0 = mpp_buffer_get_fd(enc_task->input);
1069 regs->reg0161_adr_src1 = regs->reg0160_adr_src0;
1070 regs->reg0162_adr_src2 = regs->reg0160_adr_src0;
1071
1072 recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx);
1073 ref_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.ref_pic.slot_idx);
1074
1075 if (!syn->sp.non_reference_flag) {
1076 regs->reg0163_rfpw_h_addr = mpp_buffer_get_fd(recon_buf->buf[0]);
1077 regs->reg0164_rfpw_b_addr = regs->reg0163_rfpw_h_addr;
1078 mpp_dev_set_reg_offset(ctx->dev, 164, ctx->fbc_header_len);
1079 }
1080 regs->reg0165_rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]);
1081 regs->reg0166_rfpr_b_addr = regs->reg0165_rfpr_h_addr;
1082 regs->reg0167_cmvw_addr = mpp_buffer_get_fd(recon_buf->buf[2]);
1083 regs->reg0168_cmvr_addr = mpp_buffer_get_fd(ref_buf->buf[2]);
1084 regs->reg0169_dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]);
1085 regs->reg0170_dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]);
1086
1087 mpp_dev_set_reg_offset(ctx->dev, 166, ctx->fbc_header_len);
1088
1089 if (md_info_buf) {
1090 regs->reg0192_enc_pic.mei_stor = 1;
1091 regs->reg0171_meiw_addr = mpp_buffer_get_fd(md_info_buf);
1092 } else {
1093 regs->reg0192_enc_pic.mei_stor = 0;
1094 regs->reg0171_meiw_addr = 0;
1095 }
1096
1097 regs->reg0172_bsbt_addr = mpp_buffer_get_fd(enc_task->output);
1098 /* TODO: stream size relative with syntax */
1099 regs->reg0173_bsbb_addr = regs->reg0172_bsbt_addr;
1100 regs->reg0175_bsbr_addr = regs->reg0172_bsbt_addr;
1101 regs->reg0174_adr_bsbs = regs->reg0172_bsbt_addr;
1102
1103 regs->reg0180_adr_rfpt_h = 0xffffffff;
1104 regs->reg0181_adr_rfpb_h = 0;
1105 regs->reg0182_adr_rfpt_b = 0xffffffff;
1106 regs->reg0183_adr_rfpb_b = 0;
1107
1108
1109 mpp_dev_set_reg_offset(ctx->dev, 174, mpp_packet_get_length(task->packet));
1110 mpp_dev_set_reg_offset(ctx->dev, 172, mpp_buffer_get_size(enc_task->output));
1111
1112 regs->reg0204_pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
1113 regs->reg0204_pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
1114 }
1115
setup_vepu540c_ext_line_buf(H265eV540cHalContext * ctx,H265eV540cRegSet * regs)1116 static void setup_vepu540c_ext_line_buf(H265eV540cHalContext *ctx, H265eV540cRegSet *regs)
1117 {
1118 if (ctx->ext_line_buf) {
1119 RK_S32 fd = mpp_buffer_get_fd(ctx->ext_line_buf);
1120
1121 regs->reg_base.reg0179_adr_ebufb = fd;
1122 regs->reg_base.reg0178_adr_ebuft = fd;
1123 mpp_dev_set_reg_offset(ctx->dev, 178, ctx->ext_line_buf_size);
1124 } else {
1125 regs->reg_base.reg0179_adr_ebufb = 0;
1126 regs->reg_base.reg0178_adr_ebuft = 0;
1127 }
1128 }
1129
vepu540c_h265_set_split(H265eV540cRegSet * regs,MppEncCfgSet * enc_cfg,RK_U32 title_en)1130 static void vepu540c_h265_set_split(H265eV540cRegSet *regs, MppEncCfgSet *enc_cfg, RK_U32 title_en)
1131 {
1132 MppEncSliceSplit *cfg = &enc_cfg->split;
1133
1134 hal_h265e_dbg_func("enter\n");
1135
1136 switch (cfg->split_mode) {
1137 case MPP_ENC_SPLIT_NONE : {
1138 regs->reg_base.reg0216_sli_splt.sli_splt = 0;
1139 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 0;
1140 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;
1141 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 0;
1142 regs->reg_base.reg0216_sli_splt.sli_flsh = 0;
1143 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = 0;
1144
1145 regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0;
1146 regs->reg_base.reg0192_enc_pic.slen_fifo = 0;
1147 } break;
1148 case MPP_ENC_SPLIT_BY_BYTE : {
1149 regs->reg_base.reg0216_sli_splt.sli_splt = 1;
1150 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 0;
1151 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;
1152 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 500;
1153 regs->reg_base.reg0216_sli_splt.sli_flsh = 1;
1154 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = 0;
1155
1156 regs->reg_base.reg0217_sli_byte.sli_splt_byte = cfg->split_arg;
1157 regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
1158 regs->reg_ctl.reg0008_int_en.vslc_done_en = regs->reg_base.reg0192_enc_pic.slen_fifo;
1159 } break;
1160 case MPP_ENC_SPLIT_BY_CTU : {
1161 RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 64) / 64;
1162 RK_U32 mb_h = MPP_ALIGN(enc_cfg->prep.height, 64) / 64;
1163 RK_U32 slice_num = 0;
1164
1165 if (title_en)
1166 mb_w = mb_w / 2;
1167
1168 slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg;
1169
1170 regs->reg_base.reg0216_sli_splt.sli_splt = 1;
1171 regs->reg_base.reg0216_sli_splt.sli_splt_mode = 1;
1172 regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;
1173 regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 500;
1174 regs->reg_base.reg0216_sli_splt.sli_flsh = 1;
1175 regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1;
1176
1177 regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0;
1178 regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
1179
1180 if ((cfg->split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) ||
1181 (regs->reg_base.reg0192_enc_pic.slen_fifo && (slice_num > VEPU540C_SLICE_FIFO_LEN)))
1182 regs->reg_ctl.reg0008_int_en.vslc_done_en = 1 ;
1183 } break;
1184 default : {
1185 mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
1186 } break;
1187 }
1188
1189 hal_h265e_dbg_func("leave\n");
1190 }
1191
hal_h265e_v540c_gen_regs(void * hal,HalEncTask * task)1192 MPP_RET hal_h265e_v540c_gen_regs(void *hal, HalEncTask *task)
1193 {
1194 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
1195 HalEncTask *enc_task = task;
1196 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
1197 H265eV540cRegSet *regs = ctx->regs;
1198 RK_U32 pic_width_align8, pic_height_align8;
1199 RK_S32 pic_wd32, pic_h32;
1200 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
1201 hevc_vepu540c_control_cfg *reg_ctl = ®s->reg_ctl;
1202 hevc_vepu540c_base *reg_base = ®s->reg_base;
1203 hevc_vepu540c_rc_roi *reg_klut = ®s->reg_rc_roi;
1204
1205 hal_h265e_enter();
1206 pic_width_align8 = (syn->pp.pic_width + 7) & (~7);
1207 pic_height_align8 = (syn->pp.pic_height + 7) & (~7);
1208 pic_wd32 = (syn->pp.pic_width + 31) / 32;
1209 pic_h32 = (syn->pp.pic_height + 31) / 32;
1210
1211 hal_h265e_dbg_simple("frame %d | type %d | start gen regs",
1212 ctx->frame_cnt, ctx->frame_type);
1213
1214 memset(regs, 0, sizeof(H265eV540cRegSet));
1215
1216 reg_ctl->reg0004_enc_strt.lkt_num = 0;
1217 reg_ctl->reg0004_enc_strt.vepu_cmd = ctx->enc_mode;
1218 reg_ctl->reg0005_enc_clr.safe_clr = 0x0;
1219 reg_ctl->reg0005_enc_clr.force_clr = 0x0;
1220
1221 reg_ctl->reg0008_int_en.enc_done_en = 1;
1222 reg_ctl->reg0008_int_en.lkt_node_done_en = 1;
1223 reg_ctl->reg0008_int_en.sclr_done_en = 1;
1224 reg_ctl->reg0008_int_en.vslc_done_en = 0;
1225 reg_ctl->reg0008_int_en.vbsf_oflw_en = 1;
1226 reg_ctl->reg0008_int_en.vbuf_lens_en = 1;
1227 reg_ctl->reg0008_int_en.enc_err_en = 1;
1228 reg_ctl->reg0008_int_en.dvbm_fcfg_en = 1;
1229 reg_ctl->reg0008_int_en.wdg_en = 1;
1230 reg_ctl->reg0008_int_en.lkt_err_int_en = 0;
1231 reg_ctl->reg0008_int_en.lkt_err_stop_en = 1;
1232 reg_ctl->reg0008_int_en.lkt_force_stop_en = 1;
1233 reg_ctl->reg0008_int_en.jslc_done_en = 1;
1234 reg_ctl->reg0008_int_en.jbsf_oflw_en = 1;
1235 reg_ctl->reg0008_int_en.jbuf_lens_en = 1;
1236 reg_ctl->reg0008_int_en.dvbm_dcnt_en = 1;
1237
1238 reg_ctl->reg0012_dtrns_map.jpeg_bus_edin = 0x0;
1239 reg_ctl->reg0012_dtrns_map.src_bus_edin = 0x0;
1240 reg_ctl->reg0012_dtrns_map.meiw_bus_edin = 0x0;
1241 reg_ctl->reg0012_dtrns_map.bsw_bus_edin = 0x7;
1242 reg_ctl->reg0012_dtrns_map.lktr_bus_edin = 0x0;
1243 reg_ctl->reg0012_dtrns_map.roir_bus_edin = 0x0;
1244 reg_ctl->reg0012_dtrns_map.lktw_bus_edin = 0x0;
1245 reg_ctl->reg0012_dtrns_map.rec_nfbc_bus_edin = 0x0;
1246 /* enable rdo clk gating */
1247 {
1248 RK_U32 *rdo_ckg = (RK_U32*)®_ctl->reg0022_rdo_ckg;
1249
1250 *rdo_ckg = 0xffffffff;
1251 }
1252 // reg_ctl->reg0013_dtrns_cfg.dspr_otsd = (ctx->frame_type == INTER_P_FRAME);
1253 reg_ctl->reg0013_dtrns_cfg.axi_brsp_cke = 0x0;
1254 reg_ctl->reg0014_enc_wdg.vs_load_thd = 0x1fffff;
1255 reg_ctl->reg0014_enc_wdg.rfp_load_thd = 0xff;
1256
1257 reg_ctl->reg0021_func_en.cke = 1;
1258 reg_ctl->reg0021_func_en.resetn_hw_en = 1;
1259 reg_ctl->reg0021_func_en.enc_done_tmvp_en = 1;
1260
1261 reg_base->reg0196_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1;
1262 reg_base->reg0197_src_fill.pic_wfill = (syn->pp.pic_width & 0x7)
1263 ? (8 - (syn->pp.pic_width & 0x7)) : 0;
1264 reg_base->reg0196_enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1;
1265 reg_base->reg0197_src_fill.pic_hfill = (syn->pp.pic_height & 0x7)
1266 ? (8 - (syn->pp.pic_height & 0x7)) : 0;
1267
1268 reg_base->reg0192_enc_pic.enc_stnd = 1; //H265
1269 reg_base->reg0192_enc_pic.cur_frm_ref = !syn->sp.non_reference_flag; //current frame will be refered
1270 reg_base->reg0192_enc_pic.bs_scp = 1;
1271 reg_base->reg0192_enc_pic.log2_ctu_num = mpp_ceil_log2(pic_wd32 * pic_h32);
1272
1273 reg_base->reg0203_src_proc.src_mirr = 0;
1274 reg_base->reg0203_src_proc.src_rot = 0;
1275
1276 reg_klut->klut_ofst.chrm_klut_ofst = (ctx->frame_type == INTRA_FRAME) ? 6 :
1277 (ctx->cfg->tune.scene_mode == MPP_ENC_SCENE_MODE_IPC ? 9 : 6);
1278 reg_klut->klut_ofst.inter_chrm_dist_multi = 4;
1279 reg_base->reg0248_sao_cfg.sao_lambda_multi = 5;
1280
1281 vepu540c_h265_set_me_regs(ctx, syn, reg_base);
1282
1283 reg_base->reg0232_rdo_cfg.chrm_spcl = 0;
1284 reg_base->reg0232_rdo_cfg.cu_inter_e = 0x0092;
1285 reg_base->reg0232_rdo_cfg.cu_intra_e = 0xe;
1286 reg_base->reg0232_rdo_cfg.lambda_qp_use_avg_cu16_flag = 1;
1287 reg_base->reg0232_rdo_cfg.yuvskip_calc_en = 1;
1288 reg_base->reg0232_rdo_cfg.atf_e = 1;
1289 reg_base->reg0232_rdo_cfg.atr_e = 1;
1290
1291 if (syn->pp.num_long_term_ref_pics_sps) {
1292 reg_base->reg0232_rdo_cfg.ltm_col = 0;
1293 reg_base->reg0232_rdo_cfg.ltm_idx0l0 = 1;
1294 } else {
1295 reg_base->reg0232_rdo_cfg.ltm_col = 0;
1296 reg_base->reg0232_rdo_cfg.ltm_idx0l0 = 0;
1297 }
1298
1299 reg_base->reg0232_rdo_cfg.ccwa_e = 1;
1300 reg_base->reg0232_rdo_cfg.scl_lst_sel = syn->pp.scaling_list_enabled_flag;
1301 reg_base->reg0236_synt_nal.nal_unit_type = h265e_get_nal_type(&syn->sp, ctx->frame_type);
1302
1303 vepu540c_h265_set_hw_address(ctx, reg_base, task);
1304 vepu540c_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep);
1305 vepu540c_h265_set_rc_regs(ctx, regs, task);
1306 vepu540c_h265_set_slice_regs(syn, reg_base);
1307 vepu540c_h265_set_ref_regs(syn, reg_base);
1308 vepu540c_h265_set_patch_info(ctx->dev, syn, (VepuFmt)fmt->format, enc_task);
1309 setup_vepu540c_ext_line_buf(ctx, ctx->regs);
1310 vepu540c_h265_set_split(regs, ctx->cfg, syn->pp.tiles_enabled_flag);
1311
1312 /* ROI configure */
1313 if (ctx->roi_data)
1314 vepu540c_set_roi(®s->reg_rc_roi.roi_cfg, ctx->roi_data,
1315 ctx->cfg->prep.width, ctx->cfg->prep.height);
1316 /*paramet cfg*/
1317 vepu540c_h265_global_cfg_set(ctx, regs);
1318
1319 ctx->frame_num++;
1320
1321 hal_h265e_leave();
1322 return MPP_OK;
1323 }
1324
hal_h265e_v540c_start(void * hal,HalEncTask * enc_task)1325 MPP_RET hal_h265e_v540c_start(void *hal, HalEncTask *enc_task)
1326 {
1327 MPP_RET ret = MPP_OK;
1328 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
1329 RK_U32 *regs = (RK_U32*)ctx->regs;
1330 H265eV540cRegSet *hw_regs = ctx->regs;
1331 H265eV540cStatusElem *reg_out = (H265eV540cStatusElem *)ctx->reg_out[0];
1332 MppDevRegWrCfg cfg;
1333 MppDevRegRdCfg cfg1;
1334 RK_U32 i = 0;
1335 hal_h265e_enter();
1336
1337 if (enc_task->flags.err) {
1338 hal_h265e_err("enc_task->flags.err %08x, return e arly",
1339 enc_task->flags.err);
1340 return MPP_NOK;
1341 }
1342
1343 cfg.reg = (RK_U32*)&hw_regs->reg_ctl;
1344 cfg.size = sizeof(hevc_vepu540c_control_cfg);
1345 cfg.offset = VEPU540C_CTL_OFFSET;
1346
1347 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
1348 if (ret) {
1349 mpp_err_f("set register write failed %d\n", ret);
1350 return ret;
1351 }
1352
1353 if (hal_h265e_debug & HAL_H265E_DBG_CTL_REGS) {
1354 regs = (RK_U32*)&hw_regs->reg_ctl;
1355 for (i = 0; i < sizeof(hevc_vepu540c_control_cfg) / 4; i++) {
1356 hal_h265e_dbg_ctl("ctl reg[%04x]: 0%08x\n", i * 4, regs[i]);
1357 }
1358 }
1359
1360 cfg.reg = &hw_regs->reg_base;
1361 cfg.size = sizeof(hevc_vepu540c_base);
1362 cfg.offset = VEPU540C_BASE_OFFSET;
1363
1364 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
1365 if (ret) {
1366 mpp_err_f("set register write failed %d\n", ret);
1367 return ret;
1368 }
1369
1370 if (hal_h265e_debug & HAL_H265E_DBG_REGS) {
1371 regs = (RK_U32*)(&hw_regs->reg_base);
1372 for (i = 0; i < 32; i++) {
1373 hal_h265e_dbg_regs("hw add cfg reg[%04x]: 0%08x\n", i * 4, regs[i]);
1374 }
1375 regs += 32;
1376 for (i = 0; i < (sizeof(hevc_vepu540c_base) - 128) / 4; i++) {
1377 hal_h265e_dbg_regs("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
1378 }
1379 }
1380 cfg.reg = &hw_regs->reg_rc_roi;
1381 cfg.size = sizeof(hevc_vepu540c_rc_roi);
1382 cfg.offset = VEPU540C_RCROI_OFFSET;
1383
1384 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
1385 if (ret) {
1386 mpp_err_f("set register write failed %d\n", ret);
1387 return ret;
1388 }
1389
1390 if (hal_h265e_debug & HAL_H265E_DBG_RCKUT_REGS) {
1391 regs = (RK_U32*)&hw_regs->reg_rc_roi;
1392 for (i = 0; i < sizeof(hevc_vepu540c_rc_roi) / 4; i++) {
1393 hal_h265e_dbg_rckut("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
1394 }
1395 }
1396
1397 cfg.reg = &hw_regs->reg_wgt;
1398 cfg.size = sizeof(hevc_vepu540c_wgt);
1399 cfg.offset = VEPU540C_WEG_OFFSET;
1400
1401 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
1402 if (ret) {
1403 mpp_err_f("set register write failed %d\n", ret);
1404 return ret;
1405 }
1406
1407 if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) {
1408 regs = (RK_U32*)&hw_regs->reg_wgt;
1409 for (i = 0; i < sizeof(hevc_vepu540c_wgt) / 4; i++) {
1410 hal_h265e_dbg_wgt("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
1411 }
1412 }
1413
1414 cfg.reg = &hw_regs->reg_rdo;
1415 cfg.size = sizeof(vepu540c_rdo_cfg);
1416 cfg.offset = VEPU540C_RDOCFG_OFFSET;
1417
1418 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
1419 if (ret) {
1420 mpp_err_f("set register write failed %d\n", ret);
1421 return ret;
1422 }
1423
1424 cfg1.reg = ®_out->hw_status;
1425 cfg1.size = sizeof(RK_U32);
1426 cfg1.offset = VEPU540C_REG_BASE_HW_STATUS;
1427
1428 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
1429 if (ret) {
1430 mpp_err_f("set register read failed %d\n", ret);
1431 return ret;
1432 }
1433
1434 cfg1.reg = ®_out->st;
1435 cfg1.size = sizeof(H265eV540cStatusElem) - 4;
1436 cfg1.offset = VEPU540C_STATUS_OFFSET;
1437
1438 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
1439 if (ret) {
1440 mpp_err_f("set register read failed %d\n", ret);
1441 return ret;
1442 }
1443
1444 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
1445 if (ret) {
1446 mpp_err_f("send cmd failed %d\n", ret);
1447 }
1448 hal_h265e_leave();
1449 return ret;
1450 }
1451
vepu540c_h265_set_feedback(H265eV540cHalContext * ctx,HalEncTask * enc_task)1452 static MPP_RET vepu540c_h265_set_feedback(H265eV540cHalContext *ctx, HalEncTask *enc_task)
1453 {
1454 EncRcTaskInfo *hal_rc_ret = (EncRcTaskInfo *)&enc_task->rc_task->info;
1455 vepu540c_h265_fbk *fb = &ctx->feedback;
1456 MppEncCfgSet *cfg = ctx->cfg;
1457 RK_S32 mb64_num = ((cfg->prep.width + 63) / 64) * ((cfg->prep.height + 63) / 64);
1458 RK_S32 mb8_num = (mb64_num << 6);
1459 RK_S32 mb4_num = (mb8_num << 2);
1460 H265eV540cStatusElem *elem = (H265eV540cStatusElem *)ctx->reg_out[0];
1461 vepu540c_hw_status hw_status = elem->hw_status;
1462
1463 hal_h265e_enter();
1464
1465 fb->qp_sum += elem->st.qp_sum;
1466
1467 fb->out_strm_size += elem->st.bs_lgth_l32;
1468
1469 fb->sse_sum += (RK_S64)(elem->st.sse_h32 << 16) +
1470 (elem->st.st_sse_bsl.sse_l16 & 0xffff) ;
1471
1472 fb->hw_status = hw_status;
1473 hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status.val);
1474 if (hw_status.int_sta.enc_done_sta)
1475 hal_h265e_dbg_detail("RKV_ENC_INT_ENC_DONE");
1476
1477 if (hw_status.int_sta.lkt_node_done_sta)
1478 hal_h265e_dbg_detail("RKV_ENC_INT_LKT_NODE_DONE");
1479
1480 if (hw_status.int_sta.sclr_done_sta)
1481 hal_h265e_dbg_detail("RKV_ENC_INT_SCLR_DONE");
1482
1483 if (hw_status.int_sta.vslc_done_sta)
1484 hal_h265e_dbg_detail("RKV_ENC_INT_VSLC_DONE");
1485
1486 if (hw_status.int_sta.vbsf_oflw_sta)
1487 hal_h265e_err("RKV_ENC_INT_VBSF_OFLOW");
1488
1489 if (hw_status.int_sta.vbuf_lens_sta)
1490 hal_h265e_err("RKV_ENC_INT_VBUF_LENS");
1491
1492 if (hw_status.int_sta.enc_err_sta)
1493 hal_h265e_err("RKV_ENC_INT_ENC_ERR");
1494
1495 if (hw_status.int_sta.dvbm_fcfg_sta)
1496 hal_h265e_err("RKV_ENC_INT_DVBM_FCFG");
1497
1498 if (hw_status.int_sta.wdg_sta)
1499 hal_h265e_err("RKV_ENC_INT_WDG_TIMEOUT");
1500
1501 // fb->st_madi += elem->st.madi;
1502 //fb->st_madp += elem->st.madp;
1503 fb->st_mb_num += elem->st.st_bnum_b16.num_b16;
1504 // fb->st_ctu_num += elem->st.st_bnum_cme.num_ctu;
1505
1506 fb->st_lvl64_inter_num += elem->st.st_pnum_p64.pnum_p64;
1507 fb->st_lvl32_inter_num += elem->st.st_pnum_p32.pnum_p32;
1508 fb->st_lvl32_intra_num += elem->st.st_pnum_i32.pnum_i32;
1509 fb->st_lvl16_inter_num += elem->st.st_pnum_p16.pnum_p16;
1510 fb->st_lvl16_intra_num += elem->st.st_pnum_i16.pnum_i16;
1511 fb->st_lvl8_inter_num += elem->st.st_pnum_p8.pnum_p8;
1512 fb->st_lvl8_intra_num += elem->st.st_pnum_i8.pnum_i8;
1513 fb->st_lvl4_intra_num += elem->st.st_pnum_i4.pnum_i4;
1514 memcpy(&fb->st_cu_num_qp[0], &elem->st.st_b8_qp, 52 * sizeof(RK_U32));
1515
1516 hal_rc_ret->bit_real += fb->out_strm_size * 8;
1517
1518 if (fb->st_mb_num) {
1519 fb->st_madi = fb->st_madi / fb->st_mb_num;
1520 } else {
1521 fb->st_madi = 0;
1522 }
1523 if (fb->st_ctu_num) {
1524 fb->st_madp = fb->st_madp / fb->st_ctu_num;
1525 } else {
1526 fb->st_madp = 0;
1527 }
1528
1529 if (mb4_num > 0)
1530 hal_rc_ret->iblk4_prop = ((((fb->st_lvl4_intra_num + fb->st_lvl8_intra_num) << 2) +
1531 (fb->st_lvl16_intra_num << 4) +
1532 (fb->st_lvl32_intra_num << 6)) << 8) / mb4_num;
1533
1534 if (mb64_num > 0) {
1535 /*
1536 hal_cfg[k].inter_lv8_prop = ((fb->st_lvl8_inter_num + (fb->st_lvl16_inter_num << 2) +
1537 (fb->st_lvl32_inter_num << 4) +
1538 (fb->st_lvl64_inter_num << 6)) << 8) / mb8_num;*/
1539
1540 hal_rc_ret->quality_real = fb->qp_sum / mb8_num;
1541 // hal_cfg[k].sse = fb->sse_sum / mb64_num;
1542 }
1543
1544 hal_rc_ret->madi = fb->st_madi;
1545 hal_rc_ret->madp = fb->st_madp;
1546 hal_h265e_leave();
1547 return MPP_OK;
1548 }
1549
1550
1551 //#define DUMP_DATA
hal_h265e_v540c_wait(void * hal,HalEncTask * task)1552 MPP_RET hal_h265e_v540c_wait(void *hal, HalEncTask *task)
1553 {
1554 MPP_RET ret = MPP_OK;
1555 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
1556 HalEncTask *enc_task = task;
1557 H265eV540cStatusElem *elem = (H265eV540cStatusElem *)ctx->reg_out;
1558 hal_h265e_enter();
1559
1560 if (enc_task->flags.err) {
1561 hal_h265e_err("enc_task->flags.err %08x, return early",
1562 enc_task->flags.err);
1563 return MPP_NOK;
1564 }
1565
1566 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
1567
1568 #ifdef DUMP_DATA
1569 static FILE *fp_fbd = NULL;
1570 static FILE *fp_fbh = NULL;
1571 static FILE *fp_dws = NULL;
1572 HalBuf *recon_buf;
1573 static RK_U32 frm_num = 0;
1574 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
1575 recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx);
1576 char file_name[20] = "";
1577 size_t rec_size = mpp_buffer_get_size(recon_buf->buf[0]);
1578 size_t dws_size = mpp_buffer_get_size(recon_buf->buf[1]);
1579
1580 void *ptr = mpp_buffer_get_ptr(recon_buf->buf[0]);
1581 void *dws_ptr = mpp_buffer_get_ptr(recon_buf->buf[1]);
1582
1583 sprintf(&file_name[0], "fbd%d.bin", frm_num);
1584 if (fp_fbd != NULL) {
1585 fclose(fp_fbd);
1586 fp_fbd = NULL;
1587 } else {
1588 fp_fbd = fopen(file_name, "wb+");
1589 }
1590 if (fp_fbd) {
1591 fwrite(ptr + ctx->fbc_header_len, 1, rec_size - ctx->fbc_header_len, fp_fbd);
1592 fflush(fp_fbd);
1593 }
1594
1595 sprintf(&file_name[0], "fbh%d.bin", frm_num);
1596
1597 if (fp_fbh != NULL) {
1598 fclose(fp_fbh);
1599 fp_fbh = NULL;
1600 } else {
1601 fp_fbh = fopen(file_name, "wb+");
1602 }
1603
1604 if (fp_fbh) {
1605 fwrite(ptr , 1, ctx->fbc_header_len, fp_fbh);
1606 fflush(fp_fbh);
1607 }
1608
1609
1610 sprintf(&file_name[0], "dws%d.bin", frm_num);
1611
1612 if (fp_dws != NULL) {
1613 fclose(fp_dws);
1614 fp_dws = NULL;
1615 } else {
1616 fp_dws = fopen(file_name, "wb+");
1617 }
1618
1619 if (fp_dws) {
1620 fwrite(dws_ptr , 1, dws_size, fp_dws);
1621 fflush(fp_dws);
1622 }
1623 frm_num++;
1624 #endif
1625 if (ret)
1626 mpp_err_f("poll cmd failed %d status %d \n", ret, elem->hw_status.val);
1627
1628 hal_h265e_leave();
1629 return ret;
1630 }
1631
hal_h265e_v540c_get_task(void * hal,HalEncTask * task)1632 MPP_RET hal_h265e_v540c_get_task(void *hal, HalEncTask *task)
1633 {
1634 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
1635 MppFrame frame = task->frame;
1636 EncFrmStatus *frm_status = &task->rc_task->frm;
1637
1638 hal_h265e_enter();
1639
1640 if (vepu540c_h265_setup_hal_bufs(ctx)) {
1641 hal_h265e_err("vepu541_h265_allocate_buffers failed, free buffers and return\n");
1642 task->flags.err |= HAL_ENC_TASK_ERR_ALLOC;
1643 return MPP_ERR_MALLOC;
1644 }
1645
1646 ctx->last_frame_type = ctx->frame_type;
1647 if (frm_status->is_intra) {
1648 ctx->frame_type = INTRA_FRAME;
1649 } else {
1650 ctx->frame_type = INTER_P_FRAME;
1651 }
1652 if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
1653 MppMeta meta = mpp_frame_get_meta(frame);
1654
1655 mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
1656 }
1657 memset(&ctx->feedback, 0, sizeof(vepu540c_h265_fbk));
1658
1659 hal_h265e_leave();
1660 return MPP_OK;
1661 }
1662
hal_h265e_v540c_ret_task(void * hal,HalEncTask * task)1663 MPP_RET hal_h265e_v540c_ret_task(void *hal, HalEncTask *task)
1664 {
1665 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
1666 HalEncTask *enc_task = task;
1667 vepu540c_h265_fbk *fb = &ctx->feedback;
1668 EncRcTaskInfo *rc_info = &task->rc_task->info;
1669 RK_U32 offset = mpp_packet_get_length(enc_task->packet);
1670
1671 hal_h265e_enter();
1672
1673 vepu540c_h265_set_feedback(ctx, enc_task);
1674 mpp_buffer_sync_partial_begin(enc_task->output, offset, fb->out_strm_size);
1675 hal_h265e_amend_temporal_id(task, fb->out_strm_size);
1676
1677 rc_info->sse = fb->sse_sum;
1678 rc_info->lvl64_inter_num = fb->st_lvl64_inter_num;
1679 rc_info->lvl32_inter_num = fb->st_lvl32_inter_num;
1680 rc_info->lvl16_inter_num = fb->st_lvl16_inter_num;
1681 rc_info->lvl8_inter_num = fb->st_lvl8_inter_num;
1682 rc_info->lvl32_intra_num = fb->st_lvl32_intra_num;
1683 rc_info->lvl16_intra_num = fb->st_lvl16_intra_num;
1684 rc_info->lvl8_intra_num = fb->st_lvl8_intra_num;
1685 rc_info->lvl4_intra_num = fb->st_lvl4_intra_num;
1686
1687 enc_task->hw_length = fb->out_strm_size;
1688 enc_task->length += fb->out_strm_size;
1689
1690 hal_h265e_dbg_detail("output stream size %d\n", fb->out_strm_size);
1691
1692 hal_h265e_leave();
1693 return MPP_OK;
1694 }
1695
1696 const MppEncHalApi hal_h265e_vepu540c = {
1697 "hal_h265e_v540c",
1698 MPP_VIDEO_CodingHEVC,
1699 sizeof(H265eV540cHalContext),
1700 0,
1701 hal_h265e_v540c_init,
1702 hal_h265e_v540c_deinit,
1703 hal_h265e_vepu540c_prepare,
1704 hal_h265e_v540c_get_task,
1705 hal_h265e_v540c_gen_regs,
1706 hal_h265e_v540c_start,
1707 hal_h265e_v540c_wait,
1708 NULL,
1709 NULL,
1710 hal_h265e_v540c_ret_task,
1711 };
1712