Lines Matching refs:regs
65 #define SET_REF_INFO(regs, index, field, value)\ argument
68 case 0: regs.reg99.ref0_##field = value; break;\
69 case 1: regs.reg99.ref1_##field = value; break;\
70 case 2: regs.reg99.ref2_##field = value; break;\
71 case 3: regs.reg99.ref3_##field = value; break;\
72 case 4: regs.reg100.ref4_##field = value; break;\
73 case 5: regs.reg100.ref5_##field = value; break;\
74 case 6: regs.reg100.ref6_##field = value; break;\
75 case 7: regs.reg100.ref7_##field = value; break;\
76 case 8: regs.reg101.ref8_##field = value; break;\
77 case 9: regs.reg101.ref9_##field = value; break;\
78 case 10: regs.reg101.ref10_##field = value; break;\
79 case 11: regs.reg101.ref11_##field = value; break;\
80 case 12: regs.reg102.ref12_##field = value; break;\
81 case 13: regs.reg102.ref13_##field = value; break;\
82 case 14: regs.reg102.ref14_##field = value; break;\
83 case 15: regs.reg102.ref15_##field = value; break;\
87 #define SET_POC_HIGNBIT_INFO(regs, index, field, value)\ argument
90 case 0: regs.reg200.ref0_##field = value; break;\
91 case 1: regs.reg200.ref1_##field = value; break;\
92 case 2: regs.reg200.ref2_##field = value; break;\
93 case 3: regs.reg200.ref3_##field = value; break;\
94 case 4: regs.reg200.ref4_##field = value; break;\
95 case 5: regs.reg200.ref5_##field = value; break;\
96 case 6: regs.reg200.ref6_##field = value; break;\
97 case 7: regs.reg200.ref7_##field = value; break;\
98 case 8: regs.reg201.ref8_##field = value; break;\
99 case 9: regs.reg201.ref9_##field = value; break;\
100 case 10: regs.reg201.ref10_##field = value; break;\
101 case 11: regs.reg201.ref11_##field = value; break;\
102 case 12: regs.reg201.ref12_##field = value; break;\
103 case 13: regs.reg201.ref13_##field = value; break;\
104 case 14: regs.reg201.ref14_##field = value; break;\
105 case 15: regs.reg201.ref15_##field = value; break;\
106 case 16: regs.reg202.ref16_##field = value; break;\
107 case 17: regs.reg202.ref17_##field = value; break;\
108 case 18: regs.reg202.ref18_##field = value; break;\
109 case 19: regs.reg202.ref19_##field = value; break;\
110 case 20: regs.reg202.ref20_##field = value; break;\
111 case 21: regs.reg202.ref21_##field = value; break;\
112 case 22: regs.reg202.ref22_##field = value; break;\
113 case 23: regs.reg202.ref23_##field = value; break;\
114 case 24: regs.reg203.ref24_##field = value; break;\
115 case 25: regs.reg203.ref25_##field = value; break;\
116 case 26: regs.reg203.ref26_##field = value; break;\
117 case 27: regs.reg203.ref27_##field = value; break;\
118 case 28: regs.reg203.ref28_##field = value; break;\
119 case 29: regs.reg203.ref29_##field = value; break;\
120 case 30: regs.reg203.ref30_##field = value; break;\
121 case 31: regs.reg203.ref31_##field = value; break;\
129 Vdpu34xH264dRegSet *regs; member
163 Vdpu34xH264dRegSet *regs; member
532 static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, HalTaskInfo *task) in set_registers() argument
535 Vdpu34xRegCommon *common = ®s->common; in set_registers()
539 memset(®s->h264d_highpoc, 0, sizeof(regs->h264d_highpoc)); in set_registers()
577 regs->h264d_param.reg65.cur_top_poc = pp->CurrFieldOrderCnt[0]; in set_registers()
578 regs->h264d_param.reg66.cur_bot_poc = pp->CurrFieldOrderCnt[1]; in set_registers()
581 regs->common_addr.reg130_decout_base = fd; in set_registers()
585 regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]); in set_registers()
586 regs->common_addr.reg132_error_ref_base = fd; in set_registers()
593 regs->h264d_highpoc.reg204.cur_poc_highbit = pp->CurrPic.AssociatedFlag; in set_registers()
595 regs->h264d_highpoc.reg204.cur_poc_highbit = 0; in set_registers()
611 regs->h264d_param.reg67_98_ref_poc[2 * i] = pp->FieldOrderCntList[i][0]; in set_registers()
612 regs->h264d_param.reg67_98_ref_poc[2 * i + 1] = pp->FieldOrderCntList[i][1]; in set_registers()
613 SET_REF_INFO(regs->h264d_param, i, field, field_flag); in set_registers()
614 SET_REF_INFO(regs->h264d_param, i, topfield_used, top_used); in set_registers()
615 SET_REF_INFO(regs->h264d_param, i, botfield_used, bot_used); in set_registers()
616 … SET_REF_INFO(regs->h264d_param, i, colmv_use_flag, (pp->RefPicColmvUsedFlags >> i) & 0x01); in set_registers()
626 SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i, poc_highbit, 0); in set_registers()
627 SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i + 1, poc_highbit, 1); in set_registers()
629 SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i, poc_highbit, 3); in set_registers()
630 SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i + 1, poc_highbit, 3); in set_registers()
640 regs->common_addr.reg132_error_ref_base = mpp_buffer_get_fd(mbuffer); in set_registers()
645 regs->h264d_addr.ref_base[i] = mpp_buffer_get_fd(mbuffer); in set_registers()
647 regs->h264d_addr.colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]); in set_registers()
656 regs->common_addr.reg128_rlc_base = mpp_buffer_get_fd(mbuffer); in set_registers()
657 regs->common_addr.reg129_rlcwrite_base = regs->common_addr.reg128_rlc_base; in set_registers()
659 regs->h264d_addr.cabactbl_base = reg_ctx->bufs_fd; in set_registers()
666 static MPP_RET init_common_regs(Vdpu34xH264dRegSet *regs) in init_common_regs() argument
668 Vdpu34xRegCommon *common = ®s->common; in init_common_regs()
728 reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu34xH264dRegSet, 1); in vdpu34x_h264d_init()
729 init_common_regs(reg_ctx->reg_buf[i].regs); in vdpu34x_h264d_init()
736 reg_ctx->regs = reg_ctx->reg_buf[0].regs; in vdpu34x_h264d_init()
774 MPP_FREE(reg_ctx->reg_buf[i].regs); in vdpu34x_h264d_deinit()
795 Vdpu34xH264dRegSet *regs, in h264d_refine_rcb_size() argument
837 if (regs->common.reg012.fbc_e) { in h264d_refine_rcb_size()
846 static void hal_h264d_rcb_info_update(void *hal, Vdpu34xH264dRegSet *regs) in hal_h264d_rcb_info_update() argument
865 h264d_refine_rcb_size(hal, ctx->rcb_info, regs, width, height); in hal_h264d_rcb_info_update()
929 Vdpu34xH264dRegSet *regs = ctx->regs; in vdpu34x_h264d_gen_regs() local
942 regs = ctx->reg_buf[i].regs; in vdpu34x_h264d_gen_regs()
958 set_registers(p_hal, regs, task); in vdpu34x_h264d_gen_regs()
977 regs->h264d_addr.pps_base = ctx->bufs_fd; in vdpu34x_h264d_gen_regs()
981 regs->h264d_addr.rps_base = ctx->bufs_fd; in vdpu34x_h264d_gen_regs()
984 regs->common.reg012.scanlist_addr_valid_en = 1; in vdpu34x_h264d_gen_regs()
987 regs->h264d_addr.scanlist_addr = ctx->bufs_fd; in vdpu34x_h264d_gen_regs()
990 regs->h264d_addr.scanlist_addr = 0; in vdpu34x_h264d_gen_regs()
993 hal_h264d_rcb_info_update(p_hal, regs); in vdpu34x_h264d_gen_regs()
994 vdpu34x_setup_rcb(®s->common_addr, p_hal->dev, p_hal->fast_mode ? in vdpu34x_h264d_gen_regs()
997 vdpu34x_setup_statistic(®s->common, ®s->statistic); in vdpu34x_h264d_gen_regs()
1016 Vdpu34xH264dRegSet *regs = p_hal->fast_mode ? in vdpu34x_h264d_start() local
1017 reg_ctx->reg_buf[task->dec.reg_index].regs : in vdpu34x_h264d_start()
1018 reg_ctx->regs; in vdpu34x_h264d_start()
1025 wr_cfg.reg = ®s->common; in vdpu34x_h264d_start()
1026 wr_cfg.size = sizeof(regs->common); in vdpu34x_h264d_start()
1035 wr_cfg.reg = ®s->h264d_param; in vdpu34x_h264d_start()
1036 wr_cfg.size = sizeof(regs->h264d_param); in vdpu34x_h264d_start()
1045 wr_cfg.reg = ®s->common_addr; in vdpu34x_h264d_start()
1046 wr_cfg.size = sizeof(regs->common_addr); in vdpu34x_h264d_start()
1055 wr_cfg.reg = ®s->h264d_addr; in vdpu34x_h264d_start()
1056 wr_cfg.size = sizeof(regs->h264d_addr); in vdpu34x_h264d_start()
1066 wr_cfg.reg = ®s->h264d_highpoc; in vdpu34x_h264d_start()
1067 wr_cfg.size = sizeof(regs->h264d_highpoc); in vdpu34x_h264d_start()
1076 wr_cfg.reg = ®s->statistic; in vdpu34x_h264d_start()
1077 wr_cfg.size = sizeof(regs->statistic); in vdpu34x_h264d_start()
1086 rd_cfg.reg = ®s->irq_status; in vdpu34x_h264d_start()
1087 rd_cfg.size = sizeof(regs->irq_status); in vdpu34x_h264d_start()
1119 reg_ctx->reg_buf[task->dec.reg_index].regs : in vdpu34x_h264d_wait()
1120 reg_ctx->regs; in vdpu34x_h264d_wait()
1136 param.regs = (RK_U32 *)p_regs; in vdpu34x_h264d_wait()