Lines Matching refs:regs
375 static void setup_vepu541_normal(Vepu541H264eRegSet *regs, RK_U32 is_vepu540) in setup_vepu541_normal() argument
381 regs->reg001.lkt_num = 0; in setup_vepu541_normal()
382 regs->reg001.rkvenc_cmd = 1; in setup_vepu541_normal()
383 regs->reg001.clk_gate_en = 1; in setup_vepu541_normal()
384 regs->reg001.resetn_hw_en = 0; in setup_vepu541_normal()
385 regs->reg001.enc_done_tmvp_en = 1; in setup_vepu541_normal()
388 regs->reg002.safe_clr = 0; in setup_vepu541_normal()
389 regs->reg002.force_clr = 0; in setup_vepu541_normal()
392 regs->reg003.lkt_addr = 0; in setup_vepu541_normal()
395 regs->reg004.enc_done_en = 1; in setup_vepu541_normal()
396 regs->reg004.lkt_done_en = 1; in setup_vepu541_normal()
397 regs->reg004.sclr_done_en = 1; in setup_vepu541_normal()
398 regs->reg004.enc_slice_done_en = 1; in setup_vepu541_normal()
399 regs->reg004.oflw_done_en = 1; in setup_vepu541_normal()
400 regs->reg004.brsp_done_en = 1; in setup_vepu541_normal()
401 regs->reg004.berr_done_en = 1; in setup_vepu541_normal()
402 regs->reg004.rerr_done_en = 1; in setup_vepu541_normal()
403 regs->reg004.wdg_done_en = 0; in setup_vepu541_normal()
406 regs->reg005.enc_done_msk = 0; in setup_vepu541_normal()
407 regs->reg005.lkt_done_msk = 0; in setup_vepu541_normal()
408 regs->reg005.sclr_done_msk = 0; in setup_vepu541_normal()
409 regs->reg005.enc_slice_done_msk = 0; in setup_vepu541_normal()
410 regs->reg005.oflw_done_msk = 0; in setup_vepu541_normal()
411 regs->reg005.brsp_done_msk = 0; in setup_vepu541_normal()
412 regs->reg005.berr_done_msk = 0; in setup_vepu541_normal()
413 regs->reg005.rerr_done_msk = 0; in setup_vepu541_normal()
414 regs->reg005.wdg_done_msk = 0; in setup_vepu541_normal()
419 regs->reg014.vs_load_thd = 0; in setup_vepu541_normal()
420 regs->reg014.rfp_load_thrd = 0; in setup_vepu541_normal()
423 regs->reg015.cmvw_bus_ordr = 0; in setup_vepu541_normal()
424 regs->reg015.dspw_bus_ordr = 0; in setup_vepu541_normal()
425 regs->reg015.rfpw_bus_ordr = 0; in setup_vepu541_normal()
426 regs->reg015.src_bus_edin = 0; in setup_vepu541_normal()
427 regs->reg015.meiw_bus_edin = 0; in setup_vepu541_normal()
428 regs->reg015.bsw_bus_edin = 7; in setup_vepu541_normal()
429 regs->reg015.lktr_bus_edin = 0; in setup_vepu541_normal()
430 regs->reg015.roir_bus_edin = 0; in setup_vepu541_normal()
431 regs->reg015.lktw_bus_edin = 0; in setup_vepu541_normal()
432 regs->reg015.afbc_bsize = 1; in setup_vepu541_normal()
437 regs->reg016.vepu540.axi_brsp_cke = 0; in setup_vepu541_normal()
438 regs->reg016.vepu540.dspr_otsd = 1; in setup_vepu541_normal()
441 regs->reg016.vepu541.axi_brsp_cke = 0; in setup_vepu541_normal()
442 regs->reg016.vepu541.dspr_otsd = 1; in setup_vepu541_normal()
448 static MPP_RET setup_vepu541_prep(Vepu541H264eRegSet *regs, HalH264eVepu541Ctx *ctx, in setup_vepu541_prep() argument
466 regs->reg012.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu541_prep()
467 regs->reg012.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu541_prep()
468 regs->reg012.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu541_prep()
469 regs->reg012.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu541_prep()
472 regs->reg015.src_bus_edin = cfg.src_endian; in setup_vepu541_prep()
475 regs->reg017.src_cfmt = hw_fmt; in setup_vepu541_prep()
476 regs->reg017.alpha_swap = cfg.alpha_swap; in setup_vepu541_prep()
477 regs->reg017.rbuv_swap = cfg.rbuv_swap; in setup_vepu541_prep()
478 regs->reg017.src_range = cfg.src_range; in setup_vepu541_prep()
479 regs->reg017.out_fmt_cfg = (fmt == MPP_FMT_YUV400) ? 1 : 0; in setup_vepu541_prep()
500 regs->reg018.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu541_prep()
501 regs->reg018.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu541_prep()
502 regs->reg018.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu541_prep()
504 regs->reg019.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu541_prep()
505 regs->reg019.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu541_prep()
506 regs->reg019.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu541_prep()
508 regs->reg020.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in setup_vepu541_prep()
509 regs->reg020.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu541_prep()
510 regs->reg020.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu541_prep()
512 regs->reg021.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu541_prep()
513 regs->reg021.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu541_prep()
514 regs->reg021.csc_ofst_v = cfg_coeffs->_2v.offset; in setup_vepu541_prep()
518 regs->reg018.csc_wgt_b2y = cfg.weight[0]; in setup_vepu541_prep()
519 regs->reg018.csc_wgt_g2y = cfg.weight[1]; in setup_vepu541_prep()
520 regs->reg018.csc_wgt_r2y = cfg.weight[2]; in setup_vepu541_prep()
522 regs->reg019.csc_wgt_b2u = cfg.weight[3]; in setup_vepu541_prep()
523 regs->reg019.csc_wgt_g2u = cfg.weight[4]; in setup_vepu541_prep()
524 regs->reg019.csc_wgt_r2u = cfg.weight[5]; in setup_vepu541_prep()
526 regs->reg020.csc_wgt_b2v = cfg.weight[6]; in setup_vepu541_prep()
527 regs->reg020.csc_wgt_g2v = cfg.weight[7]; in setup_vepu541_prep()
528 regs->reg020.csc_wgt_r2v = cfg.weight[8]; in setup_vepu541_prep()
530 regs->reg021.csc_ofst_y = cfg.offset[0]; in setup_vepu541_prep()
531 regs->reg021.csc_ofst_u = cfg.offset[1]; in setup_vepu541_prep()
532 regs->reg021.csc_ofst_v = cfg.offset[2]; in setup_vepu541_prep()
535 regs->reg022.afbcd_en = MPP_FRAME_FMT_IS_FBC(fmt) ? 1 : 0; in setup_vepu541_prep()
536 regs->reg069.src_strd0 = y_stride; in setup_vepu541_prep()
537 regs->reg069.src_strd1 = c_stride; in setup_vepu541_prep()
539 regs->reg022.src_mirr = prep->mirroring > 0; in setup_vepu541_prep()
540 regs->reg022.src_rot = prep->rotation; in setup_vepu541_prep()
541 regs->reg022.txa_en = 1; in setup_vepu541_prep()
543 regs->reg023.sli_crs_en = 1; in setup_vepu541_prep()
545 regs->reg068.pic_ofst_y = 0; in setup_vepu541_prep()
546 regs->reg068.pic_ofst_x = 0; in setup_vepu541_prep()
553 static void setup_vepu541_codec(Vepu541H264eRegSet *regs, H264eSps *sps, in setup_vepu541_codec() argument
558 regs->reg013.enc_stnd = 0; in setup_vepu541_codec()
559 regs->reg013.cur_frm_ref = slice->nal_reference_idc > 0; in setup_vepu541_codec()
560 regs->reg013.bs_scp = 1; in setup_vepu541_codec()
561 regs->reg013.lamb_mod_sel = (slice->slice_type == H264_I_SLICE) ? 0 : 1; in setup_vepu541_codec()
562 regs->reg013.atr_thd_sel = 0; in setup_vepu541_codec()
563 regs->reg013.node_int = 0; in setup_vepu541_codec()
565 regs->reg103.nal_ref_idc = slice->nal_reference_idc; in setup_vepu541_codec()
566 regs->reg103.nal_unit_type = slice->nalu_type; in setup_vepu541_codec()
568 regs->reg104.max_fnum = sps->log2_max_frame_num_minus4; in setup_vepu541_codec()
569 regs->reg104.drct_8x8 = sps->direct8x8_inference; in setup_vepu541_codec()
570 regs->reg104.mpoc_lm4 = sps->log2_max_poc_lsb_minus4; in setup_vepu541_codec()
572 regs->reg105.etpy_mode = pps->entropy_coding_mode; in setup_vepu541_codec()
573 regs->reg105.trns_8x8 = pps->transform_8x8_mode; in setup_vepu541_codec()
574 regs->reg105.csip_flag = pps->constrained_intra_pred; in setup_vepu541_codec()
575 regs->reg105.num_ref0_idx = pps->num_ref_idx_l0_default_active - 1; in setup_vepu541_codec()
576 regs->reg105.num_ref1_idx = pps->num_ref_idx_l1_default_active - 1; in setup_vepu541_codec()
577 regs->reg105.pic_init_qp = pps->pic_init_qp; in setup_vepu541_codec()
578 regs->reg105.cb_ofst = pps->chroma_qp_index_offset; in setup_vepu541_codec()
579 regs->reg105.cr_ofst = pps->second_chroma_qp_index_offset; in setup_vepu541_codec()
580 regs->reg105.wght_pred = pps->weighted_pred; in setup_vepu541_codec()
581 regs->reg105.dbf_cp_flg = pps->deblocking_filter_control; in setup_vepu541_codec()
583 regs->reg106.sli_type = (slice->slice_type == H264_I_SLICE) ? (2) : (0); in setup_vepu541_codec()
584 regs->reg106.pps_id = slice->pic_parameter_set_id; in setup_vepu541_codec()
585 regs->reg106.drct_smvp = 0; in setup_vepu541_codec()
586 regs->reg106.num_ref_ovrd = slice->num_ref_idx_override; in setup_vepu541_codec()
587 regs->reg106.cbc_init_idc = slice->cabac_init_idc; in setup_vepu541_codec()
588 regs->reg106.frm_num = slice->frame_num; in setup_vepu541_codec()
590 …regs->reg107.idr_pic_id = (slice->slice_type == H264_I_SLICE) ? slice->idr_pic_id : (RK_U32)(-… in setup_vepu541_codec()
591 regs->reg107.poc_lsb = slice->pic_order_cnt_lsb; in setup_vepu541_codec()
594 regs->reg108.dis_dblk_idc = slice->disable_deblocking_filter_idc; in setup_vepu541_codec()
595 regs->reg108.sli_alph_ofst = slice->slice_alpha_c0_offset_div2; in setup_vepu541_codec()
603 regs->reg108.ref_list0_rodr = 1; in setup_vepu541_codec()
604 regs->reg108.rodr_pic_idx = rplmo.modification_of_pic_nums_idc; in setup_vepu541_codec()
609 regs->reg108.rodr_pic_num = rplmo.abs_diff_pic_num_minus1; in setup_vepu541_codec()
612 regs->reg108.rodr_pic_num = rplmo.long_term_pic_idx; in setup_vepu541_codec()
621 regs->reg108.ref_list0_rodr = 0; in setup_vepu541_codec()
622 regs->reg108.rodr_pic_idx = 0; in setup_vepu541_codec()
623 regs->reg108.rodr_pic_num = 0; in setup_vepu541_codec()
628 regs->reg109.nopp_flg = 0; in setup_vepu541_codec()
629 regs->reg109.ltrf_flg = 0; in setup_vepu541_codec()
630 regs->reg109.arpm_flg = 0; in setup_vepu541_codec()
631 regs->reg109.mmco4_pre = 0; in setup_vepu541_codec()
632 regs->reg109.mmco_type0 = 0; in setup_vepu541_codec()
633 regs->reg109.mmco_parm0 = 0; in setup_vepu541_codec()
634 regs->reg109.mmco_type1 = 0; in setup_vepu541_codec()
635 regs->reg110.mmco_parm1 = 0; in setup_vepu541_codec()
636 regs->reg109.mmco_type2 = 0; in setup_vepu541_codec()
637 regs->reg110.mmco_parm2 = 0; in setup_vepu541_codec()
638 regs->reg114.long_term_frame_idx0 = 0; in setup_vepu541_codec()
639 regs->reg114.long_term_frame_idx1 = 0; in setup_vepu541_codec()
640 regs->reg114.long_term_frame_idx2 = 0; in setup_vepu541_codec()
646 regs->reg109.nopp_flg = slice->no_output_of_prior_pics; in setup_vepu541_codec()
647 regs->reg109.ltrf_flg = slice->long_term_reference_flag; in setup_vepu541_codec()
652 regs->reg109.arpm_flg = 1; in setup_vepu541_codec()
687 regs->reg109.mmco_type0 = type; in setup_vepu541_codec()
688 regs->reg109.mmco_parm0 = param_0; in setup_vepu541_codec()
689 regs->reg114.long_term_frame_idx0 = param_1; in setup_vepu541_codec()
723 regs->reg109.mmco_type1 = type; in setup_vepu541_codec()
724 regs->reg110.mmco_parm1 = param_0; in setup_vepu541_codec()
725 regs->reg114.long_term_frame_idx1 = param_1; in setup_vepu541_codec()
759 regs->reg109.mmco_type2 = type; in setup_vepu541_codec()
760 regs->reg110.mmco_parm2 = param_0; in setup_vepu541_codec()
761 regs->reg114.long_term_frame_idx2 = param_1; in setup_vepu541_codec()
769 static void setup_vepu541_rdo_pred(Vepu541H264eRegSet *regs, H264eSps *sps, in setup_vepu541_rdo_pred() argument
775 regs->reg025.chrm_klut_ofst = 0; in setup_vepu541_rdo_pred()
776 memcpy(®s->reg026, &h264e_klut_weight[0], CHROMA_KLUT_TAB_SIZE); in setup_vepu541_rdo_pred()
778 regs->reg025.chrm_klut_ofst = 3; in setup_vepu541_rdo_pred()
780 memcpy(®s->reg026, &h264e_klut_weight[3], CHROMA_KLUT_TAB_SIZE); in setup_vepu541_rdo_pred()
782 memcpy(®s->reg026, &h264e_klut_weight[0], CHROMA_KLUT_TAB_SIZE); in setup_vepu541_rdo_pred()
786 regs->reg101.vthd_y = 9; in setup_vepu541_rdo_pred()
787 regs->reg101.vthd_c = 63; in setup_vepu541_rdo_pred()
788 regs->reg102.inter_4x4 = 0; in setup_vepu541_rdo_pred()
789 regs->reg102.rdo_mask = 24; in setup_vepu541_rdo_pred()
790 regs->reg102.atf_intra_e = 1; in setup_vepu541_rdo_pred()
792 regs->reg101.vthd_y = 2501; in setup_vepu541_rdo_pred()
793 regs->reg101.vthd_c = 2501; in setup_vepu541_rdo_pred()
794 regs->reg102.inter_4x4 = 1; in setup_vepu541_rdo_pred()
795 regs->reg102.rdo_mask = 0; in setup_vepu541_rdo_pred()
796 regs->reg102.atf_intra_e = 0; in setup_vepu541_rdo_pred()
799 regs->reg102.rect_size = (sps->profile_idc == H264_PROFILE_BASELINE && in setup_vepu541_rdo_pred()
802 regs->reg102.vlc_lmt = (sps->profile_idc < H264_PROFILE_MAIN) && in setup_vepu541_rdo_pred()
804 regs->reg102.chrm_spcl = 1; in setup_vepu541_rdo_pred()
805 regs->reg102.ccwa_e = 1; in setup_vepu541_rdo_pred()
806 regs->reg102.scl_lst_sel = pps->pic_scaling_matrix_present; in setup_vepu541_rdo_pred()
807 regs->reg102.scl_lst_sel_ = pps->pic_scaling_matrix_present; in setup_vepu541_rdo_pred()
808 regs->reg102.atr_e = 1; in setup_vepu541_rdo_pred()
809 regs->reg102.atf_edg = 0; in setup_vepu541_rdo_pred()
810 regs->reg102.atf_lvl_e = 0; in setup_vepu541_rdo_pred()
811 regs->reg102.satd_byps_flg = 0; in setup_vepu541_rdo_pred()
816 static void setup_vepu541_rc_base(Vepu541H264eRegSet *regs, H264eSps *sps, in setup_vepu541_rc_base() argument
845 regs->reg013.pic_qp = qp_target; in setup_vepu541_rc_base()
847 regs->reg050.rc_en = 1; in setup_vepu541_rc_base()
848 regs->reg050.aq_en = 1; in setup_vepu541_rc_base()
849 regs->reg050.aq_mode = 0; in setup_vepu541_rc_base()
850 regs->reg050.rc_ctu_num = mb_w; in setup_vepu541_rc_base()
852 regs->reg051.rc_qp_range = (slice->slice_type == H264_I_SLICE) ? in setup_vepu541_rc_base()
854 regs->reg051.rc_max_qp = qp_max; in setup_vepu541_rc_base()
855 regs->reg051.rc_min_qp = qp_min; in setup_vepu541_rc_base()
857 regs->reg052.ctu_ebit = mb_target_bits_mul_16; in setup_vepu541_rc_base()
859 regs->reg053.qp_adj0 = -2; in setup_vepu541_rc_base()
860 regs->reg053.qp_adj1 = -1; in setup_vepu541_rc_base()
861 regs->reg053.qp_adj2 = 0; in setup_vepu541_rc_base()
862 regs->reg053.qp_adj3 = 1; in setup_vepu541_rc_base()
863 regs->reg053.qp_adj4 = 2; in setup_vepu541_rc_base()
864 regs->reg054.qp_adj5 = 0; in setup_vepu541_rc_base()
865 regs->reg054.qp_adj6 = 0; in setup_vepu541_rc_base()
866 regs->reg054.qp_adj7 = 0; in setup_vepu541_rc_base()
867 regs->reg054.qp_adj8 = 0; in setup_vepu541_rc_base()
869 regs->reg055_063.rc_dthd[0] = 2 * negative_bits_thd; in setup_vepu541_rc_base()
870 regs->reg055_063.rc_dthd[1] = negative_bits_thd; in setup_vepu541_rc_base()
871 regs->reg055_063.rc_dthd[2] = positive_bits_thd; in setup_vepu541_rc_base()
872 regs->reg055_063.rc_dthd[3] = 2 * positive_bits_thd; in setup_vepu541_rc_base()
873 regs->reg055_063.rc_dthd[4] = 0x7fffffff; in setup_vepu541_rc_base()
874 regs->reg055_063.rc_dthd[5] = 0x7fffffff; in setup_vepu541_rc_base()
875 regs->reg055_063.rc_dthd[6] = 0x7fffffff; in setup_vepu541_rc_base()
876 regs->reg055_063.rc_dthd[7] = 0x7fffffff; in setup_vepu541_rc_base()
877 regs->reg055_063.rc_dthd[8] = 0x7fffffff; in setup_vepu541_rc_base()
879 regs->reg064.qpmin_area0 = qp_min; in setup_vepu541_rc_base()
880 regs->reg064.qpmax_area0 = qp_max; in setup_vepu541_rc_base()
881 regs->reg064.qpmin_area1 = qp_min; in setup_vepu541_rc_base()
882 regs->reg064.qpmax_area1 = qp_max; in setup_vepu541_rc_base()
883 regs->reg064.qpmin_area2 = qp_min; in setup_vepu541_rc_base()
885 regs->reg065.qpmax_area2 = qp_max; in setup_vepu541_rc_base()
886 regs->reg065.qpmin_area3 = qp_min; in setup_vepu541_rc_base()
887 regs->reg065.qpmax_area3 = qp_max; in setup_vepu541_rc_base()
888 regs->reg065.qpmin_area4 = qp_min; in setup_vepu541_rc_base()
889 regs->reg065.qpmax_area4 = qp_max; in setup_vepu541_rc_base()
891 regs->reg066.qpmin_area5 = qp_min; in setup_vepu541_rc_base()
892 regs->reg066.qpmax_area5 = qp_max; in setup_vepu541_rc_base()
893 regs->reg066.qpmin_area6 = qp_min; in setup_vepu541_rc_base()
894 regs->reg066.qpmax_area6 = qp_max; in setup_vepu541_rc_base()
895 regs->reg066.qpmin_area7 = qp_min; in setup_vepu541_rc_base()
897 regs->reg067.qpmax_area7 = qp_max; in setup_vepu541_rc_base()
898 regs->reg067.qpmap_mode = qpmap_mode; in setup_vepu541_rc_base()
903 static void setup_vepu541_io_buf(Vepu541H264eRegSet *regs, MppDev dev, in setup_vepu541_io_buf() argument
921 regs->reg070.adr_src0 = fd_in; in setup_vepu541_io_buf()
922 regs->reg071.adr_src1 = fd_in; in setup_vepu541_io_buf()
923 regs->reg072.adr_src2 = fd_in; in setup_vepu541_io_buf()
925 regs->reg084.bsbb_addr = fd_out; in setup_vepu541_io_buf()
926 regs->reg085.bsbr_addr = fd_out; in setup_vepu541_io_buf()
927 regs->reg086.adr_bsbs = fd_out; in setup_vepu541_io_buf()
928 regs->reg083.bsbt_addr = fd_out; in setup_vepu541_io_buf()
978 static MPP_RET setup_vepu541_intra_refresh(Vepu541H264eRegSet *regs, HalH264eVepu541Ctx *ctx, RK_U3… in setup_vepu541_intra_refresh() argument
1040 regs->reg089.cme_srch_v = 1; in setup_vepu541_intra_refresh()
1051 regs->reg089.cme_srch_h = 1; in setup_vepu541_intra_refresh()
1061 regs->reg013.roi_enc = 1; in setup_vepu541_intra_refresh()
1062 regs->reg073.roi_addr = fd; in setup_vepu541_intra_refresh()
1072 static void setup_vepu541_roi(Vepu541H264eRegSet *regs, HalH264eVepu541Ctx *ctx) in setup_vepu541_roi() argument
1080 regs->reg013.roi_enc = 1; in setup_vepu541_roi()
1081 regs->reg073.roi_addr = mpp_buffer_get_fd(cfg->base_cfg_buf); in setup_vepu541_roi()
1083 regs->reg013.roi_enc = 1; in setup_vepu541_roi()
1084 regs->reg073.roi_addr = mpp_buffer_get_fd(ctx->qpmap); in setup_vepu541_roi()
1117 regs->reg013.roi_enc = 1; in setup_vepu541_roi()
1118 regs->reg073.roi_addr = fd; in setup_vepu541_roi()
1123 regs->reg013.roi_enc = 0; in setup_vepu541_roi()
1124 regs->reg073.roi_addr = 0; in setup_vepu541_roi()
1131 static void setup_vepu541_recn_refr(Vepu541H264eRegSet *regs, MppDev dev, in setup_vepu541_recn_refr() argument
1148 regs->reg074.rfpw_h_addr = fd; in setup_vepu541_recn_refr()
1149 regs->reg075.rfpw_b_addr = fd; in setup_vepu541_recn_refr()
1150 regs->reg080.dspw_addr = mpp_buffer_get_fd(buf_thumb); in setup_vepu541_recn_refr()
1163 regs->reg076.rfpr_h_addr = fd; in setup_vepu541_recn_refr()
1164 regs->reg077.rfpr_b_addr = fd; in setup_vepu541_recn_refr()
1165 regs->reg081.dspr_addr = mpp_buffer_get_fd(buf_thumb); in setup_vepu541_recn_refr()
1173 static void setup_vepu541_split(Vepu541H264eRegSet *regs, MppEncSliceSplit *cfg) in setup_vepu541_split() argument
1179 regs->reg087.sli_splt = 0; in setup_vepu541_split()
1180 regs->reg087.sli_splt_mode = 0; in setup_vepu541_split()
1181 regs->reg087.sli_splt_cpst = 0; in setup_vepu541_split()
1182 regs->reg087.sli_max_num_m1 = 0; in setup_vepu541_split()
1183 regs->reg087.sli_flsh = 0; in setup_vepu541_split()
1184 regs->reg087.sli_splt_cnum_m1 = 0; in setup_vepu541_split()
1186 regs->reg088.sli_splt_byte = 0; in setup_vepu541_split()
1187 regs->reg013.slen_fifo = 0; in setup_vepu541_split()
1190 regs->reg087.sli_splt = 1; in setup_vepu541_split()
1191 regs->reg087.sli_splt_mode = 0; in setup_vepu541_split()
1192 regs->reg087.sli_splt_cpst = 0; in setup_vepu541_split()
1193 regs->reg087.sli_max_num_m1 = 500; in setup_vepu541_split()
1194 regs->reg087.sli_flsh = 1; in setup_vepu541_split()
1195 regs->reg087.sli_splt_cnum_m1 = 0; in setup_vepu541_split()
1197 regs->reg088.sli_splt_byte = cfg->split_arg; in setup_vepu541_split()
1198 regs->reg013.slen_fifo = 0; in setup_vepu541_split()
1201 regs->reg087.sli_splt = 1; in setup_vepu541_split()
1202 regs->reg087.sli_splt_mode = 1; in setup_vepu541_split()
1203 regs->reg087.sli_splt_cpst = 0; in setup_vepu541_split()
1204 regs->reg087.sli_max_num_m1 = 500; in setup_vepu541_split()
1205 regs->reg087.sli_flsh = 1; in setup_vepu541_split()
1206 regs->reg087.sli_splt_cnum_m1 = cfg->split_arg - 1; in setup_vepu541_split()
1208 regs->reg088.sli_splt_byte = 0; in setup_vepu541_split()
1209 regs->reg013.slen_fifo = 0; in setup_vepu541_split()
1219 static void setup_vepu540_force_slice_split(Vepu541H264eRegSet *regs, RK_S32 width) in setup_vepu540_force_slice_split() argument
1225 regs->reg087.sli_splt = 1; in setup_vepu540_force_slice_split()
1226 regs->reg087.sli_splt_mode = 1; in setup_vepu540_force_slice_split()
1227 regs->reg087.sli_splt_cpst = 0; in setup_vepu540_force_slice_split()
1228 regs->reg087.sli_max_num_m1 = 500; in setup_vepu540_force_slice_split()
1229 regs->reg087.sli_flsh = 1; in setup_vepu540_force_slice_split()
1230 regs->reg087.sli_splt_cnum_m1 = mb_w - 1; in setup_vepu540_force_slice_split()
1232 regs->reg088.sli_splt_byte = 0; in setup_vepu540_force_slice_split()
1233 regs->reg013.slen_fifo = 0; in setup_vepu540_force_slice_split()
1234 regs->reg023.sli_crs_en = 0; in setup_vepu540_force_slice_split()
1239 static void setup_vepu541_me(Vepu541H264eRegSet *regs, H264eSps *sps, in setup_vepu541_me() argument
1287 regs->reg089.cme_srch_h = cime_blk_w_max / 4; in setup_vepu541_me()
1288 regs->reg089.cme_srch_v = cime_blk_h_max / 4; in setup_vepu541_me()
1289 regs->reg089.rme_srch_h = 7; in setup_vepu541_me()
1290 regs->reg089.rme_srch_v = 5; in setup_vepu541_me()
1291 regs->reg089.dlt_frm_num = 0; in setup_vepu541_me()
1294 regs->reg090.pmv_mdst_h = 0; in setup_vepu541_me()
1295 regs->reg090.pmv_mdst_v = 0; in setup_vepu541_me()
1297 regs->reg090.pmv_mdst_h = 5; in setup_vepu541_me()
1298 regs->reg090.pmv_mdst_v = 5; in setup_vepu541_me()
1300 regs->reg090.mv_limit = 2; in setup_vepu541_me()
1301 regs->reg090.pmv_num = 2; in setup_vepu541_me()
1309 RK_U32 pic_temp = ((regs->reg012.pic_wd8_m1 + 1) * 8 + 63) / 64 * 64; in setup_vepu541_me()
1312 regs->reg091.cme_linebuf_w = cime_linebuf_w; in setup_vepu541_me()
1321 regs->reg091.cme_rama_h = h_temp; in setup_vepu541_me()
1323 RK_S32 swin_scope_wd16 = (regs->reg089.cme_srch_h + 3) / 4 * 2 + 1; in setup_vepu541_me()
1325 temp0 = 2 * regs->reg089.cme_srch_v + 1; in setup_vepu541_me()
1326 if (temp0 > regs->reg091.cme_rama_h) in setup_vepu541_me()
1327 temp0 = regs->reg091.cme_rama_h; in setup_vepu541_me()
1334 regs->reg091.cme_rama_max = pic_wd64 * (temp0 - 1) + temp1; in setup_vepu541_me()
1337 regs->reg091.cme_rama_h = 8; in setup_vepu541_me()
1339 regs->reg091.cme_rama_h = 9; in setup_vepu541_me()
1341 regs->reg091.cme_rama_h = 10; in setup_vepu541_me()
1343 regs->reg091.cme_rama_h = 11; in setup_vepu541_me()
1345 regs->reg091.cme_rama_h = 12; in setup_vepu541_me()
1347 regs->reg091.cme_rama_h = 13; in setup_vepu541_me()
1349 regs->reg091.cme_rama_h = 14; in setup_vepu541_me()
1351 regs->reg091.cme_rama_h = 15; in setup_vepu541_me()
1353 regs->reg091.cme_rama_h = 16; in setup_vepu541_me()
1355 regs->reg091.cme_rama_h = 17; in setup_vepu541_me()
1359 RK_S32 swin_all_4_ver = 2 * regs->reg089.cme_srch_v + 1; in setup_vepu541_me()
1360 RK_S32 swin_all_16_hor = (regs->reg089.cme_srch_h * 4 + 15) / 16 * 2 + 1; in setup_vepu541_me()
1362 if (swin_all_4_ver < regs->reg091.cme_rama_h) in setup_vepu541_me()
1363 regs->reg091.cme_rama_max = (swin_all_4_ver - 1) * pic_wd64 + swin_all_16_hor; in setup_vepu541_me()
1365 … regs->reg091.cme_rama_max = (regs->reg091.cme_rama_h - 1) * pic_wd64 + swin_all_16_hor; in setup_vepu541_me()
1391 static void setup_vepu541_l2(Vepu541H264eRegL2Set *regs, H264eSlice *slice, MppEncHwCfg *hw, MppEnc… in setup_vepu541_l2() argument
1397 memset(regs, 0, sizeof(*regs)); in setup_vepu541_l2()
1399 regs->iprd_tthdy4[0] = 1; in setup_vepu541_l2()
1400 regs->iprd_tthdy4[1] = 4; in setup_vepu541_l2()
1401 regs->iprd_tthdy4[2] = 9; in setup_vepu541_l2()
1402 regs->iprd_tthdy4[3] = 36; in setup_vepu541_l2()
1404 regs->iprd_tthdc8[0] = 1; in setup_vepu541_l2()
1405 regs->iprd_tthdc8[1] = 4; in setup_vepu541_l2()
1406 regs->iprd_tthdc8[2] = 9; in setup_vepu541_l2()
1407 regs->iprd_tthdc8[3] = 36; in setup_vepu541_l2()
1409 regs->iprd_tthdy8[0] = 1; in setup_vepu541_l2()
1410 regs->iprd_tthdy8[1] = 4; in setup_vepu541_l2()
1411 regs->iprd_tthdy8[2] = 9; in setup_vepu541_l2()
1412 regs->iprd_tthdy8[3] = 36; in setup_vepu541_l2()
1414 regs->iprd_wgty8[0] = 0x30; in setup_vepu541_l2()
1415 regs->iprd_wgty8[1] = 0x3c; in setup_vepu541_l2()
1416 regs->iprd_wgty8[2] = 0x28; in setup_vepu541_l2()
1417 regs->iprd_wgty8[3] = 0x30; in setup_vepu541_l2()
1419 regs->iprd_wgty4[0] = 0x30; in setup_vepu541_l2()
1420 regs->iprd_wgty4[1] = 0x3c; in setup_vepu541_l2()
1421 regs->iprd_wgty4[2] = 0x28; in setup_vepu541_l2()
1422 regs->iprd_wgty4[3] = 0x30; in setup_vepu541_l2()
1424 regs->iprd_wgty16[0] = 0x30; in setup_vepu541_l2()
1425 regs->iprd_wgty16[1] = 0x3c; in setup_vepu541_l2()
1426 regs->iprd_wgty16[2] = 0x28; in setup_vepu541_l2()
1427 regs->iprd_wgty16[3] = 0x30; in setup_vepu541_l2()
1429 regs->iprd_wgtc8[0] = 0x24; in setup_vepu541_l2()
1430 regs->iprd_wgtc8[1] = 0x2a; in setup_vepu541_l2()
1431 regs->iprd_wgtc8[2] = 0x1c; in setup_vepu541_l2()
1432 regs->iprd_wgtc8[3] = 0x20; in setup_vepu541_l2()
1435 regs->iprd_tthd_ul = 0x0; in setup_vepu541_l2()
1436 regs->rme_mvd_penalty.mvd_pnlt_e = 1; in setup_vepu541_l2()
1437 regs->rme_mvd_penalty.mvd_pnlt_coef = 1; in setup_vepu541_l2()
1439 regs->qnt_bias_comb.qnt_bias_i = 683; in setup_vepu541_l2()
1440 regs->atr_thd1_h264.atr_thd2 = 36; in setup_vepu541_l2()
1441 regs->atr_wgt16_h264.atr_lv16_wgt0 = 16; in setup_vepu541_l2()
1442 regs->atr_wgt16_h264.atr_lv16_wgt1 = 16; in setup_vepu541_l2()
1443 regs->atr_wgt16_h264.atr_lv16_wgt2 = 16; in setup_vepu541_l2()
1445 regs->atr_wgt8_h264.atr_lv8_wgt0 = 32; in setup_vepu541_l2()
1446 regs->atr_wgt8_h264.atr_lv8_wgt1 = 32; in setup_vepu541_l2()
1447 regs->atr_wgt8_h264.atr_lv8_wgt2 = 32; in setup_vepu541_l2()
1449 regs->atr_wgt4_h264.atr_lv4_wgt0 = 20; in setup_vepu541_l2()
1450 regs->atr_wgt4_h264.atr_lv4_wgt1 = 18; in setup_vepu541_l2()
1451 regs->atr_wgt4_h264.atr_lv4_wgt2 = 16; in setup_vepu541_l2()
1453 regs->qnt_bias_comb.qnt_bias_i = 583; in setup_vepu541_l2()
1454 regs->atr_thd1_h264.atr_thd2 = 81; in setup_vepu541_l2()
1455 regs->atr_wgt16_h264.atr_lv16_wgt0 = 28; in setup_vepu541_l2()
1456 regs->atr_wgt16_h264.atr_lv16_wgt1 = 27; in setup_vepu541_l2()
1457 regs->atr_wgt16_h264.atr_lv16_wgt2 = 23; in setup_vepu541_l2()
1459 regs->atr_wgt8_h264.atr_lv8_wgt0 = 32; in setup_vepu541_l2()
1460 regs->atr_wgt8_h264.atr_lv8_wgt1 = 32; in setup_vepu541_l2()
1461 regs->atr_wgt8_h264.atr_lv8_wgt2 = 32; in setup_vepu541_l2()
1463 regs->atr_wgt4_h264.atr_lv4_wgt0 = 28; in setup_vepu541_l2()
1464 regs->atr_wgt4_h264.atr_lv4_wgt1 = 27; in setup_vepu541_l2()
1465 regs->atr_wgt4_h264.atr_lv4_wgt2 = 23; in setup_vepu541_l2()
1468 regs->iprd_tthd_ul = 0x9c5; in setup_vepu541_l2()
1469 regs->rme_mvd_penalty.mvd_pnlt_e = 0; in setup_vepu541_l2()
1470 regs->rme_mvd_penalty.mvd_pnlt_coef = 0; in setup_vepu541_l2()
1472 regs->qnt_bias_comb.qnt_bias_i = 683; in setup_vepu541_l2()
1473 regs->atr_thd1_h264.atr_thd2 = 36; in setup_vepu541_l2()
1474 regs->atr_wgt16_h264.atr_lv16_wgt0 = 16; in setup_vepu541_l2()
1475 regs->atr_wgt16_h264.atr_lv16_wgt1 = 16; in setup_vepu541_l2()
1476 regs->atr_wgt16_h264.atr_lv16_wgt2 = 16; in setup_vepu541_l2()
1478 regs->atr_wgt8_h264.atr_lv8_wgt0 = 20; in setup_vepu541_l2()
1479 regs->atr_wgt8_h264.atr_lv8_wgt1 = 20; in setup_vepu541_l2()
1480 regs->atr_wgt8_h264.atr_lv8_wgt2 = 20; in setup_vepu541_l2()
1482 regs->atr_wgt4_h264.atr_lv4_wgt0 = 20; in setup_vepu541_l2()
1483 regs->atr_wgt4_h264.atr_lv4_wgt1 = 18; in setup_vepu541_l2()
1484 regs->atr_wgt4_h264.atr_lv4_wgt2 = 16; in setup_vepu541_l2()
1486 regs->qnt_bias_comb.qnt_bias_i = 583; in setup_vepu541_l2()
1487 regs->atr_thd1_h264.atr_thd2 = 81; in setup_vepu541_l2()
1488 regs->atr_wgt16_h264.atr_lv16_wgt0 = 18; in setup_vepu541_l2()
1489 regs->atr_wgt16_h264.atr_lv16_wgt1 = 17; in setup_vepu541_l2()
1490 regs->atr_wgt16_h264.atr_lv16_wgt2 = 16; in setup_vepu541_l2()
1492 regs->atr_wgt8_h264.atr_lv8_wgt0 = 20; in setup_vepu541_l2()
1493 regs->atr_wgt8_h264.atr_lv8_wgt1 = 20; in setup_vepu541_l2()
1494 regs->atr_wgt8_h264.atr_lv8_wgt2 = 20; in setup_vepu541_l2()
1496 regs->atr_wgt4_h264.atr_lv4_wgt0 = 18; in setup_vepu541_l2()
1497 regs->atr_wgt4_h264.atr_lv4_wgt1 = 17; in setup_vepu541_l2()
1498 regs->atr_wgt4_h264.atr_lv4_wgt2 = 16; in setup_vepu541_l2()
1503 regs->qnt_bias_comb.qnt_bias_p = 171; in setup_vepu541_l2()
1505 regs->qnt_bias_comb.qnt_bias_i = hw->qbias_i; in setup_vepu541_l2()
1506 regs->qnt_bias_comb.qnt_bias_p = hw->qbias_p; in setup_vepu541_l2()
1509 regs->atr_thd0_h264.atr_thd0 = 1; in setup_vepu541_l2()
1510 regs->atr_thd0_h264.atr_thd1 = 4; in setup_vepu541_l2()
1511 regs->atr_thd1_h264.atr_qp = 45; in setup_vepu541_l2()
1512 regs->atf_tthd[0] = 0; in setup_vepu541_l2()
1513 regs->atf_tthd[1] = 64; in setup_vepu541_l2()
1514 regs->atf_tthd[2] = 144; in setup_vepu541_l2()
1515 regs->atf_tthd[3] = 2500; in setup_vepu541_l2()
1517 regs->atf_sthd0_h264.atf_sthd_10 = 80; in setup_vepu541_l2()
1518 regs->atf_sthd0_h264.atf_sthd_max = 280; in setup_vepu541_l2()
1520 regs->atf_sthd1_h264.atf_sthd_11 = 144; in setup_vepu541_l2()
1521 regs->atf_sthd1_h264.atf_sthd_20 = 192; in setup_vepu541_l2()
1523 regs->atf_wgt0_h264.atf_wgt10 = 26; in setup_vepu541_l2()
1524 regs->atf_wgt0_h264.atf_wgt11 = 24; in setup_vepu541_l2()
1526 regs->atf_wgt1_h264.atf_wgt12 = 19; in setup_vepu541_l2()
1527 regs->atf_wgt1_h264.atf_wgt20 = 22; in setup_vepu541_l2()
1529 regs->atf_wgt2_h264.atf_wgt21 = 19; in setup_vepu541_l2()
1530 regs->atf_wgt2_h264.atf_wgt30 = 19; in setup_vepu541_l2()
1532 regs->atf_ofst0_h264.atf_ofst10 = 3500; in setup_vepu541_l2()
1533 regs->atf_ofst0_h264.atf_ofst11 = 3500; in setup_vepu541_l2()
1535 regs->atf_ofst1_h264.atf_ofst12 = 0; in setup_vepu541_l2()
1536 regs->atf_ofst1_h264.atf_ofst20 = 3500; in setup_vepu541_l2()
1538 regs->atf_ofst2_h264.atf_ofst21 = 1000; in setup_vepu541_l2()
1539 regs->atf_ofst2_h264.atf_ofst30 = 0; in setup_vepu541_l2()
1541 regs->iprd_wgt_qp[0] = 0; in setup_vepu541_l2()
1543 regs->iprd_wgt_qp[51] = 0; in setup_vepu541_l2()
1545 memcpy(regs->wgt_qp_grpa, &h264e_lambda_default[6], H264E_LAMBDA_TAB_SIZE); in setup_vepu541_l2()
1546 memcpy(regs->wgt_qp_grpb, &h264e_lambda_default[5], H264E_LAMBDA_TAB_SIZE); in setup_vepu541_l2()
1548 regs->madi_mode = 0; in setup_vepu541_l2()
1550 memcpy(regs->aq_tthd, h264_aq_tthd_default, sizeof(regs->aq_tthd)); in setup_vepu541_l2()
1553 for (i = 0; i < MPP_ARRAY_ELEMS(regs->aq_step); i++) { in setup_vepu541_l2()
1554 regs->aq_tthd[i] = hw->aq_thrd_i[i]; in setup_vepu541_l2()
1555 regs->aq_step[i] = hw->aq_step_i[i] & 0x3f; in setup_vepu541_l2()
1558 for (i = 0; i < MPP_ARRAY_ELEMS(regs->aq_step); i++) { in setup_vepu541_l2()
1559 regs->aq_tthd[i] = hw->aq_thrd_p[i]; in setup_vepu541_l2()
1560 regs->aq_step[i] = hw->aq_step_p[i] & 0x3f; in setup_vepu541_l2()
1564 regs->rme_mvd_penalty.mvd_pnlt_cnst = 16000; in setup_vepu541_l2()
1565 regs->rme_mvd_penalty.mvd_pnlt_lthd = 0; in setup_vepu541_l2()
1566 regs->rme_mvd_penalty.mvd_pnlt_hthd = 0; in setup_vepu541_l2()
1568 regs->atr1_thd0_h264.atr1_thd0 = 1; in setup_vepu541_l2()
1569 regs->atr1_thd0_h264.atr1_thd1 = 4; in setup_vepu541_l2()
1570 regs->atr1_thd1_h264.atr1_thd2 = 49; in setup_vepu541_l2()
1576 RK_U32 *p = (RK_U32 *)regs; in setup_vepu541_l2()
1578 for (i = 0; i < (sizeof(*regs) / sizeof(RK_U32)); i++) in setup_vepu541_l2()
1590 Vepu541H264eRegSet *regs = &ctx->regs_set; in hal_h264e_vepu541_gen_regs() local
1603 memset(regs, 0, sizeof(*regs)); in hal_h264e_vepu541_gen_regs()
1605 setup_vepu541_normal(regs, ctx->is_vepu540); in hal_h264e_vepu541_gen_regs()
1606 ret = setup_vepu541_prep(regs, ctx, task); in hal_h264e_vepu541_gen_regs()
1610 setup_vepu541_codec(regs, sps, pps, slice); in hal_h264e_vepu541_gen_regs()
1611 setup_vepu541_rdo_pred(regs, sps, pps, slice, cfg); in hal_h264e_vepu541_gen_regs()
1612 setup_vepu541_rc_base(regs, sps, slice, &cfg->hw, task->rc_task); in hal_h264e_vepu541_gen_regs()
1613 setup_vepu541_io_buf(regs, ctx->dev, task); in hal_h264e_vepu541_gen_regs()
1614 setup_vepu541_roi(regs, ctx); in hal_h264e_vepu541_gen_regs()
1615 setup_vepu541_recn_refr(regs, ctx->dev, ctx->frms, ctx->hw_recn, in hal_h264e_vepu541_gen_regs()
1618 regs->reg082.meiw_addr = task->md_info ? mpp_buffer_get_fd(task->md_info) : 0; in hal_h264e_vepu541_gen_regs()
1620 regs->reg068.pic_ofst_y = mpp_frame_get_offset_y(task->frame); in hal_h264e_vepu541_gen_regs()
1621 regs->reg068.pic_ofst_x = mpp_frame_get_offset_x(task->frame); in hal_h264e_vepu541_gen_regs()
1623 setup_vepu541_split(regs, &cfg->split); in hal_h264e_vepu541_gen_regs()
1625 setup_vepu540_force_slice_split(regs, prep->width); in hal_h264e_vepu541_gen_regs()
1627 setup_vepu541_me(regs, sps, slice, ctx->is_vepu540); in hal_h264e_vepu541_gen_regs()
1630 setup_vepu541_intra_refresh(regs, ctx, frm_status->seq_idx % cfg->rc.gop); in hal_h264e_vepu541_gen_regs()
1643 RK_U32 *p = (RK_U32 *)regs; in hal_h264e_vepu541_gen_regs()