1 /*
2 * Copyright 2017 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_vp8e_vepu2_v2"
18
19 #include <string.h>
20
21 #include "mpp_mem.h"
22 #include "mpp_common.h"
23 #include "mpp_enc_hal.h"
24 #include "hal_vp8e_base.h"
25 #include "hal_vp8e_vepu2_v2.h"
26 #include "hal_vp8e_vepu2_reg.h"
27
28 #include "mpp_rc.h"
29 #include "vp8e_syntax.h"
30 #include "hal_vp8e_debug.h"
31
32 #define SWREG_AMOUNT_VEPU2 (184)
33 #define HW_STATUS_MASK 0x250
34 #define HW_STATUS_BUFFER_FULL 0x20
35 #define HW_STATUS_FRAME_READY 0x02
36
vp8e_vpu_frame_start(void * hal)37 static MPP_RET vp8e_vpu_frame_start(void *hal)
38 {
39 RK_S32 i;
40 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
41 Vp8eHwCfg *hw_cfg = &ctx->hw_cfg;
42 Vp8eVepu2Reg_t *regs = (Vp8eVepu2Reg_t *)ctx->regs;
43
44 memset(regs, 0, sizeof(Vp8eVepu2Reg_t));
45
46 regs->sw109.val = hw_cfg->irq_disable ? (regs->sw109.val | 0x0100) :
47 (regs->sw109.val & 0xfeff);
48
49 //((0 & (255)) << 24) | ((0 & (255)) << 16) | ((16 & (63)) << 8) | ((0 & (1)) << 2) | ((0 & (1)) << 1);
50 regs->sw54.val = 0x1000;
51
52 if (hw_cfg->input_format < INPUT_RGB565) {
53 regs->sw105.val = 0xfc000000;
54 } else if (hw_cfg->input_format < INPUT_RGB888) {
55 regs->sw105.val = 0xfc000000;
56 } else {
57 regs->sw105.val = 0x3c000000;
58 }
59
60 regs->sw77.base_stream = hw_cfg->output_strm_base;
61 mpp_dev_set_reg_offset(ctx->dev, 77, hw_cfg->output_strm_offset);
62 regs->sw78.base_control = hw_cfg->size_tbl_base;
63 regs->sw74.nal_size_write = hw_cfg->size_tbl_base != 0;
64 regs->sw109.mv_write = hw_cfg->mv_output_base != 0;
65
66 regs->sw56.base_ref_lum = hw_cfg->internal_img_lum_base_r[0];
67 regs->sw57.base_ref_chr = hw_cfg->internal_img_chr_base_r[0];
68 regs->sw63.base_rec_lum = hw_cfg->internal_img_lum_base_w;
69 regs->sw64.base_rec_chr = hw_cfg->internal_img_chr_base_w;
70
71 regs->sw48.base_in_lum = hw_cfg->input_lum_base;
72 if (hw_cfg->input_lum_offset)
73 mpp_dev_set_reg_offset(ctx->dev, 48, hw_cfg->input_lum_offset);
74
75 regs->sw49.base_in_cb = hw_cfg->input_cb_base;
76 if (hw_cfg->input_cb_offset)
77 mpp_dev_set_reg_offset(ctx->dev, 49, hw_cfg->input_cb_offset);
78
79 regs->sw50.base_in_cr = hw_cfg->input_cr_base;
80 if (hw_cfg->input_cr_offset)
81 mpp_dev_set_reg_offset(ctx->dev, 50, hw_cfg->input_cr_offset);
82
83 // regs->sw109.int_timeout = 1 & 1;
84 regs->sw109.val |= 0x0400;
85 regs->sw109.int_slice_ready = hw_cfg->int_slice_ready;
86 regs->sw109.rec_write_disable = hw_cfg->rec_write_disable;
87 regs->sw103.width = hw_cfg->mbs_in_row;
88 regs->sw103.height = hw_cfg->mbs_in_col;
89 regs->sw103.picture_type = hw_cfg->frame_coding_type;
90 regs->sw103.encoding_mode = hw_cfg->coding_type;
91
92 regs->sw61.chr_offset = hw_cfg->input_chroma_base_offset;
93 regs->sw61.lum_offset = hw_cfg->input_luma_base_offset;
94 regs->sw61.row_length = hw_cfg->pixels_on_row;
95 regs->sw60.x_fill = hw_cfg->x_fill;
96 regs->sw60.y_fill = hw_cfg->y_fill;
97 regs->sw74.input_format = hw_cfg->input_format;
98 regs->sw74.input_rot = hw_cfg->input_rotation;
99
100 regs->sw59.cabac_enable = hw_cfg->enable_cabac;
101 regs->sw75.ip_intra_16_favor = hw_cfg->intra_16_favor;
102 regs->sw75.inter_favor = hw_cfg->inter_favor;
103 regs->sw59.disable_qp_mv = hw_cfg->disable_qp_mv;
104 regs->sw59.deblocking = hw_cfg->filter_disable;
105 regs->sw60.skip_penalty = hw_cfg->skip_penalty;
106 regs->sw99.split_mv = hw_cfg->split_mv_mode;
107 regs->sw107.split_penalty_16x8 = hw_cfg->split_penalty[0];
108 regs->sw107.split_penalty_8x8 = hw_cfg->split_penalty[1];
109 regs->sw107.split_penalty_8x4 = hw_cfg->split_penalty[2];
110 regs->sw102.split_penalty_4x4 = hw_cfg->split_penalty[3];
111 regs->sw102.zero_mv_favor = hw_cfg->zero_mv_favor;
112
113 regs->sw51.strm_hdr_rem1 = hw_cfg->strm_start_msb;
114 regs->sw52.strm_hdr_rem2 = hw_cfg->strm_start_lsb;
115 regs->sw53.strm_buf_limit = hw_cfg->output_strm_size;
116
117 regs->sw76.base_ref_lum2 = hw_cfg->internal_img_lum_base_r[1];
118 regs->sw106.base_ref_chr2 = hw_cfg->internal_img_chr_base_r[1];
119
120 regs->sw100.y1_quant_dc = hw_cfg->y1_quant_dc[0];
121 regs->sw65.y1_quant_ac = hw_cfg->y1_quant_ac[0];
122 regs->sw66.y2_quant_dc = hw_cfg->y2_quant_dc[0];
123 regs->sw67.y2_quant_ac = hw_cfg->y2_quant_ac[0];
124 regs->sw68.ch_quant_dc = hw_cfg->ch_quant_dc[0];
125 regs->sw69.ch_quant_ac = hw_cfg->ch_quant_ac[0];
126
127 regs->sw100.y1_zbin_dc = hw_cfg->y1_zbin_dc[0];
128 regs->sw65.y1_zbin_ac = hw_cfg->y1_zbin_ac[0];
129 regs->sw66.y2_zbin_dc = hw_cfg->y2_zbin_dc[0];
130 regs->sw67.y2_zbin_ac = hw_cfg->y2_zbin_ac[0];
131 regs->sw68.ch_zbin_dc = hw_cfg->ch_zbin_dc[0];
132 regs->sw69.ch_zbin_ac = hw_cfg->ch_zbin_ac[0];
133
134 regs->sw100.y1_round_dc = hw_cfg->y1_round_dc[0];
135 regs->sw65.y1_round_ac = hw_cfg->y1_round_ac[0];
136 regs->sw66.y2_round_dc = hw_cfg->y2_round_dc[0];
137 regs->sw67.y2_round_ac = hw_cfg->y2_round_ac[0];
138 regs->sw68.ch_round_dc = hw_cfg->ch_round_dc[0];
139 regs->sw69.ch_round_ac = hw_cfg->ch_round_ac[0];
140
141 regs->sw70.y1_dequant_dc = hw_cfg->y1_dequant_dc[0];
142 regs->sw70.y1_dequant_ac = hw_cfg->y1_dequant_ac[0];
143 regs->sw70.y2_dequant_dc = hw_cfg->y2_dequant_dc[0];
144 regs->sw71.y2_dequant_ac = hw_cfg->y2_dequant_ac[0];
145 regs->sw71.ch_dequant_dc = hw_cfg->ch_dequant_dc[0];
146 regs->sw71.ch_dequant_ac = hw_cfg->ch_dequant_ac[0];
147
148 regs->sw70.mv_ref_idx = hw_cfg->mv_ref_idx[0];
149 regs->sw71.mv_ref_idx2 = hw_cfg->mv_ref_idx[1];
150 regs->sw71.ref2_enable = hw_cfg->ref2_enable;
151
152 regs->sw72.bool_enc_value = hw_cfg->bool_enc_value;
153 regs->sw73.bool_enc_value_bits = hw_cfg->bool_enc_value_bits;
154 regs->sw73.bool_enc_range = hw_cfg->bool_enc_range;
155
156 regs->sw73.filter_level = hw_cfg->filter_level[0];
157 regs->sw73.golden_penalty = hw_cfg->golden_penalty;
158 regs->sw73.filter_sharpness = hw_cfg->filter_sharpness;
159 regs->sw73.dct_partition_count = hw_cfg->dct_partitions;
160
161 regs->sw60.start_offset = hw_cfg->first_free_bit;
162
163 regs->sw79.base_next_lum = hw_cfg->vs_next_luma_base;
164 regs->sw94.stab_mode = hw_cfg->vs_mode;
165
166 regs->sw99.dmv_penalty_4p = hw_cfg->diff_mv_penalty[0];
167 regs->sw99.dmv_penalty_1p = hw_cfg->diff_mv_penalty[1];
168 regs->sw99.dmv_penalty_qp = hw_cfg->diff_mv_penalty[2];
169
170 regs->sw81.base_cabac_ctx = hw_cfg->cabac_tbl_base;
171 regs->sw80.base_mv_write = hw_cfg->mv_output_base;
172
173 regs->sw95.rgb_coeff_a = hw_cfg->rgb_coeff_a;
174 regs->sw95.rgb_coeff_b = hw_cfg->rgb_coeff_b;
175 regs->sw96.rgb_coeff_c = hw_cfg->rgb_coeff_c;
176 regs->sw96.rgb_coeff_e = hw_cfg->rgb_coeff_e;
177 regs->sw97.rgb_coeff_f = hw_cfg->rgb_coeff_f;
178
179 regs->sw98.r_mask_msb = hw_cfg->r_mask_msb;
180 regs->sw98.g_mask_msb = hw_cfg->g_mask_msb;
181 regs->sw98.b_mask_msb = hw_cfg->b_mask_msb;
182
183 regs->sw47.cir_start = hw_cfg->cir_start;
184 regs->sw47.cir_interval = hw_cfg->cir_interval;
185
186 regs->sw46.intra_area_left = hw_cfg->intra_area_left;
187 regs->sw46.intra_area_right = hw_cfg->intra_area_right;
188 regs->sw46.intra_area_top = hw_cfg->intra_area_top;
189 regs->sw46.intra_area_bottom = hw_cfg->intra_area_bottom ;
190 regs->sw82.roi1_left = hw_cfg->roi1_left;
191 regs->sw82.roi1_right = hw_cfg->roi1_right;
192 regs->sw82.roi1_top = hw_cfg->roi1_top;
193 regs->sw82.roi1_bottom = hw_cfg->roi1_bottom;
194
195 regs->sw83.roi2_left = hw_cfg->roi2_left;
196 regs->sw83.roi2_right = hw_cfg->roi2_right;
197 regs->sw83.roi2_top = hw_cfg->roi2_top;
198 regs->sw83.roi2_bottom = hw_cfg->roi2_bottom;
199
200 regs->sw44.base_partition1 = hw_cfg->partition_Base[0];
201 mpp_dev_set_reg_offset(ctx->dev, 44, hw_cfg->partition_offset[0]);
202 regs->sw45.base_partition2 = hw_cfg->partition_Base[1];
203 mpp_dev_set_reg_offset(ctx->dev, 45, hw_cfg->partition_offset[1]);
204 regs->sw108.base_prob_count = hw_cfg->prob_count_base;
205
206 regs->sw33.mode0_penalty = hw_cfg->intra_mode_penalty[0];
207 regs->sw33.mode1_penalty = hw_cfg->intra_mode_penalty[1];
208 regs->sw34.mode2_penalty = hw_cfg->intra_mode_penalty[2];
209 regs->sw34.mode3_penalty = hw_cfg->intra_mode_penalty[3];
210
211 for (i = 0 ; i < 5; i++) {
212 regs->sw28_32[i].b_mode_0_penalty = hw_cfg->intra_b_mode_penalty[2 * i];
213 regs->sw28_32[i].b_mode_1_penalty = hw_cfg->intra_b_mode_penalty[2 * i + 1];
214 }
215
216 regs->sw71.segment_enable = hw_cfg->segment_enable;
217 regs->sw71.segment_map_update = hw_cfg->segment_map_update;
218 regs->sw27.base_segment_map = hw_cfg->segment_map_base;
219
220 for (i = 0; i < 3; i++) {
221 regs->sw0_26[0 + i * 9].num_0.y1_quant_dc = hw_cfg->y1_quant_dc[1 + i];
222 regs->sw0_26[0 + i * 9].num_0.y2_quant_dc = hw_cfg->y2_quant_dc[1 + i];
223
224 regs->sw0_26[1 + i * 9].num_1.ch_quant_dc = hw_cfg->ch_quant_dc[1 + i];
225 regs->sw0_26[1 + i * 9].num_1.y1_quant_ac = hw_cfg->y1_quant_ac[1 + i];
226
227 regs->sw0_26[2 + i * 9].num_2.y2_quant_ac = hw_cfg->y2_quant_ac[1 + i];
228 regs->sw0_26[2 + i * 9].num_2.ch_quant_ac = hw_cfg->ch_quant_ac[1 + i];
229
230 regs->sw0_26[3 + i * 9].num_3.y1_zbin_dc = hw_cfg->y1_zbin_dc[1 + i];
231 regs->sw0_26[3 + i * 9].num_3.y2_zbin_dc = hw_cfg->y2_zbin_dc[1 + i];
232 regs->sw0_26[3 + i * 9].num_3.ch_zbin_dc = hw_cfg->ch_zbin_dc[1 + i];
233
234 regs->sw0_26[4 + i * 9].num_4.y1_zbin_ac = hw_cfg->y1_zbin_ac[1 + i];
235 regs->sw0_26[4 + i * 9].num_4.y2_zbin_ac = hw_cfg->y2_zbin_ac[1 + i];
236 regs->sw0_26[4 + i * 9].num_4.ch_zbin_ac = hw_cfg->ch_zbin_ac[1 + i];
237
238 regs->sw0_26[5 + i * 9].num_5.y1_round_dc = hw_cfg->y1_round_dc[1 + i];
239 regs->sw0_26[5 + i * 9].num_5.y2_round_dc = hw_cfg->y2_round_dc[1 + i];
240 regs->sw0_26[5 + i * 9].num_5.ch_round_dc = hw_cfg->ch_round_dc[1 + i];
241
242 regs->sw0_26[6 + i * 9].num_6.y1_round_ac = hw_cfg->y1_round_ac[1 + i];
243 regs->sw0_26[6 + i * 9].num_6.y2_round_ac = hw_cfg->y2_round_ac[1 + i];
244 regs->sw0_26[6 + i * 9].num_6.ch_round_ac = hw_cfg->ch_round_ac[1 + i];
245
246 regs->sw0_26[7 + i * 9].num_7.y1_dequant_dc = hw_cfg->y1_dequant_dc[1 + i];
247 regs->sw0_26[7 + i * 9].num_7.y2_dequant_dc = hw_cfg->y2_dequant_dc[1 + i];
248 regs->sw0_26[7 + i * 9].num_7.ch_dequant_dc = hw_cfg->ch_dequant_dc[1 + i];
249 regs->sw0_26[7 + i * 9].num_7.filter_level = hw_cfg->filter_level[1 + i];
250
251 regs->sw0_26[8 + i * 9].num_8.y1_dequant_ac = hw_cfg->y1_dequant_ac[1 + i];
252 regs->sw0_26[8 + i * 9].num_8.y2_dequant_ac = hw_cfg->y2_dequant_ac[1 + i];
253 regs->sw0_26[8 + i * 9].num_8.ch_dequant_ac = hw_cfg->ch_dequant_ac[1 + i];
254 }
255
256 regs->sw40.lf_ref_delta0 = hw_cfg->lf_ref_delta[0] & mask_7b;
257 regs->sw42.lf_ref_delta1 = hw_cfg->lf_ref_delta[1] & mask_7b;
258 regs->sw42.lf_ref_delta2 = hw_cfg->lf_ref_delta[2] & mask_7b;
259 regs->sw42.lf_ref_delta3 = hw_cfg->lf_ref_delta[3] & mask_7b;
260 regs->sw40.lf_mode_delta0 = hw_cfg->lf_mode_delta[0] & mask_7b;
261 regs->sw43.lf_mode_delta1 = hw_cfg->lf_mode_delta[1] & mask_7b;
262 regs->sw43.lf_mode_delta2 = hw_cfg->lf_mode_delta[2] & mask_7b;
263 regs->sw43.lf_mode_delta3 = hw_cfg->lf_mode_delta[3] & mask_7b;
264
265 RK_S32 j = 0;
266 for (j = 0; j < 32; j++) {
267 regs->sw120_183[j].penalty_0 = hw_cfg->dmv_penalty[j * 4 + 3];
268 regs->sw120_183[j].penalty_1 = hw_cfg->dmv_penalty[j * 4 + 2];
269 regs->sw120_183[j].penalty_2 = hw_cfg->dmv_penalty[j * 4 + 1];
270 regs->sw120_183[j].penalty_3 = hw_cfg->dmv_penalty[j * 4];
271
272 regs->sw120_183[j + 32].penalty_0 = hw_cfg->dmv_qpel_penalty[j * 4 + 3];
273 regs->sw120_183[j + 32].penalty_1 = hw_cfg->dmv_qpel_penalty[j * 4 + 2];
274 regs->sw120_183[j + 32].penalty_2 = hw_cfg->dmv_qpel_penalty[j * 4 + 1];
275 regs->sw120_183[j + 32].penalty_3 = hw_cfg->dmv_qpel_penalty[j * 4];
276 }
277
278 regs->sw103.enable = 0x1;
279
280 return MPP_OK;
281 }
282
hal_vp8e_vepu2_init_v2(void * hal,MppEncHalCfg * cfg)283 static MPP_RET hal_vp8e_vepu2_init_v2(void *hal, MppEncHalCfg *cfg)
284 {
285 MPP_RET ret = MPP_OK;
286 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
287 Vp8eHwCfg *hw_cfg = &ctx->hw_cfg;
288
289 ctx->cfg = cfg->cfg;
290
291 /* update output to MppEnc */
292 cfg->type = VPU_CLIENT_VEPU2;
293 ret = mpp_dev_init(&cfg->dev, cfg->type);
294 if (ret) {
295 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
296 return ret;
297 }
298 ctx->dev = cfg->dev;
299
300 vp8e_hal_dbg(VP8E_DBG_HAL_FUNCTION, "mpp_dev_init success.\n");
301
302 ctx->buffers = mpp_calloc(Vp8eVpuBuf, 1);
303 if (ctx->buffers == NULL) {
304 mpp_err("failed to malloc buffers");
305 return MPP_ERR_NOMEM;
306 }
307 //memset(ctx->buffers, 0, sizeof(Vp8eVpuBuf));
308
309 ctx->buffer_ready = 0;
310 ctx->frame_cnt = 0;
311 ctx->frame_type = VP8E_FRM_KEY;
312 ctx->prev_frame_lost = 0;
313 ctx->frame_size = 0;
314 ctx->ivf_hdr_rdy = 0;
315 ctx->reg_size = SWREG_AMOUNT_VEPU2;
316
317 hw_cfg->irq_disable = 0;
318
319 hw_cfg->rounding_ctrl = 0;
320 hw_cfg->cp_distance_mbs = 0;
321 hw_cfg->recon_img_id = 0;
322 hw_cfg->input_lum_base = 0;
323 hw_cfg->input_cb_base = 0;
324 hw_cfg->input_cr_base = 0;
325
326 hal_vp8e_init_qp_table(hal);
327
328 return ret;
329 }
330
hal_vp8e_vepu2_deinit_v2(void * hal)331 static MPP_RET hal_vp8e_vepu2_deinit_v2(void *hal)
332 {
333 MPP_RET ret = MPP_OK;
334 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
335
336 hal_vp8e_buf_free(ctx);
337
338 if (ctx->dev) {
339 mpp_dev_deinit(ctx->dev);
340 ctx->dev = NULL;
341 }
342
343 MPP_FREE(ctx->regs);
344 MPP_FREE(ctx->buffers);
345
346 vp8e_hal_dbg(VP8E_DBG_HAL_FUNCTION, "mpp_dev_deinit success.\n");
347
348 return ret;
349 }
350
hal_vp8e_vepu2_gen_regs_v2(void * hal,HalEncTask * task)351 static MPP_RET hal_vp8e_vepu2_gen_regs_v2(void *hal, HalEncTask *task)
352 {
353 MPP_RET ret = MPP_OK;
354 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
355
356 ctx->rc->qp_hdr = MPP_CLIP3(0, 127, task->rc_task->info.quality_target);
357
358 if (!ctx->buffer_ready) {
359 ret = hal_vp8e_setup(hal);
360 if (ret) {
361 mpp_err("failed to init hal vp8e\n");
362 return ret;
363 } else {
364 ctx->buffer_ready = 1;
365 }
366 }
367
368 memset(ctx->stream_size, 0, sizeof(ctx->stream_size));
369
370 hal_vp8e_enc_strm_code(ctx, task);
371 vp8e_vpu_frame_start(ctx);
372
373 return MPP_OK;
374 }
375
hal_vp8e_vepu2_start_v2(void * hal,HalEncTask * task)376 static MPP_RET hal_vp8e_vepu2_start_v2(void *hal, HalEncTask *task)
377 {
378 MPP_RET ret = MPP_OK;
379 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
380
381 if (VP8E_DBG_HAL_DUMP_REG & vp8e_hal_debug) {
382 RK_U32 i = 0;
383 RK_U32 *tmp = (RK_U32 *)ctx->regs;
384
385 for (; i < ctx->reg_size; i++)
386 mpp_log("reg[%d]:%x\n", i, tmp[i]);
387 }
388
389 do {
390 MppDevRegWrCfg wr_cfg;
391 MppDevRegRdCfg rd_cfg;
392 RK_U32 reg_size = ctx->reg_size * sizeof(RK_U32);
393
394 wr_cfg.reg = ctx->regs;
395 wr_cfg.size = reg_size;
396 wr_cfg.offset = 0;
397
398 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
399 if (ret) {
400 mpp_err_f("set register write failed %d\n", ret);
401 break;
402 }
403
404 rd_cfg.reg = ctx->regs;
405 rd_cfg.size = reg_size;
406 rd_cfg.offset = 0;
407
408 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
409 if (ret) {
410 mpp_err_f("set register read failed %d\n", ret);
411 break;
412 }
413
414 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
415 if (ret) {
416 mpp_err_f("send cmd failed %d\n", ret);
417 break;
418 }
419 } while (0);
420
421 (void)task;
422 return ret;
423 }
424
vp8e_update_hw_cfg(void * hal)425 static void vp8e_update_hw_cfg(void *hal)
426 {
427 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
428 Vp8eHwCfg *hw_cfg = &ctx->hw_cfg;
429 Vp8eVepu2Reg_t *regs = (Vp8eVepu2Reg_t *) ctx->regs;
430
431 hw_cfg->output_strm_base = regs->sw53.strm_buf_limit / 8;
432 hw_cfg->qp_sum = regs->sw58.qp_sum * 2;
433 hw_cfg->mad_count = regs->sw104.mad_count;
434 hw_cfg->rlc_count = regs->sw62.rlc_sum * 3;
435
436 hw_cfg->intra_16_favor = -1;
437 hw_cfg->inter_favor = -1;
438 hw_cfg->diff_mv_penalty[0] = -1;
439 hw_cfg->diff_mv_penalty[1] = -1;
440 hw_cfg->diff_mv_penalty[2] = -1;
441 hw_cfg->skip_penalty = -1;
442 hw_cfg->golden_penalty = -1;
443 hw_cfg->split_penalty[0] = 0;
444 hw_cfg->split_penalty[1] = 0;
445 hw_cfg->split_penalty[3] = 0;
446 }
447
hal_vp8e_vepu2_wait_v2(void * hal,HalEncTask * task)448 static MPP_RET hal_vp8e_vepu2_wait_v2(void *hal, HalEncTask *task)
449 {
450 MPP_RET ret = MPP_OK;
451 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
452
453 Vp8eFeedback *fb = &ctx->feedback;
454 Vp8eVepu2Reg_t *regs = (Vp8eVepu2Reg_t *) ctx->regs;
455 RK_S32 sw_length = task->length;
456
457 if (NULL == ctx->dev) {
458 mpp_err_f("invalid dev ctx\n");
459 return MPP_NOK;
460 }
461
462 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
463 if (ret)
464 mpp_err_f("poll cmd failed %d\n", ret);
465
466 fb->hw_status = regs->sw109.val & HW_STATUS_MASK;
467 if (regs->sw109.val & HW_STATUS_FRAME_READY)
468 vp8e_update_hw_cfg(ctx);
469 else if (regs->sw109.val & HW_STATUS_BUFFER_FULL)
470 ctx->bitbuf[1].size = 0;
471
472 hal_vp8e_update_buffers(ctx, task);
473
474 ctx->last_frm_intra = task->rc_task->frm.is_intra;
475 ctx->frame_cnt++;
476
477 task->rc_task->info.bit_real = ctx->frame_size << 3;
478 task->hw_length = task->length - sw_length;
479 return ret;
480 }
481
hal_vp8e_vepu2_get_task_v2(void * hal,HalEncTask * task)482 static MPP_RET hal_vp8e_vepu2_get_task_v2(void *hal, HalEncTask *task)
483 {
484 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
485 Vp8eSyntax* syntax = (Vp8eSyntax*)task->syntax.data;
486 //ctx->cfg = syntax->cfg;
487 RK_U32 i;
488
489 for (i = 0; i < task->syntax.number; i++) {
490 if (syntax[i].type == VP8E_SYN_CFG) {
491 ctx->cfg = (MppEncCfgSet*)syntax[i].data;
492 }
493 if (syntax[i].type == VP8E_SYN_RC) {
494 ctx->rc = (Vp8eRc*) syntax[i].data;
495 }
496 }
497
498 ctx->frame_type = task->rc_task->frm.is_intra ? VP8E_FRM_KEY : VP8E_FRM_P;
499
500 if (!ctx->cfg->vp8.disable_ivf && !ctx->ivf_hdr_rdy) {
501 RK_U8 *p_out = mpp_buffer_get_ptr(task->output);
502
503 write_ivf_header(hal, p_out);
504 task->length += IVF_HDR_BYTES;
505
506 ctx->ivf_hdr_rdy = 1;
507 }
508
509 return MPP_OK;
510 }
511
hal_vp8e_vepu2_ret_task_v2(void * hal,HalEncTask * task)512 static MPP_RET hal_vp8e_vepu2_ret_task_v2(void *hal, HalEncTask *task)
513 {
514 (void)hal;
515 (void)task;
516 return MPP_OK;
517 }
518
519 const MppEncHalApi hal_vp8e_vepu2 = {
520 .name = "hal_vp8e_vepu2",
521 .coding = MPP_VIDEO_CodingVP8,
522 .ctx_size = sizeof(HalVp8eCtx),
523 .flag = 0,
524 .init = hal_vp8e_vepu2_init_v2,
525 .deinit = hal_vp8e_vepu2_deinit_v2,
526 .prepare = NULL,
527 .get_task = hal_vp8e_vepu2_get_task_v2,
528 .gen_regs = hal_vp8e_vepu2_gen_regs_v2,
529 .start = hal_vp8e_vepu2_start_v2,
530 .wait = hal_vp8e_vepu2_wait_v2,
531 .part_start = NULL,
532 .part_wait = NULL,
533 .ret_task = hal_vp8e_vepu2_ret_task_v2,
534 };
535