1 /*
2 * Copyright 2015 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_vp8d_vdpu1"
18
19 #include <string.h>
20
21 #include "mpp_env.h"
22 #include "mpp_mem.h"
23 #include "mpp_debug.h"
24
25 #include "hal_vp8d_vdpu1.h"
26 #include "hal_vp8d_vdpu1_reg.h"
27
28 #define CLIP3(l, h, v) ((v) < (l) ? (l) : ((v) > (h) ? (h) : (v)))
29
30 static const RK_U32 mcFilter[8][6] = {
31 { 0, 0, 128, 0, 0, 0 },
32 { 0, -6, 123, 12, -1, 0 },
33 { 2, -11, 108, 36, -8, 1 },
34 { 0, -9, 93, 50, -6, 0 },
35 { 3, -16, 77, 77, -16, 3 },
36 { 0, -6, 50, 93, -9, 0 },
37 { 1, -8, 36, 108, -11, 2 },
38 { 0, -1, 12, 123, -6, 0 }
39 };
40
hal_vp8d_vdpu1_init(void * hal,MppHalCfg * cfg)41 MPP_RET hal_vp8d_vdpu1_init(void *hal, MppHalCfg *cfg)
42 {
43 MPP_RET ret = MPP_OK;
44 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
45
46 FUN_T("enter\n");
47
48 ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU1);
49 if (ret) {
50 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
51 goto ERR_RET;
52 }
53 if (NULL == ctx->regs) {
54 ctx->regs = mpp_calloc_size(void, sizeof(VP8DRegSet_t));
55 if (NULL == ctx->regs) {
56 mpp_err("hal_vp8 reg alloc failed\n");
57 ret = MPP_ERR_MALLOC;
58 goto ERR_RET;
59 }
60 }
61
62 if (NULL == ctx->group) {
63 ret = mpp_buffer_group_get_internal(&ctx->group, MPP_BUFFER_TYPE_ION);
64 if (ret) {
65 mpp_err("hal_vp8 mpp_buffer_group_get failed\n");
66 goto ERR_RET;
67 }
68 }
69
70 ret = mpp_buffer_get(ctx->group, &ctx->probe_table, VP8D_PROB_TABLE_SIZE);
71 if (ret) {
72 mpp_err("hal_vp8 probe_table get buffer failed\n");
73 goto ERR_RET;
74 }
75
76 ret = mpp_buffer_get(ctx->group, &ctx->seg_map, VP8D_MAX_SEGMAP_SIZE);
77 if (ret) {
78 mpp_err("hal_vp8 seg_map get buffer failed\n");
79 goto ERR_RET;
80 }
81 //configure
82 ctx->packet_slots = cfg->packet_slots;
83 ctx->frame_slots = cfg->frame_slots;
84 cfg->dev = ctx->dev;
85
86 FUN_T("leave\n");
87 return ret;
88 ERR_RET:
89 if (ctx->dev) {
90 mpp_dev_deinit(ctx->dev);
91 ctx->dev = NULL;
92 }
93
94 if (ctx->regs) {
95 mpp_free(ctx->regs);
96 ctx->regs = NULL;
97 }
98
99 if (ctx->probe_table) {
100 mpp_buffer_put(ctx->probe_table);
101 ctx->probe_table = NULL;
102 }
103
104 if (ctx->seg_map) {
105 mpp_buffer_group_put(ctx->seg_map);
106 ctx->seg_map = NULL;
107 }
108
109 if (ctx->group) {
110 mpp_buffer_put(ctx->group);
111 ctx->group = NULL;
112 }
113 FUN_T("leave\n");
114 return ret;
115 }
116
hal_vp8d_vdpu1_deinit(void * hal)117 MPP_RET hal_vp8d_vdpu1_deinit(void *hal)
118 {
119 MPP_RET ret = MPP_OK;
120 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
121
122 FUN_T("enter\n");
123
124 if (ctx->dev) {
125 mpp_dev_deinit(ctx->dev);
126 ctx->dev = NULL;
127 }
128
129 if (ctx->probe_table) {
130 ret = mpp_buffer_put(ctx->probe_table);
131 if (ret) {
132 mpp_err("hal_vp8 probe table put buffer failed\n");
133 }
134 }
135
136 if (ctx->seg_map) {
137 ret = mpp_buffer_put(ctx->seg_map);
138 if (ret) {
139 mpp_err("hal_vp8 seg map put buffer failed\n");
140 }
141 }
142
143 if (ctx->group) {
144 ret = mpp_buffer_group_put(ctx->group);
145 if (ret) {
146 mpp_err("hal_vp8 group free buffer failed\n");
147 }
148 }
149
150 if (ctx->regs) {
151 mpp_free(ctx->regs);
152 ctx->regs = NULL;
153 }
154
155 FUN_T("leave\n");
156 return ret;
157 }
158
hal_vp8_init_hwcfg(VP8DHalContext_t * ctx)159 static MPP_RET hal_vp8_init_hwcfg(VP8DHalContext_t *ctx)
160 {
161
162 VP8DRegSet_t *reg = (VP8DRegSet_t *)ctx->regs;
163
164 FUN_T("enter\n");
165 memset(reg, 0, sizeof(VP8DRegSet_t));
166
167 reg->reg1_interrupt.sw_dec_e = 1;
168
169 reg->reg2_dec_ctrl.sw_dec_out_tiled_e = 0;
170 reg->reg2_dec_ctrl.sw_dec_scmd_dis = 0;
171 reg->reg2_dec_ctrl.sw_dec_adv_pre_dis = 0;
172 reg->reg2_dec_ctrl.sw_dec_latency = 0;
173
174 reg->reg2_dec_ctrl.sw_dec_in_endian = 1;
175 reg->reg2_dec_ctrl.sw_dec_out_endian = 1;
176 reg->reg2_dec_ctrl.sw_dec_inswap32_e = 1;
177 reg->reg2_dec_ctrl.sw_dec_outswap32_e = 1;
178 reg->reg2_dec_ctrl.sw_dec_strswap32_e = 1;
179 reg->reg2_dec_ctrl.sw_dec_strendian_e = 1;
180 reg->reg2_dec_ctrl.sw_dec_axi_rn_id = 0;
181
182 reg->reg2_dec_ctrl.sw_dec_data_disc_e = 0;
183 reg->reg2_dec_ctrl.sw_dec_max_burst = 16;
184 reg->reg2_dec_ctrl.sw_dec_timeout_e = 1;
185 reg->reg2_dec_ctrl.sw_dec_clk_gate_e = 1;
186
187 reg->reg3.sw_dec_out_dis = 0;
188 reg->reg3.sw_dec_axi_wr_id = 0;
189 reg->reg3.sw_dec_mode = DEC_MODE_VP8;
190
191 reg->reg1_interrupt.sw_dec_irq = 0;
192
193 reg->reg10_segment_map_base = mpp_buffer_get_fd(ctx->seg_map);
194 reg->reg40_qtable_base = mpp_buffer_get_fd(ctx->probe_table);
195
196 FUN_T("leave\n");
197 return MPP_OK;
198 }
199
hal_vp8d_pre_filter_tap_set(VP8DHalContext_t * ctx)200 static MPP_RET hal_vp8d_pre_filter_tap_set(VP8DHalContext_t *ctx)
201 {
202 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
203
204 FUN_T("enter\n");
205 regs->reg49.sw_pred_bc_tap_0_0 = mcFilter[0][1];
206 regs->reg49.sw_pred_bc_tap_0_1 = mcFilter[0][2];
207 regs->reg49.sw_pred_bc_tap_0_2 = mcFilter[0][3];
208 regs->reg34.sw_pred_bc_tap_0_3 = mcFilter[0][4];
209 regs->reg34.sw_pred_bc_tap_1_0 = mcFilter[1][1];
210 regs->reg34.sw_pred_bc_tap_1_1 = mcFilter[1][2];
211 regs->reg35.sw_pred_bc_tap_1_2 = mcFilter[1][3];
212 regs->reg35.sw_pred_bc_tap_1_3 = mcFilter[1][4];
213 regs->reg35.sw_pred_bc_tap_2_0 = mcFilter[2][1];
214 regs->reg36.sw_pred_bc_tap_2_1 = mcFilter[2][2];
215 regs->reg36.sw_pred_bc_tap_2_2 = mcFilter[2][3];
216 regs->reg36.sw_pred_bc_tap_2_3 = mcFilter[2][4];
217
218 regs->reg37.sw_pred_bc_tap_3_0 = mcFilter[3][1];
219 regs->reg37.sw_pred_bc_tap_3_1 = mcFilter[3][2];
220 regs->reg37.sw_pred_bc_tap_3_2 = mcFilter[3][3];
221 regs->reg38.sw_pred_bc_tap_3_3 = mcFilter[3][4];
222 regs->reg38.sw_pred_bc_tap_4_0 = mcFilter[4][1];
223 regs->reg38.sw_pred_bc_tap_4_1 = mcFilter[4][2];
224 regs->reg39.sw_pred_bc_tap_4_2 = mcFilter[4][3];
225 regs->reg39.sw_pred_bc_tap_4_3 = mcFilter[4][4];
226 regs->reg39.sw_pred_bc_tap_5_0 = mcFilter[5][1];
227
228 regs->reg42.sw_pred_bc_tap_5_1 = mcFilter[5][2];
229 regs->reg42.sw_pred_bc_tap_5_2 = mcFilter[5][3];
230 regs->reg42.sw_pred_bc_tap_5_3 = mcFilter[5][4];
231
232 regs->reg43.sw_pred_bc_tap_6_0 = mcFilter[6][1];
233 regs->reg43.sw_pred_bc_tap_6_1 = mcFilter[6][2];
234 regs->reg43.sw_pred_bc_tap_6_2 = mcFilter[6][3];
235
236 regs->reg44.sw_pred_bc_tap_6_3 = mcFilter[6][4];
237 regs->reg44.sw_pred_bc_tap_7_0 = mcFilter[7][1];
238 regs->reg44.sw_pred_bc_tap_7_1 = mcFilter[7][2];
239
240 regs->reg45.sw_pred_bc_tap_7_2 = mcFilter[7][3];
241 regs->reg45.sw_pred_bc_tap_7_3 = mcFilter[7][4];
242
243 regs->reg45.sw_pred_tap_2_M1 = mcFilter[2][0];
244 regs->reg45.sw_pred_tap_2_4 = mcFilter[2][5];
245 regs->reg45.sw_pred_tap_4_M1 = mcFilter[4][0];
246 regs->reg45.sw_pred_tap_4_4 = mcFilter[4][5];
247 regs->reg45.sw_pred_tap_6_M1 = mcFilter[6][0];
248 regs->reg45.sw_pred_tap_6_4 = mcFilter[6][5];
249
250 FUN_T("leave\n");
251 return MPP_OK;
252 }
253
254 static MPP_RET
hal_vp8d_dct_partition_cfg(VP8DHalContext_t * ctx,HalTaskInfo * task)255 hal_vp8d_dct_partition_cfg(VP8DHalContext_t *ctx, HalTaskInfo *task)
256 {
257 RK_U32 i = 0, len = 0, len1 = 0;
258 RK_U32 extraBytesPacked = 0;
259 RK_U32 addr = 0, byte_offset = 0;
260 RK_U32 fd = 0;
261 MppBuffer streambuf = NULL;
262 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
263 DXVA_PicParams_VP8 *pic_param = (DXVA_PicParams_VP8 *)task->dec.syntax.data;
264
265
266 FUN_T("enter\n");
267
268 mpp_buf_slot_get_prop(ctx->packet_slots, task->dec.input,
269 SLOT_BUFFER, &streambuf);
270 fd = mpp_buffer_get_fd(streambuf);
271 regs->reg27_bitpl_ctrl_base = fd;
272 if (pic_param->stream_start_offset)
273 mpp_dev_set_reg_offset(ctx->dev, 27, pic_param->stream_start_offset);
274 regs->reg5.sw_strm1_start_bit = pic_param->stream_start_bit;
275
276 /* calculate dct partition length here instead */
277 if (pic_param->decMode == VP8HWD_VP8 && !pic_param->frame_type)
278 extraBytesPacked += 7;
279
280 len = pic_param->streamEndPos + pic_param->frameTagSize
281 - pic_param->dctPartitionOffsets[0];
282 len += ((1 << pic_param->log2_nbr_of_dct_partitions) - 1) * 3;
283 len1 = extraBytesPacked + pic_param->dctPartitionOffsets[0];
284 len += (len1 & 0x7);
285 regs->reg6.sw_stream_len = len;
286
287 len = pic_param->offsetToDctParts + pic_param->frameTagSize -
288 (pic_param->stream_start_offset - extraBytesPacked);
289 len++;
290
291 regs->reg9.sw_stream1_len = len;
292 regs->reg9.sw_coeffs_part_am = (1 << pic_param->log2_nbr_of_dct_partitions);
293 regs->reg9.sw_coeffs_part_am--;
294 for (i = 0; i < (RK_U32)(1 << pic_param->log2_nbr_of_dct_partitions); i++) {
295 addr = extraBytesPacked + pic_param->dctPartitionOffsets[i];
296 byte_offset = addr & 0x7;
297 addr = addr & 0xFFFFFFF8;
298
299 if (i == 0) {
300 regs->reg12_input_stream_base = fd;
301 if (addr) {
302 mpp_dev_set_reg_offset(ctx->dev, 12, addr);
303 }
304 } else if (i <= 5) {
305 regs->reg_dct_strm0_base[i - 1] = fd;
306 if (addr) {
307 mpp_dev_set_reg_offset(ctx->dev, 21 + i, addr);
308 }
309 } else {
310 regs->reg_dct_strm1_base[i - 6] = fd;
311 if (addr) {
312 mpp_dev_set_reg_offset(ctx->dev, 22 + i, addr);
313 }
314 }
315
316 switch (i) {
317 case 0:
318 regs->reg5.sw_strm0_start_bit = byte_offset * 8;
319 break;
320 case 1:
321 regs->reg7.sw_dct1_start_bit = byte_offset * 8;
322 break;
323 case 2:
324 regs->reg7.sw_dct2_start_bit = byte_offset * 8;
325 break;
326 case 3:
327 regs->reg11.sw_dct_start_bit_3 = byte_offset * 8;
328 break;
329 case 4:
330 regs->reg11.sw_dct_start_bit_4 = byte_offset * 8;
331 break;
332 case 5:
333 regs->reg11.sw_dct_start_bit_5 = byte_offset * 8;
334 break;
335 case 6:
336 regs->reg11.sw_dct_start_bit_6 = byte_offset * 8;
337 break;
338 case 7:
339 regs->reg11.sw_dct_start_bit_7 = byte_offset * 8;
340 break;
341 default:
342 break;
343 }
344 }
345
346 FUN_T("leave\n");
347 return MPP_OK;
348 }
349
hal_vp8hw_asic_probe_update(DXVA_PicParams_VP8 * p,RK_U8 * probTbl)350 static void hal_vp8hw_asic_probe_update(DXVA_PicParams_VP8 *p, RK_U8 *probTbl)
351 {
352 RK_U8 *dst;
353 RK_U32 i, j, k;
354
355 FUN_T("enter\n");
356 /* first probs */
357 dst = probTbl;
358
359 dst[0] = p->probe_skip_false;
360 dst[1] = p->prob_intra;
361 dst[2] = p->prob_last;
362 dst[3] = p->prob_golden;
363 dst[4] = p->stVP8Segments.mb_segment_tree_probs[0];
364 dst[5] = p->stVP8Segments.mb_segment_tree_probs[1];
365 dst[6] = p->stVP8Segments.mb_segment_tree_probs[2];
366 dst[7] = 0; /*unused*/
367
368 dst += 8;
369 dst[0] = p->intra_16x16_prob[0];
370 dst[1] = p->intra_16x16_prob[1];
371 dst[2] = p->intra_16x16_prob[2];
372 dst[3] = p->intra_16x16_prob[3];
373 dst[4] = p->intra_chroma_prob[0];
374 dst[5] = p->intra_chroma_prob[1];
375 dst[6] = p->intra_chroma_prob[2];
376 dst[7] = 0; /*unused*/
377
378 /* mv probs */
379 dst += 8;
380 dst[0] = p->vp8_mv_update_probs[0][0]; /* is short */
381 dst[1] = p->vp8_mv_update_probs[1][0];
382 dst[2] = p->vp8_mv_update_probs[0][1]; /* sign */
383 dst[3] = p->vp8_mv_update_probs[1][1];
384 dst[4] = p->vp8_mv_update_probs[0][8 + 9];
385 dst[5] = p->vp8_mv_update_probs[0][9 + 9];
386 dst[6] = p->vp8_mv_update_probs[1][8 + 9];
387 dst[7] = p->vp8_mv_update_probs[1][9 + 9];
388 dst += 8;
389 for ( i = 0 ; i < 2 ; ++i ) {
390 for ( j = 0 ; j < 8 ; j += 4 ) {
391 dst[0] = p->vp8_mv_update_probs[i][j + 9 + 0];
392 dst[1] = p->vp8_mv_update_probs[i][j + 9 + 1];
393 dst[2] = p->vp8_mv_update_probs[i][j + 9 + 2];
394 dst[3] = p->vp8_mv_update_probs[i][j + 9 + 3];
395 dst += 4;
396 }
397 }
398 for ( i = 0 ; i < 2 ; ++i ) {
399 dst[0] = p->vp8_mv_update_probs[i][0 + 2];
400 dst[1] = p->vp8_mv_update_probs[i][1 + 2];
401 dst[2] = p->vp8_mv_update_probs[i][2 + 2];
402 dst[3] = p->vp8_mv_update_probs[i][3 + 2];
403 dst[4] = p->vp8_mv_update_probs[i][4 + 2];
404 dst[5] = p->vp8_mv_update_probs[i][5 + 2];
405 dst[6] = p->vp8_mv_update_probs[i][6 + 2];
406 dst[7] = 0; /*unused*/
407 dst += 8;
408 }
409
410 /* coeff probs (header part) */
411 dst = (RK_U8*)probTbl;
412 dst += (8 * 7);
413 for ( i = 0 ; i < 4 ; ++i ) {
414 for ( j = 0 ; j < 8 ; ++j ) {
415 for ( k = 0 ; k < 3 ; ++k ) {
416 dst[0] = p->vp8_coef_update_probs[i][j][k][0];
417 dst[1] = p->vp8_coef_update_probs[i][j][k][1];
418 dst[2] = p->vp8_coef_update_probs[i][j][k][2];
419 dst[3] = p->vp8_coef_update_probs[i][j][k][3];
420 dst += 4;
421 }
422 }
423 }
424
425 /* coeff probs (footer part) */
426 dst = (RK_U8*)probTbl;
427 dst += (8 * 55);
428 for ( i = 0 ; i < 4 ; ++i ) {
429 for ( j = 0 ; j < 8 ; ++j ) {
430 for ( k = 0 ; k < 3 ; ++k ) {
431 dst[0] = p->vp8_coef_update_probs[i][j][k][4];
432 dst[1] = p->vp8_coef_update_probs[i][j][k][5];
433 dst[2] = p->vp8_coef_update_probs[i][j][k][6];
434 dst[3] = p->vp8_coef_update_probs[i][j][k][7];
435 dst[4] = p->vp8_coef_update_probs[i][j][k][8];
436 dst[5] = p->vp8_coef_update_probs[i][j][k][9];
437 dst[6] = p->vp8_coef_update_probs[i][j][k][10];
438 dst[7] = 0; /*unused*/
439 dst += 8;
440 }
441 }
442 }
443 FUN_T("leave\n");
444 return ;
445 }
446
hal_vp8d_vdpu1_gen_regs(void * hal,HalTaskInfo * task)447 MPP_RET hal_vp8d_vdpu1_gen_regs(void* hal, HalTaskInfo *task)
448 {
449 MPP_RET ret = MPP_OK;
450 RK_U32 mb_width = 0, mb_height = 0;
451 MppBuffer framebuf = NULL;
452 RK_U8 *segmap_ptr = NULL;
453 RK_U8 *probe_ptr = NULL;
454 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
455 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
456 DXVA_PicParams_VP8 *pic_param = (DXVA_PicParams_VP8 *)task->dec.syntax.data;
457
458 FUN_T("enter\n");
459
460 hal_vp8_init_hwcfg(ctx);
461 mb_width = (pic_param->width + 15) >> 4;
462 mb_height = (pic_param->height + 15) >> 4;
463
464 regs->reg4.sw_pic_mb_width = mb_width & 0x1FF;
465 regs->reg4.sw_pic_mb_hight_p = mb_height & 0xFF;
466 regs->reg4.sw_pic_mb_w_ext = mb_width >> 9;
467 regs->reg4.sw_pic_mb_h_ext = mb_height >> 8;
468
469 if (!pic_param->frame_type) {
470 segmap_ptr = mpp_buffer_get_ptr(ctx->seg_map);
471 if (NULL != segmap_ptr) {
472 memset(segmap_ptr, 0, VP8D_MAX_SEGMAP_SIZE);
473 }
474 }
475
476 probe_ptr = mpp_buffer_get_ptr(ctx->probe_table);
477 if (NULL != probe_ptr) {
478 hal_vp8hw_asic_probe_update(pic_param, probe_ptr);
479 }
480 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->CurrPic.Index7Bits, SLOT_BUFFER, &framebuf);
481 regs->reg13_cur_pic_base = mpp_buffer_get_fd(framebuf);
482 if (!pic_param->frame_type) { //key frame
483 if ((mb_width * mb_height) << 8 > 0x400000) {
484 mpp_log("mb_width*mb_height is big then 0x400000,iommu err");
485 }
486 regs->reg14_ref0_base = regs->reg13_cur_pic_base;
487 mpp_dev_set_reg_offset(ctx->dev, 14, (mb_width * mb_height) << 8);
488 } else if (pic_param->lst_fb_idx.Index7Bits < 0x7f) { //config ref0 base
489 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->lst_fb_idx.Index7Bits, SLOT_BUFFER, &framebuf);
490 regs->reg14_ref0_base = mpp_buffer_get_fd(framebuf);
491 } else {
492 regs->reg14_ref0_base = regs->reg13_cur_pic_base;
493 }
494
495 /* golden reference */
496 if (pic_param->gld_fb_idx.Index7Bits < 0x7f) {
497 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->gld_fb_idx.Index7Bits, SLOT_BUFFER, &framebuf);
498 regs->reg18_golden_ref_base = mpp_buffer_get_fd(framebuf);
499 } else {
500 regs->reg18_golden_ref_base = regs->reg13_cur_pic_base;
501 }
502
503 if (pic_param->ref_frame_sign_bias_golden) {
504 mpp_dev_set_reg_offset(ctx->dev, 18, pic_param->ref_frame_sign_bias_golden);
505 }
506
507 /* alternate reference */
508 if (pic_param->alt_fb_idx.Index7Bits < 0x7f) {
509 mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->alt_fb_idx.Index7Bits, SLOT_BUFFER, &framebuf);
510 regs->reg19.alternate_ref_base = mpp_buffer_get_fd(framebuf);
511 } else {
512 regs->reg19.alternate_ref_base = regs->reg13_cur_pic_base;
513 }
514
515 if (pic_param->ref_frame_sign_bias_altref) {
516 mpp_dev_set_reg_offset(ctx->dev, 19, pic_param->ref_frame_sign_bias_altref);
517 }
518
519 if (pic_param->stVP8Segments.segmentation_enabled || pic_param->stVP8Segments.update_mb_segmentation_map) {
520 mpp_dev_set_reg_offset(ctx->dev, 10, (pic_param->stVP8Segments.segmentation_enabled
521 + (pic_param->stVP8Segments.update_mb_segmentation_map << 1)));
522 }
523
524 regs->reg3.sw_pic_inter_e = pic_param->frame_type;
525 regs->reg3.sw_skip_mode = !pic_param->mb_no_coeff_skip;
526
527 if (!pic_param->stVP8Segments.segmentation_enabled) {
528 regs->reg32.sw_filt_level_0 = pic_param->filter_level;
529 } else if (pic_param->stVP8Segments.update_mb_segmentation_data) {
530 regs->reg32.sw_filt_level_0 =
531 pic_param->stVP8Segments.segment_feature_data[1][0];
532 regs->reg32.sw_filt_level_1 =
533 pic_param->stVP8Segments.segment_feature_data[1][1];
534 regs->reg32.sw_filt_level_2 =
535 pic_param->stVP8Segments.segment_feature_data[1][2];
536 regs->reg32.sw_filt_level_3 =
537 pic_param->stVP8Segments.segment_feature_data[1][3];
538 } else {
539 regs->reg32.sw_filt_level_0 = CLIP3(0, 63,
540 (RK_S32)pic_param->filter_level
541 + pic_param->stVP8Segments.segment_feature_data[1][0]);
542 regs->reg32.sw_filt_level_1 = CLIP3(0, 63,
543 (RK_S32)pic_param->filter_level
544 + pic_param->stVP8Segments.segment_feature_data[1][1]);
545 regs->reg32.sw_filt_level_2 = CLIP3(0, 63,
546 (RK_S32)pic_param->filter_level
547 + pic_param->stVP8Segments.segment_feature_data[1][2]);
548 regs->reg32.sw_filt_level_3 = CLIP3(0, 63,
549 (RK_S32)pic_param->filter_level
550 + pic_param->stVP8Segments.segment_feature_data[1][3]);
551 }
552
553 regs->reg30.sw_filt_type = pic_param->filter_type;
554 regs->reg30.sw_filt_sharpness = pic_param->sharpness;
555
556 if (pic_param->filter_level == 0)
557 regs->reg3.sw_filtering_dis = 1;
558
559 if (pic_param->version != 3)
560 regs->reg7.sw_ch_mv_res = 1;
561
562 if (pic_param->decMode == VP8HWD_VP8 && (pic_param->version & 0x3))
563 regs->reg7.sw_bilin_mc_e = 1;
564
565 regs->reg5.sw_boolean_value = pic_param->bool_value;
566 regs->reg5.sw_boolean_range = pic_param->bool_range;
567
568 {
569 if (!pic_param->stVP8Segments.segmentation_enabled)
570 regs->reg33.sw_quant_0 = pic_param->y1ac_delta_q;
571 else if (pic_param->stVP8Segments.update_mb_segmentation_data) { /* absolute mode */
572 regs->reg33.sw_quant_0 =
573 pic_param->stVP8Segments.segment_feature_data[0][0];
574 regs->reg33.sw_quant_1 =
575 pic_param->stVP8Segments.segment_feature_data[0][1];
576 regs->reg46.sw_quant_2 = pic_param->stVP8Segments.segment_feature_data[0][2];
577 regs->reg46.sw_quant_3 = pic_param->stVP8Segments.segment_feature_data[0][3];
578 } else { /* delta mode */
579 regs->reg33.sw_quant_0 = CLIP3(0, 127,
580 pic_param->y1ac_delta_q
581 + pic_param->stVP8Segments.segment_feature_data[0][0]);
582 regs->reg33.sw_quant_1 = CLIP3(0, 127,
583 pic_param->y1ac_delta_q
584 + pic_param->stVP8Segments.segment_feature_data[0][1]);
585 regs->reg46.sw_quant_2 = CLIP3(0, 127,
586 pic_param->y1ac_delta_q
587 + pic_param->stVP8Segments.segment_feature_data[0][2]);
588 regs->reg46.sw_quant_3 = CLIP3(0, 127,
589 pic_param->y1ac_delta_q
590 + pic_param->stVP8Segments.segment_feature_data[0][3]);
591 }
592
593 regs->reg33.sw_quant_delta_0 = pic_param->y1dc_delta_q;
594 regs->reg33.sw_quant_delta_1 = pic_param->y2dc_delta_q;
595 regs->reg46.sw_quant_delta_2 = pic_param->y2ac_delta_q;
596 regs->reg46.sw_quant_delta_3 = pic_param->uvdc_delta_q;
597 regs->reg47.sw_quant_delta_4 = pic_param->uvac_delta_q;
598
599 if (pic_param->mode_ref_lf_delta_enabled) {
600 regs->reg31.sw_filt_ref_adj_0 = pic_param->ref_lf_deltas[0];
601 regs->reg31.sw_filt_ref_adj_1 = pic_param->ref_lf_deltas[1];
602 regs->reg31.sw_filt_ref_adj_2 = pic_param->ref_lf_deltas[2];
603 regs->reg31.sw_filt_ref_adj_3 = pic_param->ref_lf_deltas[3];
604 regs->reg30.sw_filt_mb_adj_0 = pic_param->mode_lf_deltas[0];
605 regs->reg30.sw_filt_mb_adj_1 = pic_param->mode_lf_deltas[1];
606 regs->reg30.sw_filt_mb_adj_2 = pic_param->mode_lf_deltas[2];
607 regs->reg30.sw_filt_mb_adj_3 = pic_param->mode_lf_deltas[3];
608 }
609 }
610
611 if ((pic_param->version & 0x3) == 0)
612 hal_vp8d_pre_filter_tap_set(ctx);
613
614 hal_vp8d_dct_partition_cfg(ctx, task);
615
616 mpp_buffer_sync_end(ctx->probe_table);
617 mpp_buffer_sync_end(ctx->seg_map);
618
619 FUN_T("leave\n");
620 return ret;
621 }
622
hal_vp8d_vdpu1_start(void * hal,HalTaskInfo * task)623 MPP_RET hal_vp8d_vdpu1_start(void *hal, HalTaskInfo *task)
624 {
625 MPP_RET ret = MPP_OK;
626 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
627 VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
628
629 FUN_T("enter\n");
630
631 if (hal_vp8d_debug & VP8H_DBG_REG) {
632 RK_U32 *p = ctx->regs;
633 RK_U32 i = 0;
634
635 for (i = 0; i < VP8D_REG_NUM; i++)
636 mpp_log_f("vp8d: regs[%02d]=%08X\n", i, *p++);
637 }
638
639 do {
640 MppDevRegWrCfg wr_cfg;
641 MppDevRegRdCfg rd_cfg;
642 RK_U32 reg_size = sizeof(VP8DRegSet_t);
643
644 wr_cfg.reg = regs;
645 wr_cfg.size = reg_size;
646 wr_cfg.offset = 0;
647
648 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
649 if (ret) {
650 mpp_err_f("set register write failed %d\n", ret);
651 break;
652 }
653
654 rd_cfg.reg = regs;
655 rd_cfg.size = reg_size;
656 rd_cfg.offset = 0;
657
658 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
659 if (ret) {
660 mpp_err_f("set register read failed %d\n", ret);
661 break;
662 }
663
664 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
665 if (ret) {
666 mpp_err_f("send cmd failed %d\n", ret);
667 break;
668 }
669 } while (0);
670
671 FUN_T("leave\n");
672
673 (void)task;
674 return ret;
675 }
676
hal_vp8d_vdpu1_wait(void * hal,HalTaskInfo * task)677 MPP_RET hal_vp8d_vdpu1_wait(void *hal, HalTaskInfo *task)
678 {
679 MPP_RET ret = MPP_OK;
680 VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
681
682 FUN_T("enter\n");
683
684 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
685 if (ret)
686 mpp_err_f("poll cmd failed %d\n", ret);
687
688 (void)task;
689 FUN_T("leave\n");
690 return ret;
691 }
692