Lines Matching refs:regs
66 VdpuAv1dRegSet *regs; member
103 VdpuAv1dRegSet *regs; member
144 reg_ctx->reg_buf[i].regs = mpp_calloc(VdpuAv1dRegSet, 1); in hal_av1d_alloc_res()
145 memset(reg_ctx->reg_buf[i].regs, 0, sizeof(VdpuAv1dRegSet)); in hal_av1d_alloc_res()
149 reg_ctx->regs = reg_ctx->reg_buf[0].regs; in hal_av1d_alloc_res()
240 MPP_FREE(reg_ctx->reg_buf[i].regs); in hal_av1d_release_res()
290 static void set_ref_width(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) in set_ref_width() argument
293 regs->swreg33.sw_ref0_width = val; in set_ref_width()
295 regs->swreg34.sw_ref1_width = val; in set_ref_width()
297 regs->swreg35.sw_ref2_width = val; in set_ref_width()
299 regs->swreg43.sw_ref3_width = val; in set_ref_width()
301 regs->swreg44.sw_ref4_width = val; in set_ref_width()
303 regs->swreg45.sw_ref5_width = val; in set_ref_width()
305 regs->swreg46.sw_ref6_width = val; in set_ref_width()
311 static void set_ref_height(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) in set_ref_height() argument
314 regs->swreg33.sw_ref0_height = val; in set_ref_height()
316 regs->swreg34.sw_ref1_height = val; in set_ref_height()
318 regs->swreg35.sw_ref2_height = val; in set_ref_height()
320 regs->swreg43.sw_ref3_height = val; in set_ref_height()
322 regs->swreg44.sw_ref4_height = val; in set_ref_height()
324 regs->swreg45.sw_ref5_height = val; in set_ref_height()
326 regs->swreg46.sw_ref6_height = val; in set_ref_height()
332 static void set_ref_hor_scale(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) in set_ref_hor_scale() argument
335 regs->swreg36.sw_ref0_hor_scale = val; in set_ref_hor_scale()
337 regs->swreg37.sw_ref1_hor_scale = val; in set_ref_hor_scale()
339 regs->swreg38.sw_ref2_hor_scale = val; in set_ref_hor_scale()
341 regs->swreg39.sw_ref3_hor_scale = val; in set_ref_hor_scale()
343 regs->swreg40.sw_ref4_hor_scale = val; in set_ref_hor_scale()
345 regs->swreg41.sw_ref5_hor_scale = val; in set_ref_hor_scale()
347 regs->swreg42.sw_ref6_hor_scale = val; in set_ref_hor_scale()
353 static void set_ref_ver_scale(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) in set_ref_ver_scale() argument
356 regs->swreg36.sw_ref0_ver_scale = val; in set_ref_ver_scale()
358 regs->swreg37.sw_ref1_ver_scale = val; in set_ref_ver_scale()
360 regs->swreg38.sw_ref2_ver_scale = val; in set_ref_ver_scale()
362 regs->swreg39.sw_ref3_ver_scale = val; in set_ref_ver_scale()
364 regs->swreg40.sw_ref4_ver_scale = val; in set_ref_ver_scale()
366 regs->swreg41.sw_ref5_ver_scale = val; in set_ref_ver_scale()
368 regs->swreg42.sw_ref6_ver_scale = val; in set_ref_ver_scale()
374 static void set_ref_lum_base(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val, HalBufs bufs) in set_ref_lum_base() argument
386 regs->addr_cfg.swreg67.sw_refer0_ybase_lsb = val; in set_ref_lum_base()
388 regs->addr_cfg.swreg69.sw_refer1_ybase_lsb = val; in set_ref_lum_base()
390 regs->addr_cfg.swreg71.sw_refer2_ybase_lsb = val; in set_ref_lum_base()
392 regs->addr_cfg.swreg73.sw_refer3_ybase_lsb = val; in set_ref_lum_base()
394 regs->addr_cfg.swreg75.sw_refer4_ybase_lsb = val; in set_ref_lum_base()
396 regs->addr_cfg.swreg77.sw_refer5_ybase_lsb = val; in set_ref_lum_base()
398 regs->addr_cfg.swreg79.sw_refer6_ybase_lsb = val; in set_ref_lum_base()
404 static void set_ref_lum_base_msb(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) in set_ref_lum_base_msb() argument
407 regs->addr_cfg.swreg66.sw_refer0_ybase_msb = val; in set_ref_lum_base_msb()
409 regs->addr_cfg.swreg68.sw_refer1_ybase_msb = val; in set_ref_lum_base_msb()
411 regs->addr_cfg.swreg70.sw_refer2_ybase_msb = val; in set_ref_lum_base_msb()
413 regs->addr_cfg.swreg72.sw_refer3_ybase_msb = val; in set_ref_lum_base_msb()
415 regs->addr_cfg.swreg74.sw_refer4_ybase_msb = val; in set_ref_lum_base_msb()
417 regs->addr_cfg.swreg76.sw_refer5_ybase_msb = val; in set_ref_lum_base_msb()
419 regs->addr_cfg.swreg78.sw_refer6_ybase_msb = val; in set_ref_lum_base_msb()
428 VdpuAv1dRegSet *regs = ctx->regs; in set_ref_cb_base() local
442 regs->addr_cfg.swreg101.sw_refer0_cbase_lsb = val; in set_ref_cb_base()
445 regs->addr_cfg.swreg103.sw_refer1_cbase_lsb = val; in set_ref_cb_base()
448 regs->addr_cfg.swreg105.sw_refer2_cbase_lsb = val; in set_ref_cb_base()
451 regs->addr_cfg.swreg107.sw_refer3_cbase_lsb = val; in set_ref_cb_base()
454 regs->addr_cfg.swreg109.sw_refer4_cbase_lsb = val; in set_ref_cb_base()
457 regs->addr_cfg.swreg111.sw_refer5_cbase_lsb = val; in set_ref_cb_base()
460 regs->addr_cfg.swreg113.sw_refer6_cbase_lsb = val; in set_ref_cb_base()
466 static void set_ref_cb_base_msb(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) in set_ref_cb_base_msb() argument
469 regs->addr_cfg.swreg100.sw_refer0_cbase_msb = val; in set_ref_cb_base_msb()
471 regs->addr_cfg.swreg102.sw_refer1_cbase_msb = val; in set_ref_cb_base_msb()
473 regs->addr_cfg.swreg104.sw_refer2_cbase_msb = val; in set_ref_cb_base_msb()
475 regs->addr_cfg.swreg106.sw_refer3_cbase_msb = val; in set_ref_cb_base_msb()
477 regs->addr_cfg.swreg108.sw_refer4_cbase_msb = val; in set_ref_cb_base_msb()
479 regs->addr_cfg.swreg110.sw_refer5_cbase_msb = val; in set_ref_cb_base_msb()
481 regs->addr_cfg.swreg112.sw_refer6_cbase_msb = val; in set_ref_cb_base_msb()
491 VdpuAv1dRegSet *regs = ctx->regs; in set_ref_dbase() local
504 regs->addr_cfg.swreg135.sw_refer0_dbase_lsb = val; in set_ref_dbase()
507 regs->addr_cfg.swreg137.sw_refer1_dbase_lsb = val; in set_ref_dbase()
510 regs->addr_cfg.swreg139.sw_refer2_dbase_lsb = val; in set_ref_dbase()
513 regs->addr_cfg.swreg141.sw_refer3_dbase_lsb = val; in set_ref_dbase()
516 regs->addr_cfg.swreg143.sw_refer4_dbase_lsb = val; in set_ref_dbase()
519 regs->addr_cfg.swreg145.sw_refer5_dbase_lsb = val; in set_ref_dbase()
522 regs->addr_cfg.swreg147.sw_refer6_dbase_lsb = val; in set_ref_dbase()
528 static void set_ref_dbase_msb(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) in set_ref_dbase_msb() argument
531 regs->addr_cfg.swreg134.sw_refer0_dbase_msb = val; in set_ref_dbase_msb()
533 regs->addr_cfg.swreg136.sw_refer1_dbase_msb = val; in set_ref_dbase_msb()
535 regs->addr_cfg.swreg138.sw_refer2_dbase_msb = val; in set_ref_dbase_msb()
537 regs->addr_cfg.swreg140.sw_refer3_dbase_msb = val; in set_ref_dbase_msb()
539 regs->addr_cfg.swreg142.sw_refer4_dbase_msb = val; in set_ref_dbase_msb()
541 regs->addr_cfg.swreg144.sw_refer5_dbase_msb = val; in set_ref_dbase_msb()
543 regs->addr_cfg.swreg146.sw_refer6_dbase_msb = val; in set_ref_dbase_msb()
549 static void set_ref_ty_base(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val, HalBufs bufs) in set_ref_ty_base() argument
562 regs->swreg192.sw_refer0_tybase_lsb = val; in set_ref_ty_base()
564 regs->swreg194.sw_refer1_tybase_lsb = val; in set_ref_ty_base()
566 regs->swreg196.sw_refer2_tybase_lsb = val; in set_ref_ty_base()
568 regs->swreg198.sw_refer3_tybase_lsb = val; in set_ref_ty_base()
570 regs->swreg200.sw_refer4_tybase_lsb = val; in set_ref_ty_base()
572 regs->swreg202.sw_refer5_tybase_lsb = val; in set_ref_ty_base()
574 regs->swreg204.sw_refer6_tybase_lsb = val; in set_ref_ty_base()
580 static void set_ref_ty_base_msb(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) in set_ref_ty_base_msb() argument
583 regs->swreg191.sw_refer0_tybase_msb = val; in set_ref_ty_base_msb()
585 regs->swreg193.sw_refer1_tybase_msb = val; in set_ref_ty_base_msb()
587 regs->swreg195.sw_refer2_tybase_msb = val; in set_ref_ty_base_msb()
589 regs->swreg197.sw_refer3_tybase_msb = val; in set_ref_ty_base_msb()
591 regs->swreg199.sw_refer4_tybase_msb = val; in set_ref_ty_base_msb()
593 regs->swreg201.sw_refer5_tybase_msb = val; in set_ref_ty_base_msb()
595 regs->swreg203.sw_refer6_tybase_msb = val; in set_ref_ty_base_msb()
601 static void set_ref_tc_base(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val, HalBufs bufs) in set_ref_tc_base() argument
614 regs->swreg226.sw_refer0_tcbase_lsb = val; in set_ref_tc_base()
616 regs->swreg228.sw_refer1_tcbase_lsb = val; in set_ref_tc_base()
618 regs->swreg230.sw_refer2_tcbase_lsb = val; in set_ref_tc_base()
620 regs->swreg232.sw_refer3_tcbase_lsb = val; in set_ref_tc_base()
622 regs->swreg234.sw_refer4_tcbase_lsb = val; in set_ref_tc_base()
624 regs->swreg236.sw_refer5_tcbase_lsb = val; in set_ref_tc_base()
626 regs->swreg238.sw_refer6_tcbase_lsb = val; in set_ref_tc_base()
633 static void set_ref_tc_base_msb(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) in set_ref_tc_base_msb() argument
636 regs->swreg225.sw_refer0_tcbase_msb = val; in set_ref_tc_base_msb()
638 regs->swreg227.sw_refer1_tcbase_msb = val; in set_ref_tc_base_msb()
640 regs->swreg229.sw_refer2_tcbase_msb = val; in set_ref_tc_base_msb()
642 regs->swreg231.sw_refer3_tcbase_msb = val; in set_ref_tc_base_msb()
644 regs->swreg233.sw_refer4_tcbase_msb = val; in set_ref_tc_base_msb()
646 regs->swreg235.sw_refer5_tcbase_msb = val; in set_ref_tc_base_msb()
648 regs->swreg237.sw_refer6_tcbase_msb = val; in set_ref_tc_base_msb()
654 static void set_ref_sign_bias(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) in set_ref_sign_bias() argument
657 regs->swreg59.sw_ref0_sign_bias = val; in set_ref_sign_bias()
659 regs->swreg59.sw_ref1_sign_bias = val; in set_ref_sign_bias()
661 regs->swreg59.sw_ref2_sign_bias = val; in set_ref_sign_bias()
663 regs->swreg59.sw_ref3_sign_bias = val; in set_ref_sign_bias()
665 regs->swreg9.sw_ref4_sign_bias = val; in set_ref_sign_bias()
667 regs->swreg9.sw_ref5_sign_bias = val; in set_ref_sign_bias()
669 regs->swreg9.sw_ref6_sign_bias = val; in set_ref_sign_bias()
708 regs->swreg20.sw_mf1_last_offset = ref_offset[0]; \
709 regs->swreg21.sw_mf1_last2_offset = ref_offset[1]; \
710 regs->swreg22.sw_mf1_last3_offset = ref_offset[2]; \
711 regs->swreg23.sw_mf1_golden_offset = ref_offset[3]; \
712 regs->swreg24.sw_mf1_bwdref_offset = ref_offset[4]; \
713 regs->swreg25.sw_mf1_altref2_offset = ref_offset[5]; \
714 regs->swreg26.sw_mf1_altref_offset = ref_offset[6]; \
716 regs->swreg27.sw_mf2_last_offset = ref_offset[0]; \
717 regs->swreg47.sw_mf2_last2_offset = ref_offset[1]; \
718 regs->swreg47.sw_mf2_last3_offset = ref_offset[2]; \
719 regs->swreg47.sw_mf2_golden_offset = ref_offset[3]; \
720 regs->swreg48.sw_mf2_bwdref_offset = ref_offset[4]; \
721 regs->swreg48.sw_mf2_altref2_offset = ref_offset[5]; \
722 regs->swreg48.sw_mf2_altref_offset = ref_offset[6]; \
724 regs->swreg184.sw_mf3_last_offset = ref_offset[0]; \
725 regs->swreg185.sw_mf3_last2_offset = ref_offset[1]; \
726 regs->swreg186.sw_mf3_last3_offset = ref_offset[2]; \
727 regs->swreg187.sw_mf3_golden_offset = ref_offset[3]; \
728 regs->swreg188.sw_mf3_bwdref_offset = ref_offset[4]; \
729 regs->swreg257.sw_mf3_altref2_offset = ref_offset[5]; \
730 regs->swreg262.sw_mf3_altref_offset = ref_offset[6]; \
764 VdpuAv1dRegSet *regs = reg_ctx->regs; in vdpu_av1d_set_prob() local
774 …regs->addr_cfg.swreg171.sw_prob_tab_out_base_lsb = mpp_buffer_get_fd(reg_ctx->prob_tbl_out_base… in vdpu_av1d_set_prob()
775 regs->addr_cfg.swreg173.sw_prob_tab_base_lsb = mpp_buffer_get_fd(reg_ctx->prob_tbl_base); in vdpu_av1d_set_prob()
785 VdpuAv1dRegSet *regs = ctx->regs; in vdpu_av1d_set_reference_frames() local
801 regs->swreg4.sw_ref_frames++; in vdpu_av1d_set_reference_frames()
804 regs->swreg4.sw_ref_frames = 1; in vdpu_av1d_set_reference_frames()
826 set_ref_width(regs, ref, tmp1); in vdpu_av1d_set_reference_frames()
827 set_ref_height(regs, ref, tmp2); in vdpu_av1d_set_reference_frames()
831 set_ref_hor_scale(regs, ref, tmp1); in vdpu_av1d_set_reference_frames()
832 set_ref_ver_scale(regs, ref, tmp2); in vdpu_av1d_set_reference_frames()
842 set_ref_lum_base(regs, ref, idx, ctx->tile_out_bufs); in vdpu_av1d_set_reference_frames()
846 set_ref_lum_base_msb(regs, ref, 0); in vdpu_av1d_set_reference_frames()
847 set_ref_cb_base_msb(regs, ref, 0); in vdpu_av1d_set_reference_frames()
848 set_ref_dbase_msb (regs, ref, 0); in vdpu_av1d_set_reference_frames()
851 set_ref_ty_base(regs, ref, idx, ctx->tile_out_bufs); in vdpu_av1d_set_reference_frames()
852 set_ref_tc_base(regs, ref, idx, ctx->tile_out_bufs); in vdpu_av1d_set_reference_frames()
853 set_ref_ty_base_msb(regs, ref, 0); in vdpu_av1d_set_reference_frames()
854 set_ref_tc_base_msb(regs, ref, 0); in vdpu_av1d_set_reference_frames()
856 set_ref_sign_bias(regs, ref, ctx->ref_frame_sign_bias[i]); in vdpu_av1d_set_reference_frames()
859 regs->swreg184.sw_ref0_gm_mode = dxva->frame_refs[0].wmtype; in vdpu_av1d_set_reference_frames()
860 regs->swreg185.sw_ref1_gm_mode = dxva->frame_refs[1].wmtype; in vdpu_av1d_set_reference_frames()
861 regs->swreg186.sw_ref2_gm_mode = dxva->frame_refs[2].wmtype; in vdpu_av1d_set_reference_frames()
862 regs->swreg187.sw_ref3_gm_mode = dxva->frame_refs[3].wmtype; in vdpu_av1d_set_reference_frames()
863 regs->swreg188.sw_ref4_gm_mode = dxva->frame_refs[4].wmtype; in vdpu_av1d_set_reference_frames()
864 regs->swreg257.sw_ref5_gm_mode = dxva->frame_refs[5].wmtype; in vdpu_av1d_set_reference_frames()
865 regs->swreg262.sw_ref6_gm_mode = dxva->frame_refs[6].wmtype; in vdpu_av1d_set_reference_frames()
1016 regs->swreg11.sw_use_temporal0_mvs = 0; in vdpu_av1d_set_reference_frames()
1017 regs->swreg11.sw_use_temporal1_mvs = 0; in vdpu_av1d_set_reference_frames()
1018 regs->swreg11.sw_use_temporal2_mvs = 0; in vdpu_av1d_set_reference_frames()
1019 regs->swreg11.sw_use_temporal3_mvs = 0; in vdpu_av1d_set_reference_frames()
1024 regs->swreg11.sw_use_temporal0_mvs = 1; in vdpu_av1d_set_reference_frames()
1031 regs->swreg11.sw_use_temporal1_mvs = 1; in vdpu_av1d_set_reference_frames()
1038 regs->swreg11.sw_use_temporal2_mvs = 1; in vdpu_av1d_set_reference_frames()
1056 regs->addr_cfg.swreg80.sw_segment_read_base_msb = 0; in vdpu_av1d_set_reference_frames()
1057 … regs->addr_cfg.swreg81.sw_segment_read_base_lsb = mpp_buffer_get_fd(tile_out_buf->buf[0]); in vdpu_av1d_set_reference_frames()
1059 regs->swreg11.sw_use_temporal3_mvs = 1; in vdpu_av1d_set_reference_frames()
1073 regs->swreg184.sw_cur_last_offset = cur_offset[0]; in vdpu_av1d_set_reference_frames()
1074 regs->swreg185.sw_cur_last2_offset = cur_offset[1]; in vdpu_av1d_set_reference_frames()
1075 regs->swreg186.sw_cur_last3_offset = cur_offset[2]; in vdpu_av1d_set_reference_frames()
1076 regs->swreg187.sw_cur_golden_offset = cur_offset[3]; in vdpu_av1d_set_reference_frames()
1077 regs->swreg188.sw_cur_bwdref_offset = cur_offset[4]; in vdpu_av1d_set_reference_frames()
1078 regs->swreg257.sw_cur_altref2_offset = cur_offset[5]; in vdpu_av1d_set_reference_frames()
1079 regs->swreg262.sw_cur_altref_offset = cur_offset[6]; in vdpu_av1d_set_reference_frames()
1081 regs->swreg184.sw_cur_last_roffset = cur_roffset[0]; in vdpu_av1d_set_reference_frames()
1082 regs->swreg185.sw_cur_last2_roffset = cur_roffset[1]; in vdpu_av1d_set_reference_frames()
1083 regs->swreg186.sw_cur_last3_roffset = cur_roffset[2]; in vdpu_av1d_set_reference_frames()
1084 regs->swreg187.sw_cur_golden_roffset = cur_roffset[3]; in vdpu_av1d_set_reference_frames()
1085 regs->swreg188.sw_cur_bwdref_roffset = cur_roffset[4]; in vdpu_av1d_set_reference_frames()
1086 regs->swreg257.sw_cur_altref2_roffset = cur_roffset[5]; in vdpu_av1d_set_reference_frames()
1087 regs->swreg262.sw_cur_altref_roffset = cur_roffset[6]; in vdpu_av1d_set_reference_frames()
1090 regs->swreg9.sw_mf1_type = mf_types[0] - LAST_FRAME; in vdpu_av1d_set_reference_frames()
1091 regs->swreg9.sw_mf2_type = mf_types[1] - LAST_FRAME; in vdpu_av1d_set_reference_frames()
1092 regs->swreg9.sw_mf3_type = mf_types[2] - LAST_FRAME; in vdpu_av1d_set_reference_frames()
1095 regs->swreg5.sw_ref_scaling_enable = ref_scale_e; in vdpu_av1d_set_reference_frames()
1113 VdpuAv1dRegSet *regs = ctx->regs; in vdpu_av1d_superres_params() local
1124 superres_scale_denominator = regs->swreg9.sw_scale_denom_minus9 + 9; in vdpu_av1d_superres_params()
1198 regs->swreg51.sw_superres_luma_step = superres_luma_step; in vdpu_av1d_superres_params()
1199 regs->swreg51.sw_superres_chroma_step = superres_chroma_step; in vdpu_av1d_superres_params()
1200 regs->swreg298.sw_superres_luma_step_invra = superres_luma_step_invra; in vdpu_av1d_superres_params()
1201 regs->swreg298.sw_superres_chroma_step_invra = superres_chroma_step_invra; in vdpu_av1d_superres_params()
1202 regs->swreg52.sw_superres_init_luma_subpel_x = superres_init_luma_subpel_x; in vdpu_av1d_superres_params()
1203 regs->swreg52.sw_superres_init_chroma_subpel_x = superres_init_chroma_subpel_x; in vdpu_av1d_superres_params()
1204 regs->swreg5.sw_superres_is_scaled = superres_is_scaled; in vdpu_av1d_superres_params()
1206 regs->addr_cfg.swreg89.sw_superres_colbuf_base_lsb = mpp_buffer_get_fd(ctx->filter_mem); in vdpu_av1d_superres_params()
1216 VdpuAv1dRegSet *regs = ctx->regs; in vdpu_av1d_set_picture_dimensions() local
1218 regs->swreg4.sw_pic_width_in_cbs = MPP_ALIGN(dxva->width, 8) >> 3; in vdpu_av1d_set_picture_dimensions()
1219 regs->swreg4.sw_pic_height_in_cbs = MPP_ALIGN(dxva->height, 8) >> 3; in vdpu_av1d_set_picture_dimensions()
1220 regs->swreg12.sw_pic_width_pad = MPP_ALIGN(dxva->width, 8) - dxva->width; in vdpu_av1d_set_picture_dimensions()
1221 regs->swreg12.sw_pic_height_pad = MPP_ALIGN(dxva->height, 8) - dxva->height; in vdpu_av1d_set_picture_dimensions()
1223 regs->swreg8.sw_superres_pic_width = dxva->upscaled_width; in vdpu_av1d_set_picture_dimensions()
1224 regs->swreg9.sw_scale_denom_minus9 = dxva->superres_denom; in vdpu_av1d_set_picture_dimensions()
1232 VdpuAv1dRegSet *regs = ctx->regs; in vdpu_av1d_set_segmentation() local
1238 regs->swreg13.sw_segment_temp_upd_e = dxva->segmentation.temporal_update; in vdpu_av1d_set_segmentation()
1239 regs->swreg13.sw_segment_upd_e = dxva->segmentation.update_map; in vdpu_av1d_set_segmentation()
1240 regs->swreg13.sw_segment_e = dxva->segmentation.enabled; in vdpu_av1d_set_segmentation()
1243 regs->swreg5.sw_error_resilient = dxva->coding.error_resilient_mode; in vdpu_av1d_set_segmentation()
1246 || regs->swreg5.sw_error_resilient) { in vdpu_av1d_set_segmentation()
1247 regs->swreg11.sw_use_temporal3_mvs = 0; in vdpu_av1d_set_segmentation()
1250 regs->swreg14.sw_filt_level0 = dxva->loop_filter.filter_level[0]; in vdpu_av1d_set_segmentation()
1251 regs->swreg15.sw_filt_level1 = dxva->loop_filter.filter_level[1]; in vdpu_av1d_set_segmentation()
1252 regs->swreg16.sw_filt_level2 = dxva->loop_filter.filter_level_u; in vdpu_av1d_set_segmentation()
1253 regs->swreg17.sw_filt_level3 = dxva->loop_filter.filter_level_v; in vdpu_av1d_set_segmentation()
1315 regs->swreg9.sw_last_active_seg = last_active_seg; in vdpu_av1d_set_segmentation()
1316 regs->swreg5.sw_preskip_segid = preskip_segid; in vdpu_av1d_set_segmentation()
1318 regs->swreg12.sw_seg_quant_sign = segsign; in vdpu_av1d_set_segmentation()
1320 regs->swreg14.sw_quant_seg0 = segval[0][SEG_AV1_LVL_ALT_Q]; in vdpu_av1d_set_segmentation()
1321 regs->swreg14.sw_filt_level_delta0_seg0 = segval[0][SEG_AV1_LVL_ALT_LF_Y_V]; in vdpu_av1d_set_segmentation()
1322 regs->swreg20.sw_filt_level_delta1_seg0 = segval[0][SEG_AV1_LVL_ALT_LF_Y_H]; in vdpu_av1d_set_segmentation()
1323 regs->swreg20.sw_filt_level_delta2_seg0 = segval[0][SEG_AV1_LVL_ALT_LF_U]; in vdpu_av1d_set_segmentation()
1324 regs->swreg20.sw_filt_level_delta3_seg0 = segval[0][SEG_AV1_LVL_ALT_LF_V]; in vdpu_av1d_set_segmentation()
1325 regs->swreg14.sw_refpic_seg0 = segval[0][SEG_AV1_LVL_REF_FRAME]; in vdpu_av1d_set_segmentation()
1326 regs->swreg14.sw_skip_seg0 = segval[0][SEG_AV1_LVL_SKIP]; in vdpu_av1d_set_segmentation()
1327 regs->swreg20.sw_global_mv_seg0 = segval[0][SEG_AV1_LVL_GLOBALMV]; in vdpu_av1d_set_segmentation()
1329 regs->swreg15.sw_quant_seg1 = segval[1][SEG_AV1_LVL_ALT_Q]; in vdpu_av1d_set_segmentation()
1330 regs->swreg15.sw_filt_level_delta0_seg1 = segval[1][SEG_AV1_LVL_ALT_LF_Y_V]; in vdpu_av1d_set_segmentation()
1331 regs->swreg21.sw_filt_level_delta1_seg1 = segval[1][SEG_AV1_LVL_ALT_LF_Y_H]; in vdpu_av1d_set_segmentation()
1332 regs->swreg21.sw_filt_level_delta2_seg1 = segval[1][SEG_AV1_LVL_ALT_LF_U]; in vdpu_av1d_set_segmentation()
1333 regs->swreg21.sw_filt_level_delta3_seg1 = segval[1][SEG_AV1_LVL_ALT_LF_V]; in vdpu_av1d_set_segmentation()
1334 regs->swreg15.sw_refpic_seg1 = segval[1][SEG_AV1_LVL_REF_FRAME]; in vdpu_av1d_set_segmentation()
1335 regs->swreg15.sw_skip_seg1 = segval[1][SEG_AV1_LVL_SKIP]; in vdpu_av1d_set_segmentation()
1336 regs->swreg21.sw_global_mv_seg1 = segval[1][SEG_AV1_LVL_GLOBALMV]; in vdpu_av1d_set_segmentation()
1338 regs->swreg16.sw_quant_seg2 = segval[2][SEG_AV1_LVL_ALT_Q]; in vdpu_av1d_set_segmentation()
1339 regs->swreg16.sw_filt_level_delta0_seg2 = segval[2][SEG_AV1_LVL_ALT_LF_Y_V]; in vdpu_av1d_set_segmentation()
1340 regs->swreg22.sw_filt_level_delta1_seg2 = segval[2][SEG_AV1_LVL_ALT_LF_Y_H]; in vdpu_av1d_set_segmentation()
1341 regs->swreg22.sw_filt_level_delta2_seg2 = segval[2][SEG_AV1_LVL_ALT_LF_U]; in vdpu_av1d_set_segmentation()
1342 regs->swreg22.sw_filt_level_delta3_seg2 = segval[2][SEG_AV1_LVL_ALT_LF_V]; in vdpu_av1d_set_segmentation()
1343 regs->swreg16.sw_refpic_seg2 = segval[2][SEG_AV1_LVL_REF_FRAME]; in vdpu_av1d_set_segmentation()
1344 regs->swreg16.sw_skip_seg2 = segval[2][SEG_AV1_LVL_SKIP]; in vdpu_av1d_set_segmentation()
1345 regs->swreg22.sw_global_mv_seg2 = segval[2][SEG_AV1_LVL_GLOBALMV]; in vdpu_av1d_set_segmentation()
1347 regs->swreg17.sw_quant_seg3 = segval[3][SEG_AV1_LVL_ALT_Q]; in vdpu_av1d_set_segmentation()
1348 regs->swreg17.sw_filt_level_delta0_seg3 = segval[3][SEG_AV1_LVL_ALT_LF_Y_V]; in vdpu_av1d_set_segmentation()
1349 regs->swreg23.sw_filt_level_delta1_seg3 = segval[3][SEG_AV1_LVL_ALT_LF_Y_H]; in vdpu_av1d_set_segmentation()
1350 regs->swreg23.sw_filt_level_delta2_seg3 = segval[3][SEG_AV1_LVL_ALT_LF_U]; in vdpu_av1d_set_segmentation()
1351 regs->swreg23.sw_filt_level_delta3_seg3 = segval[3][SEG_AV1_LVL_ALT_LF_V]; in vdpu_av1d_set_segmentation()
1352 regs->swreg17.sw_refpic_seg3 = segval[3][SEG_AV1_LVL_REF_FRAME]; in vdpu_av1d_set_segmentation()
1353 regs->swreg17.sw_skip_seg3 = segval[3][SEG_AV1_LVL_SKIP]; in vdpu_av1d_set_segmentation()
1354 regs->swreg23.sw_global_mv_seg3 = segval[3][SEG_AV1_LVL_GLOBALMV]; in vdpu_av1d_set_segmentation()
1356 regs->swreg18.sw_quant_seg4 = segval[4][SEG_AV1_LVL_ALT_Q]; in vdpu_av1d_set_segmentation()
1357 regs->swreg18.sw_filt_level_delta0_seg4 = segval[4][SEG_AV1_LVL_ALT_LF_Y_V]; in vdpu_av1d_set_segmentation()
1358 regs->swreg24.sw_filt_level_delta1_seg4 = segval[4][SEG_AV1_LVL_ALT_LF_Y_H]; in vdpu_av1d_set_segmentation()
1359 regs->swreg24.sw_filt_level_delta2_seg4 = segval[4][SEG_AV1_LVL_ALT_LF_U]; in vdpu_av1d_set_segmentation()
1360 regs->swreg24.sw_filt_level_delta3_seg4 = segval[4][SEG_AV1_LVL_ALT_LF_V]; in vdpu_av1d_set_segmentation()
1361 regs->swreg18.sw_refpic_seg4 = segval[4][SEG_AV1_LVL_REF_FRAME]; in vdpu_av1d_set_segmentation()
1362 regs->swreg18.sw_skip_seg4 = segval[4][SEG_AV1_LVL_SKIP]; in vdpu_av1d_set_segmentation()
1363 regs->swreg24.sw_global_mv_seg4 = segval[4][SEG_AV1_LVL_GLOBALMV]; in vdpu_av1d_set_segmentation()
1365 regs->swreg19.sw_quant_seg5 = segval[5][SEG_AV1_LVL_ALT_Q]; in vdpu_av1d_set_segmentation()
1366 regs->swreg19.sw_filt_level_delta0_seg5 = segval[5][SEG_AV1_LVL_ALT_LF_Y_V]; in vdpu_av1d_set_segmentation()
1367 regs->swreg25.sw_filt_level_delta1_seg5 = segval[5][SEG_AV1_LVL_ALT_LF_Y_H]; in vdpu_av1d_set_segmentation()
1368 regs->swreg25.sw_filt_level_delta2_seg5 = segval[5][SEG_AV1_LVL_ALT_LF_U]; in vdpu_av1d_set_segmentation()
1369 regs->swreg25.sw_filt_level_delta3_seg5 = segval[5][SEG_AV1_LVL_ALT_LF_V]; in vdpu_av1d_set_segmentation()
1370 regs->swreg19.sw_refpic_seg5 = segval[5][SEG_AV1_LVL_REF_FRAME]; in vdpu_av1d_set_segmentation()
1371 regs->swreg19.sw_skip_seg5 = segval[5][SEG_AV1_LVL_SKIP]; in vdpu_av1d_set_segmentation()
1372 regs->swreg25.sw_global_mv_seg5 = segval[5][SEG_AV1_LVL_GLOBALMV]; in vdpu_av1d_set_segmentation()
1374 regs->swreg31.sw_quant_seg6 = segval[6][SEG_AV1_LVL_ALT_Q]; in vdpu_av1d_set_segmentation()
1375 regs->swreg31.sw_filt_level_delta0_seg6 = segval[6][SEG_AV1_LVL_ALT_LF_Y_V]; in vdpu_av1d_set_segmentation()
1376 regs->swreg26.sw_filt_level_delta1_seg6 = segval[6][SEG_AV1_LVL_ALT_LF_Y_H]; in vdpu_av1d_set_segmentation()
1377 regs->swreg26.sw_filt_level_delta2_seg6 = segval[6][SEG_AV1_LVL_ALT_LF_U]; in vdpu_av1d_set_segmentation()
1378 regs->swreg26.sw_filt_level_delta3_seg6 = segval[6][SEG_AV1_LVL_ALT_LF_V]; in vdpu_av1d_set_segmentation()
1379 regs->swreg31.sw_refpic_seg6 = segval[6][SEG_AV1_LVL_REF_FRAME]; in vdpu_av1d_set_segmentation()
1380 regs->swreg31.sw_skip_seg6 = segval[6][SEG_AV1_LVL_SKIP]; in vdpu_av1d_set_segmentation()
1381 regs->swreg26.sw_global_mv_seg6 = segval[6][SEG_AV1_LVL_GLOBALMV]; in vdpu_av1d_set_segmentation()
1383 regs->swreg32.sw_quant_seg7 = segval[7][SEG_AV1_LVL_ALT_Q]; in vdpu_av1d_set_segmentation()
1384 regs->swreg32.sw_filt_level_delta0_seg7 = segval[7][SEG_AV1_LVL_ALT_LF_Y_V]; in vdpu_av1d_set_segmentation()
1385 regs->swreg27.sw_filt_level_delta1_seg7 = segval[7][SEG_AV1_LVL_ALT_LF_Y_H]; in vdpu_av1d_set_segmentation()
1386 regs->swreg27.sw_filt_level_delta2_seg7 = segval[7][SEG_AV1_LVL_ALT_LF_U]; in vdpu_av1d_set_segmentation()
1387 regs->swreg27.sw_filt_level_delta3_seg7 = segval[7][SEG_AV1_LVL_ALT_LF_V]; in vdpu_av1d_set_segmentation()
1388 regs->swreg32.sw_refpic_seg7 = segval[7][SEG_AV1_LVL_REF_FRAME]; in vdpu_av1d_set_segmentation()
1389 regs->swreg32.sw_skip_seg7 = segval[7][SEG_AV1_LVL_SKIP]; in vdpu_av1d_set_segmentation()
1390 regs->swreg27.sw_global_mv_seg7 = segval[7][SEG_AV1_LVL_GLOBALMV]; in vdpu_av1d_set_segmentation()
1396 VdpuAv1dRegSet *regs = ctx->regs; in vdpu_av1d_set_loopfilter() local
1397 …regs->swreg3.sw_filtering_dis = (dxva->loop_filter.filter_level[0] == 0) && (dxva->loop_filte… in vdpu_av1d_set_loopfilter()
1398 regs->swreg5.sw_filt_level_base_gt32 = dxva->loop_filter.filter_level[0] > 32; in vdpu_av1d_set_loopfilter()
1399 regs->swreg30.sw_filt_sharpness = dxva->loop_filter.sharpness_level; in vdpu_av1d_set_loopfilter()
1401 regs->swreg59.sw_filt_ref_adj_0 = dxva->loop_filter.ref_deltas[0]; in vdpu_av1d_set_loopfilter()
1402 regs->swreg59.sw_filt_ref_adj_1 = dxva->loop_filter.ref_deltas[1]; in vdpu_av1d_set_loopfilter()
1403 regs->swreg59.sw_filt_ref_adj_2 = dxva->loop_filter.ref_deltas[2]; in vdpu_av1d_set_loopfilter()
1404 regs->swreg59.sw_filt_ref_adj_3 = dxva->loop_filter.ref_deltas[3]; in vdpu_av1d_set_loopfilter()
1405 regs->swreg30.sw_filt_ref_adj_4 = dxva->loop_filter.ref_deltas[4]; in vdpu_av1d_set_loopfilter()
1406 regs->swreg30.sw_filt_ref_adj_5 = dxva->loop_filter.ref_deltas[5]; in vdpu_av1d_set_loopfilter()
1407 regs->swreg49.sw_filt_ref_adj_7 = dxva->loop_filter.ref_deltas[6]; in vdpu_av1d_set_loopfilter()
1408 regs->swreg49.sw_filt_ref_adj_6 = dxva->loop_filter.ref_deltas[7]; in vdpu_av1d_set_loopfilter()
1409 regs->swreg30.sw_filt_mb_adj_0 = dxva->loop_filter.mode_deltas[0]; in vdpu_av1d_set_loopfilter()
1410 regs->swreg30.sw_filt_mb_adj_1 = dxva->loop_filter.mode_deltas[1]; in vdpu_av1d_set_loopfilter()
1412 regs->swreg59.sw_filt_ref_adj_0 = 0; in vdpu_av1d_set_loopfilter()
1413 regs->swreg59.sw_filt_ref_adj_1 = 0; in vdpu_av1d_set_loopfilter()
1414 regs->swreg59.sw_filt_ref_adj_2 = 0; in vdpu_av1d_set_loopfilter()
1415 regs->swreg59.sw_filt_ref_adj_3 = 0; in vdpu_av1d_set_loopfilter()
1416 regs->swreg30.sw_filt_ref_adj_4 = 0; in vdpu_av1d_set_loopfilter()
1417 regs->swreg30.sw_filt_ref_adj_5 = 0; in vdpu_av1d_set_loopfilter()
1418 regs->swreg49.sw_filt_ref_adj_7 = 0; in vdpu_av1d_set_loopfilter()
1419 regs->swreg49.sw_filt_ref_adj_6 = 0; in vdpu_av1d_set_loopfilter()
1420 regs->swreg30.sw_filt_mb_adj_0 = 0; in vdpu_av1d_set_loopfilter()
1421 regs->swreg30.sw_filt_mb_adj_1 = 0; in vdpu_av1d_set_loopfilter()
1424 regs->addr_cfg.swreg179.sw_dec_vert_filt_base_lsb = mpp_buffer_get_fd(ctx->filter_mem); in vdpu_av1d_set_loopfilter()
1425 regs->addr_cfg.swreg183.sw_dec_bsd_ctrl_base_lsb = mpp_buffer_get_fd(ctx->filter_mem); in vdpu_av1d_set_loopfilter()
1432 VdpuAv1dRegSet *regs = ctx->regs; in vdpu_av1d_set_global_model() local
1467 regs->addr_cfg.swreg82.sw_global_model_base_msb = 0; in vdpu_av1d_set_global_model()
1468 regs->addr_cfg.swreg83.sw_global_model_base_lsb = mpp_buffer_get_fd(ctx->global_model); in vdpu_av1d_set_global_model()
1474 VdpuAv1dRegSet *regs = ctx->regs; in vdpu_av1d_set_tile_info_regs() local
1479 regs->swreg11.sw_multicore_expect_context_update = (0 == context_update_x); in vdpu_av1d_set_tile_info_regs()
1484 regs->swreg10.sw_tile_enable = (dxva->tiles.cols > 1) || (dxva->tiles.rows > 1); in vdpu_av1d_set_tile_info_regs()
1485 regs->swreg10.sw_num_tile_cols_8k = dxva->tiles.cols; in vdpu_av1d_set_tile_info_regs()
1486 regs->swreg10.sw_num_tile_rows_8k_av1 = dxva->tiles.rows; in vdpu_av1d_set_tile_info_regs()
1487 regs->swreg9.sw_context_update_tile_id = context_update_tile_id; in vdpu_av1d_set_tile_info_regs()
1488 regs->swreg10.sw_tile_transpose = transpose; in vdpu_av1d_set_tile_info_regs()
1489 regs->swreg11.sw_dec_tile_size_mag = dxva->tiles.tile_sz_mag; in vdpu_av1d_set_tile_info_regs()
1490 if (regs->swreg10.sw_tile_enable) AV1D_DBG(AV1D_DBG_LOG, "NOTICE: tile enabled.\n"); in vdpu_av1d_set_tile_info_regs()
1492 regs->addr_cfg.swreg167.sw_tile_base_lsb = mpp_buffer_get_fd(ctx->tile_info);// in vdpu_av1d_set_tile_info_regs()
1493 regs->addr_cfg.swreg166.sw_tile_base_msb = 0; in vdpu_av1d_set_tile_info_regs()
1617 VdpuAv1dRegSet *regs = ctx->regs; in vdpu_av1d_set_cdef() local
1621 regs->swreg7.sw_cdef_bits = dxva->cdef.bits; in vdpu_av1d_set_cdef()
1622 regs->swreg7.sw_cdef_damping = dxva->cdef.damping; in vdpu_av1d_set_cdef()
1632 regs->swreg263.sw_cdef_luma_primary_strength = luma_pri_strength; in vdpu_av1d_set_cdef()
1633 regs->swreg53.sw_cdef_luma_secondary_strength = luma_sec_strength; in vdpu_av1d_set_cdef()
1634 regs->swreg264.sw_cdef_chroma_primary_strength = chroma_pri_strength; in vdpu_av1d_set_cdef()
1635 regs->swreg53.sw_cdef_chroma_secondary_strength = chroma_sec_strength; in vdpu_av1d_set_cdef()
1638 regs->addr_cfg.swreg85.sw_cdef_colbuf_base_lsb = mpp_buffer_get_fd(ctx->filter_mem); in vdpu_av1d_set_cdef()
1645 VdpuAv1dRegSet *regs = ctx->regs; in vdpu_av1d_set_lr() local
1654 regs->swreg18.sw_lr_type = lr_type; in vdpu_av1d_set_lr()
1655 regs->swreg19.sw_lr_unit_size = lr_unit_size; in vdpu_av1d_set_lr()
1656 regs->addr_cfg.swreg91.sw_lr_colbuf_base_lsb = mpp_buffer_get_fd(ctx->filter_mem); in vdpu_av1d_set_lr()
1691 VdpuAv1dRegSet *regs = ctx->regs; in vdpu_av1d_set_fgs() local
1708 regs->swreg7.sw_apply_grain = 0; in vdpu_av1d_set_fgs()
1725 regs->swreg7.sw_num_y_points_b = dxva->film_grain.num_y_points > 0; in vdpu_av1d_set_fgs()
1726 regs->swreg7.sw_num_cb_points_b = dxva->film_grain.num_cb_points > 0; in vdpu_av1d_set_fgs()
1727 regs->swreg7.sw_num_cr_points_b = dxva->film_grain.num_cr_points > 0; in vdpu_av1d_set_fgs()
1728 regs->swreg8.sw_scaling_shift = dxva->film_grain.scaling_shift_minus8 + 8; in vdpu_av1d_set_fgs()
1730 regs->swreg28.sw_cb_mult = dxva->film_grain.cb_mult - 128; in vdpu_av1d_set_fgs()
1731 regs->swreg28.sw_cb_luma_mult = dxva->film_grain.cb_luma_mult - 128; in vdpu_av1d_set_fgs()
1732 regs->swreg28.sw_cb_offset = dxva->film_grain.cb_offset - 256; in vdpu_av1d_set_fgs()
1733 regs->swreg29.sw_cr_mult = dxva->film_grain.cr_mult - 128; in vdpu_av1d_set_fgs()
1734 regs->swreg29.sw_cr_luma_mult = dxva->film_grain.cr_luma_mult - 128; in vdpu_av1d_set_fgs()
1735 regs->swreg29.sw_cr_offset = dxva->film_grain.cr_offset - 256; in vdpu_av1d_set_fgs()
1737 regs->swreg28.sw_cb_mult = 0; in vdpu_av1d_set_fgs()
1738 regs->swreg28.sw_cb_luma_mult = 64; in vdpu_av1d_set_fgs()
1739 regs->swreg28.sw_cb_offset = 0; in vdpu_av1d_set_fgs()
1740 regs->swreg29.sw_cr_mult = 0; in vdpu_av1d_set_fgs()
1741 regs->swreg29.sw_cr_luma_mult = 64; in vdpu_av1d_set_fgs()
1742 regs->swreg29.sw_cr_offset = 0; in vdpu_av1d_set_fgs()
1744 regs->swreg7.sw_overlap_flag = dxva->film_grain.overlap_flag; in vdpu_av1d_set_fgs()
1745 regs->swreg7.sw_clip_to_restricted_range = dxva->film_grain.clip_to_restricted_range; in vdpu_av1d_set_fgs()
1746 regs->swreg7.sw_chroma_scaling_from_luma = dxva->film_grain.chroma_scaling_from_luma; in vdpu_av1d_set_fgs()
1747 regs->swreg7.sw_random_seed = dxva->film_grain.grain_seed; in vdpu_av1d_set_fgs()
1812 regs->addr_cfg.swreg94.sw_filmgrain_base_msb = 0; in vdpu_av1d_set_fgs()
1813 regs->addr_cfg.swreg95.sw_filmgrain_base_lsb = mpp_buffer_get_fd(ctx->film_grain_mem); in vdpu_av1d_set_fgs()
1815 if (regs->swreg7.sw_apply_grain) AV1D_DBG(AV1D_DBG_LOG, "NOTICE: filmgrain enabled.\n"); in vdpu_av1d_set_fgs()
1858 VdpuAv1dRegSet *regs; in vdpu_av1d_gen_regs() local
1887 ctx->regs = ctx->reg_buf[i].regs; in vdpu_av1d_gen_regs()
1894 regs = ctx->regs; in vdpu_av1d_gen_regs()
1895 memset(regs, 0, sizeof(*regs)); in vdpu_av1d_gen_regs()
1931 regs->swreg1.sw_dec_abort_e = 0; in vdpu_av1d_gen_regs()
1932 regs->swreg1.sw_dec_e = 1; in vdpu_av1d_gen_regs()
1933 regs->swreg1.sw_dec_tile_int_e = 0; in vdpu_av1d_gen_regs()
1934 regs->swreg2.sw_dec_clk_gate_e = 1; in vdpu_av1d_gen_regs()
1936 regs->swreg3.sw_dec_mode = 17; // av1 mode in vdpu_av1d_gen_regs()
1937 regs->swreg3.sw_skip_mode = dxva->coding.skip_mode; in vdpu_av1d_gen_regs()
1938 regs->swreg3.sw_dec_out_ec_byte_word = 0; // word align in vdpu_av1d_gen_regs()
1939 regs->swreg3.sw_write_mvs_e = 1; in vdpu_av1d_gen_regs()
1940 regs->swreg3.sw_dec_out_ec_bypass = 1; in vdpu_av1d_gen_regs()
1942 regs->swreg5.sw_tempor_mvp_e = dxva->coding.use_ref_frame_mvs; in vdpu_av1d_gen_regs()
1943 regs->swreg5.sw_delta_lf_res_log = dxva->loop_filter.delta_lf_res; in vdpu_av1d_gen_regs()
1944 regs->swreg5.sw_delta_lf_multi = dxva->loop_filter.delta_lf_multi; in vdpu_av1d_gen_regs()
1945 regs->swreg5.sw_delta_lf_present = dxva->loop_filter.delta_lf_present; in vdpu_av1d_gen_regs()
1946 regs->swreg5.sw_disable_cdf_update = dxva->coding.disable_cdf_update; in vdpu_av1d_gen_regs()
1947 regs->swreg5.sw_allow_warp = dxva->coding.warped_motion; in vdpu_av1d_gen_regs()
1948 regs->swreg5.sw_show_frame = dxva->format.show_frame; in vdpu_av1d_gen_regs()
1949 regs->swreg5.sw_switchable_motion_mode = dxva->coding.switchable_motion_mode; in vdpu_av1d_gen_regs()
1950 regs->swreg5.sw_enable_cdef = !(dxva->cdef.bits == 0 && dxva->cdef.damping == 0 && in vdpu_av1d_gen_regs()
1955 regs->swreg5.sw_allow_masked_compound = dxva->coding.masked_compound; in vdpu_av1d_gen_regs()
1956 regs->swreg5.sw_allow_interintra = dxva->coding.interintra_compound; in vdpu_av1d_gen_regs()
1957 regs->swreg5.sw_enable_intra_edge_filter = dxva->coding.intra_edge_filter; in vdpu_av1d_gen_regs()
1958 regs->swreg5.sw_allow_filter_intra = dxva->coding.filter_intra; in vdpu_av1d_gen_regs()
1959 regs->swreg5.sw_enable_jnt_comp = dxva->coding.jnt_comp; in vdpu_av1d_gen_regs()
1960 regs->swreg5.sw_enable_dual_filter = dxva->coding.dual_filter; in vdpu_av1d_gen_regs()
1961 regs->swreg5.sw_reduced_tx_set_used = dxva->coding.reduced_tx_set; in vdpu_av1d_gen_regs()
1962 regs->swreg5.sw_allow_screen_content_tools = dxva->coding.screen_content_tools; in vdpu_av1d_gen_regs()
1963 regs->swreg5.sw_allow_intrabc = dxva->coding.intrabc; in vdpu_av1d_gen_regs()
1965 regs->swreg5.sw_force_interger_mv = dxva->coding.integer_mv; in vdpu_av1d_gen_regs()
2056 regs->swreg7.sw_blackwhite_e = dxva->format.mono_chrome; in vdpu_av1d_gen_regs()
2057 regs->swreg7.sw_clip_to_restricted_range = dxva->film_grain.clip_to_restricted_range; in vdpu_av1d_gen_regs()
2058 regs->swreg7.sw_delta_q_res_log = dxva->quantization.delta_q_res; in vdpu_av1d_gen_regs()
2059 regs->swreg7.sw_delta_q_present = dxva->quantization.delta_q_present; in vdpu_av1d_gen_regs()
2061 regs->swreg8.sw_idr_pic_e = dxva->format.frame_type == AV1_FRAME_KEY || in vdpu_av1d_gen_regs()
2063 regs->swreg8.sw_quant_base_qindex = dxva->quantization.base_qindex; in vdpu_av1d_gen_regs()
2064 regs->swreg8.sw_bit_depth_y_minus8 = dxva->bitdepth - 8; in vdpu_av1d_gen_regs()
2065 regs->swreg8.sw_bit_depth_c_minus8 = dxva->bitdepth - 8; in vdpu_av1d_gen_regs()
2067 regs->swreg11.sw_mcomp_filt_type = dxva->interp_filter; in vdpu_av1d_gen_regs()
2068 regs->swreg11.sw_high_prec_mv_e = dxva->coding.high_precision_mv; in vdpu_av1d_gen_regs()
2069 regs->swreg11.sw_comp_pred_mode = dxva->coding.reference_mode ? 2 : 0; in vdpu_av1d_gen_regs()
2070 regs->swreg11.sw_transform_mode = dxva->coding.tx_mode ? (dxva->coding.tx_mode + 2) : 0; in vdpu_av1d_gen_regs()
2071 regs->swreg12.sw_max_cb_size = dxva->coding.use_128x128_superblock ? 7 : 6;; in vdpu_av1d_gen_regs()
2072 regs->swreg12.sw_min_cb_size = 3; in vdpu_av1d_gen_regs()
2075 regs->swreg12.sw_av1_comp_pred_fixed_ref = 0; in vdpu_av1d_gen_regs()
2076 regs->swreg13.sw_comp_pred_var_ref0_av1 = 0; in vdpu_av1d_gen_regs()
2077 regs->swreg13.sw_comp_pred_var_ref1_av1 = 0; in vdpu_av1d_gen_regs()
2078 regs->swreg14.sw_filt_level_seg0 = 0; in vdpu_av1d_gen_regs()
2079 regs->swreg15.sw_filt_level_seg1 = 0; in vdpu_av1d_gen_regs()
2080 regs->swreg16.sw_filt_level_seg2 = 0; in vdpu_av1d_gen_regs()
2081 regs->swreg17.sw_filt_level_seg3 = 0; in vdpu_av1d_gen_regs()
2082 regs->swreg18.sw_filt_level_seg4 = 0; in vdpu_av1d_gen_regs()
2083 regs->swreg19.sw_filt_level_seg5 = 0; in vdpu_av1d_gen_regs()
2084 regs->swreg31.sw_filt_level_seg6 = 0; in vdpu_av1d_gen_regs()
2085 regs->swreg32.sw_filt_level_seg7 = 0; in vdpu_av1d_gen_regs()
2088 regs->swreg13.sw_qp_delta_y_dc_av1 = dxva->quantization.y_dc_delta_q; in vdpu_av1d_gen_regs()
2089 regs->swreg13.sw_qp_delta_ch_dc_av1 = dxva->quantization.u_dc_delta_q; in vdpu_av1d_gen_regs()
2090 regs->swreg13.sw_qp_delta_ch_ac_av1 = dxva->quantization.u_ac_delta_q; in vdpu_av1d_gen_regs()
2091 regs->swreg47.sw_qmlevel_y = dxva->quantization.qm_y; in vdpu_av1d_gen_regs()
2092 regs->swreg48.sw_qmlevel_u = dxva->quantization.qm_u; in vdpu_av1d_gen_regs()
2093 regs->swreg49.sw_qmlevel_v = dxva->quantization.qm_v; in vdpu_av1d_gen_regs()
2095 regs->swreg13.sw_lossless_e = dxva->coded_lossless; in vdpu_av1d_gen_regs()
2096 regs->swreg28.sw_quant_delta_v_dc = dxva->quantization.v_dc_delta_q; in vdpu_av1d_gen_regs()
2097 regs->swreg29.sw_quant_delta_v_ac = dxva->quantization.v_ac_delta_q; in vdpu_av1d_gen_regs()
2099 regs->swreg31.sw_skip_ref0 = dxva->skip_ref0 ? dxva->skip_ref0 : 1; in vdpu_av1d_gen_regs()
2100 regs->swreg32.sw_skip_ref1 = dxva->skip_ref1 ? dxva->skip_ref1 : 1; in vdpu_av1d_gen_regs()
2114 …regs->addr_cfg.swreg65.sw_dec_out_ybase_lsb = mpp_buffer_get_fd(tile_out_buf->buf[0]);//mpp_buffer… in vdpu_av1d_gen_regs()
2115 regs->addr_cfg.swreg99.sw_dec_out_cbase_lsb = mpp_buffer_get_fd(tile_out_buf->buf[0]); in vdpu_av1d_gen_regs()
2117 regs->addr_cfg.swreg133.sw_dec_out_dbase_lsb = mpp_buffer_get_fd(tile_out_buf->buf[0]); in vdpu_av1d_gen_regs()
2125 regs->swreg258.sw_strm_buffer_len = MPP_ALIGN(p_hal->strm_len, 128);// in vdpu_av1d_gen_regs()
2126 … regs->swreg5.sw_strm_start_bit = (dxva->frame_tag_size & 0xf) * 8; // bit start to decode in vdpu_av1d_gen_regs()
2127 regs->swreg6.sw_stream_len = MPP_ALIGN(p_hal->strm_len, 128);//p_hal->strm_len - offset; in vdpu_av1d_gen_regs()
2128 regs->swreg259.sw_strm_start_offset = 0; in vdpu_av1d_gen_regs()
2129 regs->addr_cfg.swreg168.sw_stream_base_msb = 0; in vdpu_av1d_gen_regs()
2130 regs->addr_cfg.swreg169.sw_stream_base_lsb = mpp_buffer_get_fd(streambuf); in vdpu_av1d_gen_regs()
2136 AV1D_DBG(AV1D_DBG_LOG, "stream start_bit %d\n", regs->swreg5.sw_strm_start_bit); in vdpu_av1d_gen_regs()
2138 regs->swreg314.sw_dec_alignment = 64; in vdpu_av1d_gen_regs()
2140 regs->addr_cfg.swreg175.sw_mc_sync_curr_base_lsb = mpp_buffer_get_fd(ctx->tile_buf); in vdpu_av1d_gen_regs()
2141 regs->addr_cfg.swreg177.sw_mc_sync_left_base_lsb = mpp_buffer_get_fd(ctx->tile_buf); in vdpu_av1d_gen_regs()
2143 regs->swreg55.sw_apf_disable = 0; in vdpu_av1d_gen_regs()
2144 regs->swreg55.sw_apf_threshold = 8; in vdpu_av1d_gen_regs()
2145 regs->swreg58.sw_dec_buswidth = 2; in vdpu_av1d_gen_regs()
2146 regs->swreg58.sw_dec_max_burst = 16; in vdpu_av1d_gen_regs()
2147 regs->swreg266.sw_error_conceal_e = 0; in vdpu_av1d_gen_regs()
2148 regs->swreg265.sw_axi_rd_ostd_threshold = 64; in vdpu_av1d_gen_regs()
2149 regs->swreg265.sw_axi_wr_ostd_threshold = 64; in vdpu_av1d_gen_regs()
2151 regs->swreg318.sw_ext_timeout_cycles = 0xfffffff; in vdpu_av1d_gen_regs()
2152 regs->swreg318.sw_ext_timeout_override_e = 1; in vdpu_av1d_gen_regs()
2153 regs->swreg319.sw_timeout_cycles = 0xfffffff; in vdpu_av1d_gen_regs()
2154 regs->swreg319.sw_timeout_override_e = 1; in vdpu_av1d_gen_regs()
2157 regs->vdpu_av1d_pp_cfg.swreg320.sw_pp_out_e = 1; in vdpu_av1d_gen_regs()
2158 regs->vdpu_av1d_pp_cfg.swreg322.sw_pp_in_format = 0; in vdpu_av1d_gen_regs()
2159 regs->vdpu_av1d_pp_cfg.swreg394.sw_pp0_dup_hor = 1; in vdpu_av1d_gen_regs()
2160 regs->vdpu_av1d_pp_cfg.swreg394.sw_pp0_dup_ver = 1; in vdpu_av1d_gen_regs()
2161 regs->vdpu_av1d_pp_cfg.swreg331.sw_pp_in_height = height / 2; in vdpu_av1d_gen_regs()
2162 regs->vdpu_av1d_pp_cfg.swreg331.sw_pp_in_width = width / 2; in vdpu_av1d_gen_regs()
2163 regs->vdpu_av1d_pp_cfg.swreg332.sw_pp_out_height = height; in vdpu_av1d_gen_regs()
2164 regs->vdpu_av1d_pp_cfg.swreg332.sw_pp_out_width = width; in vdpu_av1d_gen_regs()
2165 regs->vdpu_av1d_pp_cfg.swreg329.sw_pp_out_y_stride = hor_stride; in vdpu_av1d_gen_regs()
2166 regs->vdpu_av1d_pp_cfg.swreg329.sw_pp_out_c_stride = hor_stride; in vdpu_av1d_gen_regs()
2172 RK_U32 bypass_filter = !regs->swreg5.sw_superres_is_scaled && in vdpu_av1d_gen_regs()
2173 !regs->swreg5.sw_enable_cdef && in vdpu_av1d_gen_regs()
2174 !regs->swreg14.sw_filt_level0 && in vdpu_av1d_gen_regs()
2175 !regs->swreg15.sw_filt_level1 && in vdpu_av1d_gen_regs()
2176 !regs->swreg18.sw_lr_type; in vdpu_av1d_gen_regs()
2178 regs->vdpu_av1d_pp_cfg.swreg329.sw_pp_out_y_stride = dxva->bitdepth > 8 ? in vdpu_av1d_gen_regs()
2180 regs->vdpu_av1d_pp_cfg.swreg329.sw_pp_out_c_stride = dxva->bitdepth > 8 ? in vdpu_av1d_gen_regs()
2182 regs->swreg58.sw_dec_axi_wd_id_e = 1; in vdpu_av1d_gen_regs()
2183 regs->swreg58.sw_dec_axi_rd_id_e = 1; in vdpu_av1d_gen_regs()
2184 regs->vdpu_av1d_pp_cfg.swreg320.sw_pp_out_tile_e = 1; in vdpu_av1d_gen_regs()
2185 regs->vdpu_av1d_pp_cfg.swreg321.sw_pp_tile_size = 2; in vdpu_av1d_gen_regs()
2203 regs->vdpu_av1d_pp_cfg.swreg503.sw_pp0_virtual_top = vir_top; in vdpu_av1d_gen_regs()
2204 regs->vdpu_av1d_pp_cfg.swreg503.sw_pp0_virtual_left = vir_left; in vdpu_av1d_gen_regs()
2205 regs->vdpu_av1d_pp_cfg.swreg503.sw_pp0_virtual_bottom = vir_bottom; in vdpu_av1d_gen_regs()
2206 regs->vdpu_av1d_pp_cfg.swreg503.sw_pp0_virtual_right = vir_right; in vdpu_av1d_gen_regs()
2209 regs->vdpu_av1d_pp_cfg.swreg322.sw_pp_out_format = 0; in vdpu_av1d_gen_regs()
2210 regs->vdpu_av1d_pp_cfg.swreg326.sw_pp_out_lu_base_lsb = mpp_buffer_get_fd(buffer); in vdpu_av1d_gen_regs()
2211 regs->vdpu_av1d_pp_cfg.swreg328.sw_pp_out_ch_base_lsb = mpp_buffer_get_fd(buffer); in vdpu_av1d_gen_regs()
2212 regs->vdpu_av1d_pp_cfg.swreg505.sw_pp0_afbc_tile_base_lsb = mpp_buffer_get_fd(buffer); in vdpu_av1d_gen_regs()
2227 regs->vdpu_av1d_pp_cfg.swreg322.sw_pp_out_format = out_fmt; in vdpu_av1d_gen_regs()
2228 regs->vdpu_av1d_pp_cfg.swreg326.sw_pp_out_lu_base_lsb = mpp_buffer_get_fd(buffer); in vdpu_av1d_gen_regs()
2229 regs->vdpu_av1d_pp_cfg.swreg328.sw_pp_out_ch_base_lsb = mpp_buffer_get_fd(buffer); in vdpu_av1d_gen_regs()
2248 VdpuAv1dRegSet *regs = p_hal->fast_mode ? in vdpu_av1d_start() local
2249 reg_ctx->reg_buf[task->dec.reg_index].regs : in vdpu_av1d_start()
2250 reg_ctx->regs; in vdpu_av1d_start()
2255 RK_U32 *p = (RK_U32*)regs; in vdpu_av1d_start()
2262 for (i = 0; i < sizeof(*regs) / 4; i++, p++) in vdpu_av1d_start()
2273 wr_cfg.reg = regs; in vdpu_av1d_start()
2274 wr_cfg.size = sizeof(*regs); in vdpu_av1d_start()
2282 rd_cfg.reg = regs; in vdpu_av1d_start()
2283 rd_cfg.size = sizeof(*regs); in vdpu_av1d_start()
2311 reg_ctx->reg_buf[task->dec.reg_index].regs : in vdpu_av1d_wait()
2312 reg_ctx->regs; in vdpu_av1d_wait()
2347 m_ctx.regs = (RK_U32 *)prob_out; in vdpu_av1d_wait()