Lines Matching refs:regs
34 Vpu2H263dRegSet_t *regs = (Vpu2H263dRegSet_t*)ctx->regs; in vpu2_h263d_setup_regs_by_syntax() local
61 regs->reg120.sw_pic_mb_width = (pp->vop_width + 15) >> 4; in vpu2_h263d_setup_regs_by_syntax()
62 regs->reg120.sw_pic_mb_hight_p = (pp->vop_height + 15) >> 4; in vpu2_h263d_setup_regs_by_syntax()
63 regs->reg120.sw_mb_width_off = pp->vop_width & 0xf; in vpu2_h263d_setup_regs_by_syntax()
64 regs->reg120.sw_mb_height_off = pp->vop_height & 0xf; in vpu2_h263d_setup_regs_by_syntax()
66 regs->reg53_dec_mode = 2; in vpu2_h263d_setup_regs_by_syntax()
67 regs->reg50_dec_ctrl.sw_filtering_dis = 1; in vpu2_h263d_setup_regs_by_syntax()
68 regs->reg136.sw_rounding = 0; in vpu2_h263d_setup_regs_by_syntax()
69 regs->reg51_stream_info.sw_init_qp = pp->vop_quant; in vpu2_h263d_setup_regs_by_syntax()
70 regs->reg122.sw_sync_markers_en = 1; in vpu2_h263d_setup_regs_by_syntax()
79 RK_U32 val = regs->reg64_input_stream_base; in vpu2_h263d_setup_regs_by_syntax()
88 regs->reg64_input_stream_base = val; in vpu2_h263d_setup_regs_by_syntax()
89 regs->reg122.sw_stream_start_word = start_bit_offset; in vpu2_h263d_setup_regs_by_syntax()
90 regs->reg51_stream_info.sw_stream_len = left_bytes; in vpu2_h263d_setup_regs_by_syntax()
93 regs->reg122.sw_vop_time_incr = pp->vop_time_increment_resolution; in vpu2_h263d_setup_regs_by_syntax()
97 regs->reg57_enable_ctrl.sw_pic_inter_e = 1; in vpu2_h263d_setup_regs_by_syntax()
100 regs->reg131_ref0_base = (RK_U32)ctx->fd_ref0; in vpu2_h263d_setup_regs_by_syntax()
101 regs->reg148_ref1_base = (RK_U32)ctx->fd_ref0; in vpu2_h263d_setup_regs_by_syntax()
103 regs->reg131_ref0_base = (RK_U32)ctx->fd_curr; in vpu2_h263d_setup_regs_by_syntax()
104 regs->reg148_ref1_base = (RK_U32)ctx->fd_curr; in vpu2_h263d_setup_regs_by_syntax()
108 regs->reg57_enable_ctrl.sw_pic_inter_e = 0; in vpu2_h263d_setup_regs_by_syntax()
110 regs->reg131_ref0_base = (RK_U32)ctx->fd_curr; in vpu2_h263d_setup_regs_by_syntax()
111 regs->reg148_ref1_base = (RK_U32)ctx->fd_curr; in vpu2_h263d_setup_regs_by_syntax()
118 regs->reg136.sw_hrz_bit_of_fwd_mv = 1; in vpu2_h263d_setup_regs_by_syntax()
119 regs->reg136.sw_vrz_bit_of_fwd_mv = 1; in vpu2_h263d_setup_regs_by_syntax()
120 regs->reg136.sw_prev_pic_type = (pp->prev_coding_type == H263_P_VOP); in vpu2_h263d_setup_regs_by_syntax()
126 Vpu2H263dRegSet_t *regs = NULL; in hal_vpu2_h263d_init() local
131 regs = mpp_calloc(Vpu2H263dRegSet_t, 1); in hal_vpu2_h263d_init()
132 if (NULL == regs) { in hal_vpu2_h263d_init()
148 ctx->regs = (void*)regs; in hal_vpu2_h263d_init()
152 if (regs) { in hal_vpu2_h263d_init()
153 mpp_free(regs); in hal_vpu2_h263d_init()
154 regs = NULL; in hal_vpu2_h263d_init()
167 if (ctx->regs) { in hal_vpu2_h263d_deinit()
168 mpp_free(ctx->regs); in hal_vpu2_h263d_deinit()
169 ctx->regs = NULL; in hal_vpu2_h263d_deinit()
188 Vpu2H263dRegSet_t *regs = (Vpu2H263dRegSet_t*)ctx->regs; in hal_vpu2_h263d_gen_regs() local
194 memset(regs, 0, sizeof(Vpu2H263dRegSet_t)); in hal_vpu2_h263d_gen_regs()
199 regs->reg54_endian.sw_dec_out_endian = 1; in hal_vpu2_h263d_gen_regs()
200 regs->reg54_endian.sw_dec_in_endian = 1; in hal_vpu2_h263d_gen_regs()
201 regs->reg54_endian.sw_dec_inswap32_e = 1; in hal_vpu2_h263d_gen_regs()
202 regs->reg54_endian.sw_dec_outswap32_e = 1; in hal_vpu2_h263d_gen_regs()
203 regs->reg54_endian.sw_dec_strswap32_e = 1; in hal_vpu2_h263d_gen_regs()
204 regs->reg54_endian.sw_dec_strendian_e = 1; in hal_vpu2_h263d_gen_regs()
205 regs->reg56_axi_ctrl.sw_dec_max_burst = 16; in hal_vpu2_h263d_gen_regs()
206 regs->reg52_error_concealment.sw_apf_threshold = 1; in hal_vpu2_h263d_gen_regs()
207 regs->reg57_enable_ctrl.sw_dec_timeout_e = 1; in hal_vpu2_h263d_gen_regs()
208 regs->reg57_enable_ctrl.sw_dec_clk_gate_e = 1; in hal_vpu2_h263d_gen_regs()
209 regs->reg57_enable_ctrl.sw_dec_e = 1; in hal_vpu2_h263d_gen_regs()
210 regs->reg59.sw_pred_bc_tap_0_0 = -1; in hal_vpu2_h263d_gen_regs()
211 regs->reg59.sw_pred_bc_tap_0_1 = 3; in hal_vpu2_h263d_gen_regs()
212 regs->reg59.sw_pred_bc_tap_0_2 = -6; in hal_vpu2_h263d_gen_regs()
213 regs->reg153.sw_pred_bc_tap_0_3 = 20; in hal_vpu2_h263d_gen_regs()
224 regs->reg63_cur_pic_base = (RK_U32)ctx->fd_curr; in hal_vpu2_h263d_gen_regs()
225 regs->reg64_input_stream_base = mpp_buffer_get_fd(buf_pkt); in hal_vpu2_h263d_gen_regs()
237 RK_U32 *regs = (RK_U32 *)ctx->regs; in hal_vpu2_h263d_start() local
244 mpp_log("reg[%03d]: %08x\n", i, regs[i]); in hal_vpu2_h263d_start()
251 wr_cfg.reg = regs; in hal_vpu2_h263d_start()
261 rd_cfg.reg = regs; in hal_vpu2_h263d_start()
292 RK_U32 *regs = (RK_U32 *)ctx->regs; in hal_vpu2_h263d_wait() local
297 mpp_log("reg[%03d]: %08x\n", i, regs[i]); in hal_vpu2_h263d_wait()