1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */
2 /*
3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4 */
5
6 #define MODULE_TAG "hal_h264d_vdpu384a"
7
8 #include <string.h>
9
10 #include "mpp_env.h"
11 #include "mpp_mem.h"
12 #include "mpp_common.h"
13 #include "mpp_bitput.h"
14 #include "mpp_buffer_impl.h"
15
16 #include "hal_h264d_global.h"
17 #include "hal_h264d_vdpu384a.h"
18 #include "vdpu384a_h264d.h"
19 #include "mpp_dec_cb_param.h"
20
21 /* Number registers for the decoder */
22 #define DEC_VDPU384A_REGISTERS 276
23
24 #define VDPU384A_SPSPPS_SIZE (MPP_ALIGN(2266 + 64, 128) / 8) /* byte, 2266 bit + Reserve 64 */
25 #define VDPU384A_SCALING_LIST_SIZE (6*16+2*64 + 128) /* bytes */
26 #define VDPU384A_ERROR_INFO_SIZE (256*144*4) /* bytes */
27 #define H264_CTU_SIZE 16
28
29 #define VDPU384A_ERROR_INFO_ALIGNED_SIZE (0)
30 #define VDPU384A_SPSPPS_ALIGNED_SIZE (MPP_ALIGN(VDPU384A_SPSPPS_SIZE, SZ_4K))
31 #define VDPU384A_SCALING_LIST_ALIGNED_SIZE (MPP_ALIGN(VDPU384A_SCALING_LIST_SIZE, SZ_4K))
32 #define VDPU384A_STREAM_INFO_SET_SIZE (VDPU384A_SPSPPS_ALIGNED_SIZE + \
33 VDPU384A_SCALING_LIST_ALIGNED_SIZE)
34
35 #define VDPU384A_ERROR_INFO_OFFSET (0)
36 #define VDPU384A_STREAM_INFO_OFFSET_BASE (VDPU384A_ERROR_INFO_OFFSET + VDPU384A_ERROR_INFO_ALIGNED_SIZE)
37 #define VDPU384A_SPSPPS_OFFSET(pos) (VDPU384A_STREAM_INFO_OFFSET_BASE + (VDPU384A_STREAM_INFO_SET_SIZE * pos))
38 #define VDPU384A_SCALING_LIST_OFFSET(pos) (VDPU384A_SPSPPS_OFFSET(pos) + VDPU384A_SPSPPS_ALIGNED_SIZE)
39 #define VDPU384A_INFO_BUFFER_SIZE(cnt) (VDPU384A_STREAM_INFO_OFFSET_BASE + (VDPU384A_STREAM_INFO_SET_SIZE * cnt))
40
41 #define SET_REF_INFO(regs, index, field, value)\
42 do{ \
43 switch(index){\
44 case 0: regs.reg99.ref0_##field = value; break;\
45 case 1: regs.reg99.ref1_##field = value; break;\
46 case 2: regs.reg99.ref2_##field = value; break;\
47 case 3: regs.reg99.ref3_##field = value; break;\
48 case 4: regs.reg100.ref4_##field = value; break;\
49 case 5: regs.reg100.ref5_##field = value; break;\
50 case 6: regs.reg100.ref6_##field = value; break;\
51 case 7: regs.reg100.ref7_##field = value; break;\
52 case 8: regs.reg101.ref8_##field = value; break;\
53 case 9: regs.reg101.ref9_##field = value; break;\
54 case 10: regs.reg101.ref10_##field = value; break;\
55 case 11: regs.reg101.ref11_##field = value; break;\
56 case 12: regs.reg102.ref12_##field = value; break;\
57 case 13: regs.reg102.ref13_##field = value; break;\
58 case 14: regs.reg102.ref14_##field = value; break;\
59 case 15: regs.reg102.ref15_##field = value; break;\
60 default: break;}\
61 }while(0)
62
63 #define VDPU384A_FAST_REG_SET_CNT 3
64
65 typedef struct h264d_rkv_buf_t {
66 RK_U32 valid;
67 Vdpu384aH264dRegSet *regs;
68 } H264dRkvBuf_t;
69
70 typedef struct Vdpu384aH264dRegCtx_t {
71 RK_U8 spspps[VDPU384A_SPSPPS_SIZE];
72 RK_U8 sclst[VDPU384A_SCALING_LIST_SIZE];
73
74 MppBuffer bufs;
75 RK_S32 bufs_fd;
76 void *bufs_ptr;
77 RK_U32 offset_errinfo;
78 RK_U32 offset_spspps[VDPU384A_FAST_REG_SET_CNT];
79 RK_U32 offset_sclst[VDPU384A_FAST_REG_SET_CNT];
80
81 H264dRkvBuf_t reg_buf[VDPU384A_FAST_REG_SET_CNT];
82
83 RK_U32 spspps_offset;
84 RK_U32 sclst_offset;
85
86 RK_S32 width;
87 RK_S32 height;
88 /* rcb buffers info */
89 RK_U32 bit_depth;
90 RK_U32 mbaff;
91 RK_U32 chroma_format_idc;
92
93 RK_S32 rcb_buf_size;
94 Vdpu384aRcbInfo rcb_info[RCB_BUF_COUNT];
95 MppBuffer rcb_buf[VDPU384A_FAST_REG_SET_CNT];
96
97 Vdpu384aH264dRegSet *regs;
98 HalBufs origin_bufs;
99 } Vdpu384aH264dRegCtx;
100
101 MPP_RET vdpu384a_h264d_deinit(void *hal);
rkv_ver_align(RK_U32 val)102 static RK_U32 rkv_ver_align(RK_U32 val)
103 {
104 return MPP_ALIGN(val, 16);
105 }
106
rkv_len_align(RK_U32 val)107 static RK_U32 rkv_len_align(RK_U32 val)
108 {
109 return (MPP_ALIGN(val, 16) * 3 / 2);
110 }
111
rkv_len_align_422(RK_U32 val)112 static RK_U32 rkv_len_align_422(RK_U32 val)
113 {
114 return ((5 * MPP_ALIGN(val, 16)) / 2);
115 }
116
vdpu384a_setup_scale_origin_bufs(H264dHalCtx_t * p_hal,MppFrame mframe)117 static MPP_RET vdpu384a_setup_scale_origin_bufs(H264dHalCtx_t *p_hal, MppFrame mframe)
118 {
119 Vdpu384aH264dRegCtx *ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;
120 /* for 8K FrameBuf scale mode */
121 size_t origin_buf_size = 0;
122
123 origin_buf_size = mpp_frame_get_buf_size(mframe);
124
125 if (!origin_buf_size) {
126 mpp_err_f("origin_bufs get buf size failed\n");
127 return MPP_NOK;
128 }
129 if (ctx->origin_bufs) {
130 hal_bufs_deinit(ctx->origin_bufs);
131 ctx->origin_bufs = NULL;
132 }
133 hal_bufs_init(&ctx->origin_bufs);
134 if (!ctx->origin_bufs) {
135 mpp_err_f("origin_bufs init fail\n");
136 return MPP_ERR_NOMEM;
137 }
138 hal_bufs_setup(ctx->origin_bufs, 16, 1, &origin_buf_size);
139
140 return MPP_OK;
141 }
142
prepare_spspps(H264dHalCtx_t * p_hal,RK_U64 * data,RK_U32 len)143 static MPP_RET prepare_spspps(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len)
144 {
145 RK_S32 i = 0, j = 0;
146 RK_S32 is_long_term = 0, voidx = 0;
147 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
148 RK_U32 tmp = 0;
149 BitputCtx_t bp;
150
151 mpp_set_bitput_ctx(&bp, data, len);
152
153 if (!p_hal->fast_mode && !pp->spspps_update) {
154 bp.index = 2;
155 bp.bitpos = 24;
156 bp.bvalue = bp.pbuf[bp.index] & 0xFFFFFF;
157 } else {
158 RK_U32 pic_width, pic_height;
159
160 //!< sps syntax
161 pic_width = 16 * (pp->wFrameWidthInMbsMinus1 + 1);
162 pic_height = 16 * (pp->wFrameHeightInMbsMinus1 + 1);
163 pic_height *= (2 - pp->frame_mbs_only_flag);
164 pic_height /= (1 + pp->field_pic_flag);
165 mpp_put_bits(&bp, pp->seq_parameter_set_id, 4);
166 mpp_put_bits(&bp, pp->profile_idc, 8);
167 mpp_put_bits(&bp, pp->constraint_set3_flag, 1);
168 mpp_put_bits(&bp, pp->chroma_format_idc, 2);
169 mpp_put_bits(&bp, pp->bit_depth_luma_minus8, 3);
170 mpp_put_bits(&bp, pp->bit_depth_chroma_minus8, 3);
171 mpp_put_bits(&bp, 0, 1); // set 0
172 mpp_put_bits(&bp, pp->log2_max_frame_num_minus4, 4);
173 mpp_put_bits(&bp, pp->num_ref_frames, 5);
174 mpp_put_bits(&bp, pp->pic_order_cnt_type, 2);
175 mpp_put_bits(&bp, pp->log2_max_pic_order_cnt_lsb_minus4, 4);
176 mpp_put_bits(&bp, pp->delta_pic_order_always_zero_flag, 1);
177 mpp_put_bits(&bp, pic_width, 16);
178 mpp_put_bits(&bp, pic_height, 16);
179 mpp_put_bits(&bp, pp->frame_mbs_only_flag, 1);
180 mpp_put_bits(&bp, pp->MbaffFrameFlag, 1);
181 mpp_put_bits(&bp, pp->direct_8x8_inference_flag, 1);
182 /* multi-view */
183 mpp_put_bits(&bp, pp->mvc_extension_enable, 1);
184 if (pp->mvc_extension_enable) {
185 mpp_put_bits(&bp, (pp->num_views_minus1 + 1), 2);
186 mpp_put_bits(&bp, pp->view_id[0], 10);
187 mpp_put_bits(&bp, pp->view_id[1], 10);
188 } else {
189 mpp_put_bits(&bp, 0, 22);
190 }
191 // hw_fifo_align_bits(&bp, 128);
192 //!< pps syntax
193 mpp_put_bits(&bp, pp->pps_pic_parameter_set_id, 8);
194 mpp_put_bits(&bp, pp->pps_seq_parameter_set_id, 5);
195 mpp_put_bits(&bp, pp->entropy_coding_mode_flag, 1);
196 mpp_put_bits(&bp, pp->pic_order_present_flag, 1);
197
198 mpp_put_bits(&bp, pp->num_ref_idx_l0_active_minus1, 5);
199 mpp_put_bits(&bp, pp->num_ref_idx_l1_active_minus1, 5);
200 mpp_put_bits(&bp, pp->weighted_pred_flag, 1);
201 mpp_put_bits(&bp, pp->weighted_bipred_idc, 2);
202 mpp_put_bits(&bp, pp->pic_init_qp_minus26, 7);
203 mpp_put_bits(&bp, pp->pic_init_qs_minus26, 6);
204 mpp_put_bits(&bp, pp->chroma_qp_index_offset, 5);
205 mpp_put_bits(&bp, pp->deblocking_filter_control_present_flag, 1);
206 mpp_put_bits(&bp, pp->constrained_intra_pred_flag, 1);
207 mpp_put_bits(&bp, pp->redundant_pic_cnt_present_flag, 1);
208 mpp_put_bits(&bp, pp->transform_8x8_mode_flag, 1);
209 mpp_put_bits(&bp, pp->second_chroma_qp_index_offset, 5);
210 mpp_put_bits(&bp, pp->scaleing_list_enable_flag, 1);
211 }
212
213 //!< set dpb
214 for (i = 0; i < 16; i++) {
215 is_long_term = (pp->RefFrameList[i].bPicEntry != 0xff) ? pp->RefFrameList[i].AssociatedFlag : 0;
216 tmp |= (RK_U32)(is_long_term & 0x1) << i;
217 }
218 for (i = 0; i < 16; i++) {
219 voidx = (pp->RefFrameList[i].bPicEntry != 0xff) ? pp->RefPicLayerIdList[i] : 0;
220 tmp |= (RK_U32)(voidx & 0x1) << (i + 16);
221 }
222 mpp_put_bits(&bp, tmp, 32);
223 /* set current frame */
224 mpp_put_bits(&bp, pp->field_pic_flag, 1);
225 mpp_put_bits(&bp, (pp->field_pic_flag && pp->CurrPic.AssociatedFlag), 1);
226
227 mpp_put_bits(&bp, pp->CurrFieldOrderCnt[0], 32);
228 mpp_put_bits(&bp, pp->CurrFieldOrderCnt[1], 32);
229
230 /* refer poc */
231 for (i = 0; i < 16; i++) {
232 mpp_put_bits(&bp, pp->FieldOrderCntList[i][0], 32);
233 mpp_put_bits(&bp, pp->FieldOrderCntList[i][1], 32);
234 }
235
236 tmp = 0;
237 for (i = 0; i < 16; i++)
238 tmp |= ((pp->RefPicFiledFlags >> i) & 0x01) << i;
239 for (i = 0; i < 16; i++)
240 tmp |= ((pp->UsedForReferenceFlags >> (2 * i + 0)) & 0x01) << (i + 16);
241 mpp_put_bits(&bp, tmp, 32);
242
243 tmp = 0;
244 for (i = 0; i < 16; i++)
245 tmp |= ((pp->UsedForReferenceFlags >> (2 * i + 1)) & 0x01) << i;
246 for (i = 0; i < 16; i++)
247 tmp |= ((pp->RefPicColmvUsedFlags >> i) & 0x01) << (i + 16);
248 mpp_put_bits(&bp, tmp, 32);
249
250 /* rps */
251 {
252 RK_S32 dpb_idx = 0;
253 RK_S32 dpb_valid = 0, bottom_flag = 0;
254 RK_U32 max_frame_num = 0;
255 RK_U16 frame_num_wrap = 0;
256
257 max_frame_num = 1 << (pp->log2_max_frame_num_minus4 + 4);
258 for (i = 0; i < 16; i++) {
259 if ((pp->NonExistingFrameFlags >> i) & 0x01) {
260 frame_num_wrap = 0;
261 } else {
262 if (pp->RefFrameList[i].AssociatedFlag) {
263 frame_num_wrap = pp->FrameNumList[i];
264 } else {
265 frame_num_wrap = (pp->FrameNumList[i] > pp->frame_num) ?
266 (pp->FrameNumList[i] - max_frame_num) : pp->FrameNumList[i];
267 }
268 }
269 mpp_put_bits(&bp, frame_num_wrap, 16);
270 }
271
272 /* dbp_idx_p_l0_32x7bit + dbp_idx_b_l0_32x7bit + dbp_idx_b_l1_32x7bit */
273 for (j = 0; j < 3; j++) {
274 for (i = 0; i < 32; i++) {
275 tmp = 0;
276 dpb_valid = (p_hal->slice_long[0].RefPicList[j][i].bPicEntry == 0xff) ? 0 : 1;
277 dpb_idx = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].Index7Bits : 0;
278 bottom_flag = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].AssociatedFlag : 0;
279 voidx = dpb_valid ? pp->RefPicLayerIdList[dpb_idx] : 0;
280 tmp |= (RK_U32)(dpb_idx | (dpb_valid << 4)) & 0x1f;
281 tmp |= (RK_U32)(bottom_flag & 0x1) << 5;
282 if (dpb_valid)
283 tmp |= (RK_U32)(voidx & 0x1) << 6;
284 mpp_put_bits(&bp, tmp, 7);
285 }
286 }
287 }
288 mpp_put_align(&bp, 64, 0);//128
289
290 #ifdef DUMP_VDPU384A_DATAS
291 {
292 char *cur_fname = "global_cfg.dat";
293 memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
294 sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
295 dump_data_to_file(dump_cur_fname_path, (void *)bp.pbuf, 64 * bp.index + bp.bitpos, 128, 0);
296 }
297 #endif
298
299 return MPP_OK;
300 }
301
prepare_scanlist(H264dHalCtx_t * p_hal,RK_U8 * data,RK_U32 len)302 static MPP_RET prepare_scanlist(H264dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
303 {
304 RK_U32 i = 0, j = 0, n = 0;
305
306 if (!p_hal->pp->scaleing_list_enable_flag)
307 return MPP_OK;
308
309 for (i = 0; i < 6; i++) { //4x4, 6 lists
310 /* dump by block4x4, vectial direction */
311 for (j = 0; j < 4; j++) {
312 data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 0];
313 data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 1];
314 data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 2];
315 data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 3];
316 }
317 }
318
319 for (i = 0; i < 2; i++) { //8x8, 2 lists
320 RK_U32 blk4_x = 0, blk4_y = 0;
321
322 /* dump by block4x4, vectial direction */
323 for (blk4_y = 0; blk4_y < 8; blk4_y += 4) {
324 for (blk4_x = 0; blk4_x < 8; blk4_x += 4) {
325 RK_U32 pos = blk4_y * 8 + blk4_x;
326
327 for (j = 0; j < 4; j++) {
328 data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 0];
329 data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 1];
330 data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 2];
331 data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 3];
332 }
333 }
334 }
335 }
336
337 mpp_assert(n <= len);
338
339 #ifdef DUMP_VDPU384A_DATAS
340 {
341 char *cur_fname = "scanlist.dat";
342 memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
343 sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
344 dump_data_to_file(dump_cur_fname_path, (void *)data, 8 * n, 128, 0);
345 }
346 #endif
347
348 return MPP_OK;
349 }
350
set_registers(H264dHalCtx_t * p_hal,Vdpu384aH264dRegSet * regs,HalTaskInfo * task)351 static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu384aH264dRegSet *regs, HalTaskInfo *task)
352 {
353 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
354 HalBuf *mv_buf = NULL;
355 HalBuf *origin_buf = NULL;
356 Vdpu384aH264dRegCtx *ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;
357
358 // memset(regs, 0, sizeof(Vdpu384aH264dRegSet));
359 regs->h264d_paras.reg66_stream_len = p_hal->strm_len;
360
361 //!< caculate the yuv_frame_size
362 {
363 MppFrame mframe = NULL;
364 RK_U32 hor_virstride = 0;
365 RK_U32 ver_virstride = 0;
366 RK_U32 y_virstride = 0;
367 RK_U32 uv_virstride = 0;
368
369 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe);
370 hor_virstride = mpp_frame_get_hor_stride(mframe);
371 ver_virstride = mpp_frame_get_ver_stride(mframe);
372 y_virstride = hor_virstride * ver_virstride;
373 uv_virstride = hor_virstride * ver_virstride / 2;
374
375 if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
376 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
377 RK_U32 fbd_offset;
378
379 fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16;
380
381 regs->ctrl_regs.reg9.dpb_data_sel = 0;
382 regs->ctrl_regs.reg9.dpb_output_dis = 0;
383 regs->ctrl_regs.reg9.pp_m_output_mode = 0;
384
385 regs->h264d_paras.reg68_dpb_hor_virstride = fbc_hdr_stride / 64;
386 regs->h264d_addrs.reg193_dpb_fbc64x4_payload_offset = fbd_offset;
387 regs->h264d_paras.reg80_error_ref_hor_virstride = regs->h264d_paras.reg68_dpb_hor_virstride;
388 } else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) {
389 regs->ctrl_regs.reg9.dpb_data_sel = 1;
390 regs->ctrl_regs.reg9.dpb_output_dis = 1;
391 regs->ctrl_regs.reg9.pp_m_output_mode = 2;
392
393 regs->h264d_paras.reg77_pp_m_hor_stride = hor_virstride * 6 / 16;
394 regs->h264d_paras.reg79_pp_m_y_virstride = (y_virstride + uv_virstride) / 16;
395 regs->h264d_paras.reg80_error_ref_hor_virstride = regs->h264d_paras.reg77_pp_m_hor_stride;
396 } else {
397 regs->ctrl_regs.reg9.dpb_data_sel = 1;
398 regs->ctrl_regs.reg9.dpb_output_dis = 1;
399 regs->ctrl_regs.reg9.pp_m_output_mode = 1;
400
401 regs->h264d_paras.reg77_pp_m_hor_stride = hor_virstride / 16;
402 regs->h264d_paras.reg78_pp_m_uv_hor_stride = hor_virstride / 16;
403 regs->h264d_paras.reg79_pp_m_y_virstride = y_virstride / 16;
404 regs->h264d_paras.reg80_error_ref_hor_virstride = regs->h264d_paras.reg77_pp_m_hor_stride;
405 }
406 regs->h264d_paras.reg81_error_ref_raster_uv_hor_virstride = regs->h264d_paras.reg78_pp_m_uv_hor_stride;
407 regs->h264d_paras.reg82_error_ref_virstride = regs->h264d_paras.reg79_pp_m_y_virstride;
408 }
409 //!< set current
410 {
411 MppBuffer mbuffer = NULL;
412 RK_S32 fd = -1;
413
414 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &mbuffer);
415 fd = mpp_buffer_get_fd(mbuffer);
416 /* output rkfbc64 */
417 // regs->h264d_addrs.reg168_dpb_decout_base = fd;
418 /* output raster/tile4x4 */
419 regs->common_addr.reg135_pp_m_decout_base = fd;
420 regs->h264d_addrs.reg192_dpb_payload64x4_st_cur_base = fd;
421
422 //colmv_cur_base
423 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, pp->CurrPic.Index7Bits);
424 regs->h264d_addrs.reg216_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
425 regs->h264d_addrs.reg169_error_ref_base = fd;
426 }
427 //!< set reference
428 {
429 RK_S32 i = 0;
430 RK_S32 fd = -1;
431 RK_S32 ref_index = -1;
432 RK_S32 near_index = -1;
433 MppBuffer mbuffer = NULL;
434 RK_U32 min_frame_num = 0;
435 MppFrame mframe = NULL;
436
437 for (i = 0; i < 15; i++) {
438 if (pp->RefFrameList[i].bPicEntry != 0xff) {
439 ref_index = pp->RefFrameList[i].Index7Bits;
440 near_index = pp->RefFrameList[i].Index7Bits;
441 } else {
442 ref_index = (near_index < 0) ? pp->CurrPic.Index7Bits : near_index;
443 }
444 /* mark 3 to differ from current frame */
445 mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer);
446 mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_FRAME_PTR, &mframe);
447 if (ctx->origin_bufs && mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY) {
448 origin_buf = hal_bufs_get_buf(ctx->origin_bufs, ref_index);
449 mbuffer = origin_buf->buf[0];
450 }
451
452 if (pp->FrameNumList[i] < pp->frame_num &&
453 pp->FrameNumList[i] > min_frame_num &&
454 (!mpp_frame_get_errinfo(mframe))) {
455 min_frame_num = pp->FrameNumList[i];
456 regs->h264d_addrs.reg169_error_ref_base = mpp_buffer_get_fd(mbuffer);
457 }
458
459 fd = mpp_buffer_get_fd(mbuffer);
460 regs->h264d_addrs.reg170_185_ref_base[i] = fd;
461 regs->h264d_addrs.reg195_210_payload_st_ref_base[i] = fd;
462 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index);
463 regs->h264d_addrs.reg217_232_colmv_ref_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
464 }
465
466 if (pp->RefFrameList[15].bPicEntry != 0xff) {
467 ref_index = pp->RefFrameList[15].Index7Bits;
468 } else {
469 ref_index = (near_index < 0) ? pp->CurrPic.Index7Bits : near_index;
470 }
471
472 mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer);
473 fd = mpp_buffer_get_fd(mbuffer);
474 if (mpp_frame_get_thumbnail_en(mframe) == 2) {
475 origin_buf = hal_bufs_get_buf(ctx->origin_bufs, ref_index);
476 fd = mpp_buffer_get_fd(origin_buf->buf[0]);
477 }
478 regs->h264d_addrs.reg170_185_ref_base[15] = fd;
479 regs->h264d_addrs.reg195_210_payload_st_ref_base[15] = fd;
480 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index);
481 regs->h264d_addrs.reg217_232_colmv_ref_base[15] = mpp_buffer_get_fd(mv_buf->buf[0]);
482 }
483 {
484 MppBuffer mbuffer = NULL;
485
486 mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &mbuffer);
487 regs->common_addr.reg128_strm_base = mpp_buffer_get_fd(mbuffer);
488 regs->common_addr.reg129_stream_buf_st_base = mpp_buffer_get_fd(mbuffer);
489 regs->common_addr.reg130_stream_buf_end_base = mpp_buffer_get_fd(mbuffer);
490 mpp_dev_set_reg_offset(p_hal->dev, 130, mpp_buffer_get_size(mbuffer));
491 // regs->h264d_paras.reg65_strm_start_bit = 2 * 8;
492 #ifdef DUMP_VDPU384A_DATAS
493 {
494 char *cur_fname = "stream_in.dat";
495 memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
496 sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
497 dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mbuffer),
498 8 * p_hal->strm_len, 128, 0);
499 }
500 #endif
501 }
502
503 {
504 //scale down config
505 MppFrame mframe = NULL;
506 MppBuffer mbuffer = NULL;
507 RK_S32 fd = -1;
508 MppFrameThumbnailMode thumbnail_mode;
509
510 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &mbuffer);
511 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits,
512 SLOT_FRAME_PTR, &mframe);
513 fd = mpp_buffer_get_fd(mbuffer);
514 thumbnail_mode = mpp_frame_get_thumbnail_en(mframe);
515 switch (thumbnail_mode) {
516 case MPP_FRAME_THUMBNAIL_ONLY:
517 regs->common_addr.reg133_scale_down_base = fd;
518 origin_buf = hal_bufs_get_buf(ctx->origin_bufs, pp->CurrPic.Index7Bits);
519 fd = mpp_buffer_get_fd(origin_buf->buf[0]);
520 /* output rkfbc64 */
521 // regs->h264d_addrs.reg168_dpb_decout_base = fd;
522 /* output raster/tile4x4 */
523 regs->common_addr.reg135_pp_m_decout_base = fd;
524 regs->h264d_addrs.reg192_dpb_payload64x4_st_cur_base = fd;
525 regs->h264d_addrs.reg169_error_ref_base = fd;
526 vdpu384a_setup_down_scale(mframe, p_hal->dev, ®s->ctrl_regs, (void*)®s->h264d_paras);
527 break;
528 case MPP_FRAME_THUMBNAIL_MIXED:
529 regs->common_addr.reg133_scale_down_base = fd;
530 vdpu384a_setup_down_scale(mframe, p_hal->dev, ®s->ctrl_regs, (void*)®s->h264d_paras);
531 break;
532 case MPP_FRAME_THUMBNAIL_NONE:
533 default:
534 regs->ctrl_regs.reg9.scale_down_en = 0;
535 break;
536 }
537 }
538
539 return MPP_OK;
540 }
541
init_ctrl_regs(Vdpu384aH264dRegSet * regs)542 static MPP_RET init_ctrl_regs(Vdpu384aH264dRegSet *regs)
543 {
544 Vdpu384aCtrlReg *ctrl_regs = ®s->ctrl_regs;
545
546 ctrl_regs->reg8_dec_mode = 1; //!< h264
547 ctrl_regs->reg9.low_latency_en = 0;
548
549 ctrl_regs->reg10.strmd_auto_gating_e = 1;
550 ctrl_regs->reg10.inter_auto_gating_e = 1;
551 ctrl_regs->reg10.intra_auto_gating_e = 1;
552 ctrl_regs->reg10.transd_auto_gating_e = 1;
553 ctrl_regs->reg10.recon_auto_gating_e = 1;
554 ctrl_regs->reg10.filterd_auto_gating_e = 1;
555 ctrl_regs->reg10.bus_auto_gating_e = 1;
556 ctrl_regs->reg10.ctrl_auto_gating_e = 1;
557 ctrl_regs->reg10.rcb_auto_gating_e = 1;
558 ctrl_regs->reg10.err_prc_auto_gating_e = 1;
559
560 ctrl_regs->reg11.rd_outstanding = 32;
561 ctrl_regs->reg11.wr_outstanding = 250;
562
563 ctrl_regs->reg13_core_timeout_threshold = 0xffffff;
564
565 ctrl_regs->reg16.error_proc_disable = 1;
566 ctrl_regs->reg16.error_spread_disable = 0;
567 ctrl_regs->reg16.roi_error_ctu_cal_en = 0;
568
569 ctrl_regs->reg20_cabac_error_en_lowbits = 0xfffedfff;
570 ctrl_regs->reg21_cabac_error_en_highbits = 0x0ffbf9ff;
571
572 /* performance */
573 ctrl_regs->reg28.axi_perf_work_e = 1;
574 ctrl_regs->reg28.axi_cnt_type = 1;
575 ctrl_regs->reg28.rd_latency_id = 11;
576
577 ctrl_regs->reg29.addr_align_type = 2;
578 ctrl_regs->reg29.ar_cnt_id_type = 0;
579 ctrl_regs->reg29.aw_cnt_id_type = 0;
580 ctrl_regs->reg29.ar_count_id = 0xa;
581 ctrl_regs->reg29.aw_count_id = 0;
582 ctrl_regs->reg29.rd_band_width_mode = 0;
583
584 return MPP_OK;
585 }
586
vdpu384a_h264d_init(void * hal,MppHalCfg * cfg)587 MPP_RET vdpu384a_h264d_init(void *hal, MppHalCfg *cfg)
588 {
589 MPP_RET ret = MPP_ERR_UNKNOW;
590 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
591
592 INP_CHECK(ret, NULL == p_hal);
593 (void) cfg;
594
595 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu384aH264dRegCtx)));
596 Vdpu384aH264dRegCtx *reg_ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;
597 RK_U32 max_cnt = p_hal->fast_mode ? VDPU384A_FAST_REG_SET_CNT : 1;
598 RK_U32 i = 0;
599
600 //!< malloc buffers
601 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->bufs,
602 VDPU384A_INFO_BUFFER_SIZE(max_cnt)));
603 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs);
604 reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs);
605 reg_ctx->offset_errinfo = VDPU384A_ERROR_INFO_OFFSET;
606 for (i = 0; i < max_cnt; i++) {
607 reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu384aH264dRegSet, 1);
608 init_ctrl_regs(reg_ctx->reg_buf[i].regs);
609 reg_ctx->offset_spspps[i] = VDPU384A_SPSPPS_OFFSET(i);
610 reg_ctx->offset_sclst[i] = VDPU384A_SCALING_LIST_OFFSET(i);
611 }
612
613 mpp_buffer_attach_dev(reg_ctx->bufs, p_hal->dev);
614
615 if (!p_hal->fast_mode) {
616 reg_ctx->regs = reg_ctx->reg_buf[0].regs;
617 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0];
618 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0];
619 }
620
621 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
622 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align);
623 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align);
624
625 if (cfg->hal_fbc_adj_cfg) {
626 cfg->hal_fbc_adj_cfg->func = vdpu384a_afbc_align_calc;
627 cfg->hal_fbc_adj_cfg->expand = 16;
628 }
629
630 __RETURN:
631 return MPP_OK;
632 __FAILED:
633 vdpu384a_h264d_deinit(hal);
634
635 return ret;
636 }
637
vdpu384a_h264d_deinit(void * hal)638 MPP_RET vdpu384a_h264d_deinit(void *hal)
639 {
640 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
641 Vdpu384aH264dRegCtx *reg_ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;
642
643 RK_U32 i = 0;
644 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
645
646 if (reg_ctx->bufs) {
647 mpp_buffer_put(reg_ctx->bufs);
648 reg_ctx->bufs = NULL;
649 }
650
651 for (i = 0; i < loop; i++)
652 MPP_FREE(reg_ctx->reg_buf[i].regs);
653
654 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1;
655 for (i = 0; i < loop; i++) {
656 if (reg_ctx->rcb_buf[i]) {
657 mpp_buffer_put(reg_ctx->rcb_buf[i]);
658 reg_ctx->rcb_buf[i] = NULL;
659 }
660 }
661
662 if (p_hal->cmv_bufs) {
663 hal_bufs_deinit(p_hal->cmv_bufs);
664 p_hal->cmv_bufs = NULL;
665 }
666
667 if (reg_ctx->origin_bufs) {
668 hal_bufs_deinit(reg_ctx->origin_bufs);
669 reg_ctx->origin_bufs = NULL;
670 }
671
672 MPP_FREE(p_hal->reg_ctx);
673
674 return MPP_OK;
675 }
676
h264d_refine_rcb_size(H264dHalCtx_t * p_hal,Vdpu384aRcbInfo * rcb_info,RK_S32 width,RK_S32 height)677 static void h264d_refine_rcb_size(H264dHalCtx_t *p_hal, Vdpu384aRcbInfo *rcb_info,
678 RK_S32 width, RK_S32 height)
679 {
680 RK_U32 rcb_bits = 0;
681 RK_U32 mbaff = p_hal->pp->MbaffFrameFlag;
682 RK_U32 bit_depth = p_hal->pp->bit_depth_luma_minus8 + 8;
683 RK_U32 chroma_format_idc = p_hal->pp->chroma_format_idc;
684 RK_U32 row_uv_para = 1; // for yuv420/yuv422
685 RK_U32 filterd_row_append = 8192;
686
687 // vdpu384a h264d support yuv400/yuv420/yuv422
688 if (chroma_format_idc == 0)
689 row_uv_para = 0;
690
691 width = MPP_ALIGN(width, H264_CTU_SIZE);
692 height = MPP_ALIGN(height, H264_CTU_SIZE);
693 /* RCB_STRMD_ROW && RCB_STRMD_TILE_ROW*/
694 if (width > 4096)
695 rcb_bits = ((width + 15) / 16) * 158 * (mbaff ? 2 : 1);
696 else
697 rcb_bits = 0;
698 rcb_info[RCB_STRMD_ROW].size = MPP_RCB_BYTES(rcb_bits);
699 rcb_info[RCB_STRMD_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
700 /* RCB_INTER_ROW && RCB_INTER_TILE_ROW*/
701 rcb_bits = ((width + 3) / 4) * 92 * (mbaff ? 2 : 1);
702 rcb_info[RCB_INTER_ROW].size = MPP_RCB_BYTES(rcb_bits);
703 rcb_info[RCB_INTER_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
704 /* RCB_INTRA_ROW && RCB_INTRA_TILE_ROW*/
705 rcb_bits = MPP_ALIGN(width, 512) * (bit_depth + 2) * (mbaff ? 2 : 1);
706 if (chroma_format_idc == 1 || chroma_format_idc == 2)
707 rcb_bits = rcb_bits * 5 / 2; //TODO:
708
709 rcb_info[RCB_INTRA_ROW].size = MPP_RCB_BYTES(rcb_bits);
710 rcb_info[RCB_INTRA_TILE_ROW].size = 0;
711 /* RCB_FILTERD_ROW && RCB_FILTERD_PROTECT_ROW*/
712 // save space mode : half for RCB_FILTERD_ROW, half for RCB_FILTERD_PROTECT_ROW
713 rcb_bits = width * 13 * ((6 + 3 * row_uv_para) * (mbaff ? 2 : 1) + 2 * row_uv_para + 1.5);
714 if (width > 4096)
715 filterd_row_append = 27648;
716 rcb_info[RCB_FILTERD_ROW].size = filterd_row_append + MPP_RCB_BYTES(rcb_bits / 2);
717 rcb_info[RCB_FILTERD_PROTECT_ROW].size = filterd_row_append + MPP_RCB_BYTES(rcb_bits / 2);
718
719 rcb_info[RCB_FILTERD_TILE_ROW].size = 0;
720 /* RCB_FILTERD_TILE_COL */
721 rcb_info[RCB_FILTERD_TILE_COL].size = 0;
722
723 }
724
hal_h264d_rcb_info_update(void * hal)725 static void hal_h264d_rcb_info_update(void *hal)
726 {
727 H264dHalCtx_t *p_hal = (H264dHalCtx_t*)hal;
728 RK_U32 mbaff = p_hal->pp->MbaffFrameFlag;
729 RK_U32 bit_depth = p_hal->pp->bit_depth_luma_minus8 + 8;
730 RK_U32 chroma_format_idc = p_hal->pp->chroma_format_idc;
731 Vdpu384aH264dRegCtx *ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;
732 RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);
733 RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);
734
735 if ( ctx->bit_depth != bit_depth ||
736 ctx->chroma_format_idc != chroma_format_idc ||
737 ctx->mbaff != mbaff ||
738 ctx->width != width ||
739 ctx->height != height) {
740 RK_U32 i;
741 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(ctx->reg_buf) : 1;
742
743 ctx->rcb_buf_size = vdpu384a_get_rcb_buf_size(ctx->rcb_info, width, height);
744 h264d_refine_rcb_size(hal, ctx->rcb_info, width, height);
745 /* vdpu384a_check_rcb_buf_size(ctx->rcb_info, width, height); */
746 for (i = 0; i < loop; i++) {
747 MppBuffer rcb_buf = ctx->rcb_buf[i];
748
749 if (rcb_buf) {
750 mpp_buffer_put(rcb_buf);
751 ctx->rcb_buf[i] = NULL;
752 }
753 mpp_buffer_get(p_hal->buf_group, &rcb_buf, ctx->rcb_buf_size);
754 ctx->rcb_buf[i] = rcb_buf;
755 }
756 ctx->bit_depth = bit_depth;
757 ctx->width = width;
758 ctx->height = height;
759 ctx->mbaff = mbaff;
760 ctx->chroma_format_idc = chroma_format_idc;
761 }
762 }
763
vdpu384a_h264d_gen_regs(void * hal,HalTaskInfo * task)764 MPP_RET vdpu384a_h264d_gen_regs(void *hal, HalTaskInfo *task)
765 {
766 MPP_RET ret = MPP_ERR_UNKNOW;
767 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
768 RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);
769 RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);
770 Vdpu384aH264dRegCtx *ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;
771 Vdpu384aH264dRegSet *regs = ctx->regs;
772 MppFrame mframe;
773 RK_S32 mv_size = MPP_ALIGN(width, 64) * MPP_ALIGN(height, 16); // 16 byte unit
774
775 INP_CHECK(ret, NULL == p_hal);
776
777 if (task->dec.flags.parse_err ||
778 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
779 goto __RETURN;
780 }
781
782 /* if is field mode is enabled enlarge colmv buffer and disable colmv compression */
783 if (!p_hal->pp->frame_mbs_only_flag)
784 mv_size *= 2;
785
786 if (p_hal->cmv_bufs == NULL || p_hal->mv_size < mv_size) {
787 size_t size = mv_size;
788
789 if (p_hal->cmv_bufs) {
790 hal_bufs_deinit(p_hal->cmv_bufs);
791 p_hal->cmv_bufs = NULL;
792 }
793
794 hal_bufs_init(&p_hal->cmv_bufs);
795 if (p_hal->cmv_bufs == NULL) {
796 mpp_err_f("colmv bufs init fail");
797 goto __RETURN;
798 }
799 p_hal->mv_size = mv_size;
800 p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots);
801 hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size);
802 }
803
804 mpp_buf_slot_get_prop(p_hal->frame_slots, p_hal->pp->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe);
805 if (mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY &&
806 ctx->origin_bufs == NULL) {
807 vdpu384a_setup_scale_origin_bufs(p_hal, mframe);
808 }
809
810 if (p_hal->fast_mode) {
811 RK_U32 i = 0;
812 for (i = 0; i < MPP_ARRAY_ELEMS(ctx->reg_buf); i++) {
813 if (!ctx->reg_buf[i].valid) {
814 task->dec.reg_index = i;
815 regs = ctx->reg_buf[i].regs;
816
817 ctx->spspps_offset = ctx->offset_spspps[i];
818 ctx->sclst_offset = ctx->offset_sclst[i];
819 ctx->reg_buf[i].valid = 1;
820 break;
821 }
822 }
823 }
824
825 #ifdef DUMP_VDPU384A_DATAS
826 {
827 memset(dump_cur_dir, 0, sizeof(dump_cur_dir));
828 sprintf(dump_cur_dir, "avc/Frame%04d", dump_cur_frame);
829 if (access(dump_cur_dir, 0)) {
830 if (mkdir(dump_cur_dir))
831 mpp_err_f("error: mkdir %s\n", dump_cur_dir);
832 }
833 dump_cur_frame++;
834 }
835 #endif
836
837 prepare_spspps(p_hal, (RK_U64 *)&ctx->spspps, sizeof(ctx->spspps) / 8);
838 prepare_scanlist(p_hal, ctx->sclst, sizeof(ctx->sclst));
839 set_registers(p_hal, regs, task);
840
841 //!< copy spspps datas
842 memcpy((char *)ctx->bufs_ptr + ctx->spspps_offset, (char *)ctx->spspps, sizeof(ctx->spspps));
843
844 regs->common_addr.reg131_gbl_base = ctx->bufs_fd;
845 regs->h264d_paras.reg67_global_len = VDPU384A_SPSPPS_SIZE / 16; // 128 bit as unit
846 mpp_dev_set_reg_offset(p_hal->dev, 131, ctx->spspps_offset);
847
848 if (p_hal->pp->scaleing_list_enable_flag) {
849 memcpy((char *)ctx->bufs_ptr + ctx->sclst_offset, (void *)ctx->sclst, sizeof(ctx->sclst));
850 regs->common_addr.reg132_scanlist_addr = ctx->bufs_fd;
851 mpp_dev_set_reg_offset(p_hal->dev, 132, ctx->sclst_offset);
852 } else {
853 regs->common_addr.reg132_scanlist_addr = 0;
854 }
855
856 hal_h264d_rcb_info_update(p_hal);
857 vdpu384a_setup_rcb(®s->common_addr, p_hal->dev, p_hal->fast_mode ?
858 ctx->rcb_buf[task->dec.reg_index] : ctx->rcb_buf[0],
859 ctx->rcb_info);
860 vdpu384a_setup_statistic(®s->ctrl_regs);
861 mpp_buffer_sync_end(ctx->bufs);
862
863 __RETURN:
864 return ret = MPP_OK;
865 }
866
vdpu384a_h264d_start(void * hal,HalTaskInfo * task)867 MPP_RET vdpu384a_h264d_start(void *hal, HalTaskInfo *task)
868 {
869 MPP_RET ret = MPP_ERR_UNKNOW;
870 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
871 INP_CHECK(ret, NULL == p_hal);
872
873 if (task->dec.flags.parse_err ||
874 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
875 goto __RETURN;
876 }
877
878 Vdpu384aH264dRegCtx *reg_ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;
879 Vdpu384aH264dRegSet *regs = p_hal->fast_mode ?
880 reg_ctx->reg_buf[task->dec.reg_index].regs :
881 reg_ctx->regs;
882 MppDev dev = p_hal->dev;
883
884 do {
885 MppDevRegWrCfg wr_cfg;
886 MppDevRegRdCfg rd_cfg;
887
888 wr_cfg.reg = ®s->ctrl_regs;
889 wr_cfg.size = sizeof(regs->ctrl_regs);
890 wr_cfg.offset = OFFSET_CTRL_REGS;
891 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
892 if (ret) {
893 mpp_err_f("set register write failed %d\n", ret);
894 break;
895 }
896
897 wr_cfg.reg = ®s->common_addr;
898 wr_cfg.size = sizeof(regs->common_addr);
899 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS;
900 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
901 if (ret) {
902 mpp_err_f("set register write failed %d\n", ret);
903 break;
904 }
905
906 wr_cfg.reg = ®s->h264d_paras;
907 wr_cfg.size = sizeof(regs->h264d_paras);
908 wr_cfg.offset = OFFSET_CODEC_PARAS_REGS;
909 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
910 if (ret) {
911 mpp_err_f("set register write failed %d\n", ret);
912 break;
913 }
914
915 wr_cfg.reg = ®s->h264d_addrs;
916 wr_cfg.size = sizeof(regs->h264d_addrs);
917 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS;
918 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
919 if (ret) {
920 mpp_err_f("set register write failed %d\n", ret);
921 break;
922 }
923
924 rd_cfg.reg = ®s->ctrl_regs.reg15;
925 rd_cfg.size = sizeof(regs->ctrl_regs.reg15);
926 rd_cfg.offset = OFFSET_INTERRUPT_REGS;
927 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
928 if (ret) {
929 mpp_err_f("set register read failed %d\n", ret);
930 break;
931 }
932
933 /* rcb info for sram */
934 vdpu384a_set_rcbinfo(dev, (Vdpu384aRcbInfo*)reg_ctx->rcb_info);
935
936 /* send request to hardware */
937 ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
938 if (ret) {
939 mpp_err_f("send cmd failed %d\n", ret);
940 break;
941 }
942 } while (0);
943
944 __RETURN:
945 return ret = MPP_OK;
946 }
947
vdpu384a_h264d_wait(void * hal,HalTaskInfo * task)948 MPP_RET vdpu384a_h264d_wait(void *hal, HalTaskInfo *task)
949 {
950 MPP_RET ret = MPP_ERR_UNKNOW;
951 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
952
953 INP_CHECK(ret, NULL == p_hal);
954 Vdpu384aH264dRegCtx *reg_ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;
955 Vdpu384aH264dRegSet *p_regs = p_hal->fast_mode ?
956 reg_ctx->reg_buf[task->dec.reg_index].regs :
957 reg_ctx->regs;
958
959 if (task->dec.flags.parse_err ||
960 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
961 goto __SKIP_HARD;
962 }
963
964 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
965 if (ret)
966 mpp_err_f("poll cmd failed %d\n", ret);
967
968 __SKIP_HARD:
969 if (p_hal->dec_cb) {
970 DecCbHalDone param;
971
972 param.task = (void *)&task->dec;
973 param.regs = (RK_U32 *)p_regs;
974
975 if ((!p_regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) ||
976 p_regs->ctrl_regs.reg15.rkvdec_strm_error_sta ||
977 p_regs->ctrl_regs.reg15.rkvdec_core_timeout_sta ||
978 p_regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta ||
979 p_regs->ctrl_regs.reg15.rkvdec_bus_error_sta ||
980 p_regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta ||
981 p_regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta)
982 param.hard_err = 1;
983 else
984 param.hard_err = 0;
985
986 mpp_callback(p_hal->dec_cb, ¶m);
987 }
988 memset(&p_regs->ctrl_regs.reg19, 0, sizeof(RK_U32));
989 if (p_hal->fast_mode) {
990 reg_ctx->reg_buf[task->dec.reg_index].valid = 0;
991 }
992
993 (void)task;
994 __RETURN:
995 return ret = MPP_OK;
996 }
997
vdpu384a_h264d_reset(void * hal)998 MPP_RET vdpu384a_h264d_reset(void *hal)
999 {
1000 MPP_RET ret = MPP_ERR_UNKNOW;
1001 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1002
1003 INP_CHECK(ret, NULL == p_hal);
1004
1005
1006 __RETURN:
1007 return ret = MPP_OK;
1008 }
1009
vdpu384a_h264d_flush(void * hal)1010 MPP_RET vdpu384a_h264d_flush(void *hal)
1011 {
1012 MPP_RET ret = MPP_ERR_UNKNOW;
1013 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1014
1015 INP_CHECK(ret, NULL == p_hal);
1016
1017 __RETURN:
1018 return ret = MPP_OK;
1019 }
1020
vdpu384a_h264d_control(void * hal,MpiCmd cmd_type,void * param)1021 MPP_RET vdpu384a_h264d_control(void *hal, MpiCmd cmd_type, void *param)
1022 {
1023 MPP_RET ret = MPP_ERR_UNKNOW;
1024 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1025
1026 INP_CHECK(ret, NULL == p_hal);
1027
1028 switch ((MpiCmd)cmd_type) {
1029 case MPP_DEC_SET_FRAME_INFO: {
1030 MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param);
1031 RK_U32 imgwidth = mpp_frame_get_width((MppFrame)param);
1032 RK_U32 imgheight = mpp_frame_get_height((MppFrame)param);
1033
1034 mpp_log("control info: fmt %d, w %d, h %d\n", fmt, imgwidth, imgheight);
1035 if (fmt == MPP_FMT_YUV422SP) {
1036 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
1037 }
1038 if (MPP_FRAME_FMT_IS_FBC(fmt)) {
1039 vdpu384a_afbc_align_calc(p_hal->frame_slots, (MppFrame)param, 16);
1040 } else if (imgwidth > 1920 || imgheight > 1088) {
1041 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
1042 }
1043 } break;
1044 case MPP_DEC_GET_THUMBNAIL_FRAME_INFO: {
1045 vdpu384a_update_thumbnail_frame_info((MppFrame)param);
1046 } break;
1047 case MPP_DEC_SET_OUTPUT_FORMAT: {
1048 } break;
1049 default : {
1050 } break;
1051 }
1052
1053 __RETURN:
1054 return ret = MPP_OK;
1055 }
1056
1057 const MppHalApi hal_h264d_vdpu384a = {
1058 .name = "h264d_vdpu384a",
1059 .type = MPP_CTX_DEC,
1060 .coding = MPP_VIDEO_CodingAVC,
1061 .ctx_size = sizeof(Vdpu384aH264dRegCtx),
1062 .flag = 0,
1063 .init = vdpu384a_h264d_init,
1064 .deinit = vdpu384a_h264d_deinit,
1065 .reg_gen = vdpu384a_h264d_gen_regs,
1066 .start = vdpu384a_h264d_start,
1067 .wait = vdpu384a_h264d_wait,
1068 .reset = vdpu384a_h264d_reset,
1069 .flush = vdpu384a_h264d_flush,
1070 .control = vdpu384a_h264d_control,
1071 };
1072