51 #define SET_REF_HOR_VIRSTRIDE(regs, ref_index, value)\  argument
54         case 0: regs.reg83_ref0_hor_virstride = value; break;\
55         case 1: regs.reg86_ref1_hor_virstride = value; break;\
56         case 2: regs.reg89_ref2_hor_virstride = value; break;\
57         case 3: regs.reg92_ref3_hor_virstride = value; break;\
58         case 4: regs.reg95_ref4_hor_virstride = value; break;\
59         case 5: regs.reg98_ref5_hor_virstride = value; break;\
60         case 6: regs.reg101_ref6_hor_virstride = value; break;\
61         case 7: regs.reg104_ref7_hor_virstride = value; break;\
65 #define SET_REF_RASTER_UV_HOR_VIRSTRIDE(regs, ref_index, value)\  argument
68         case 0: regs.reg84_ref0_raster_uv_hor_virstride = value; break;\
69         case 1: regs.reg87_ref1_raster_uv_hor_virstride = value; break;\
70         case 2: regs.reg90_ref2_raster_uv_hor_virstride = value; break;\
71         case 3: regs.reg93_ref3_raster_uv_hor_virstride = value; break;\
72         case 4: regs.reg96_ref4_raster_uv_hor_virstride = value; break;\
73         case 5: regs.reg99_ref5_raster_uv_hor_virstride = value; break;\
74         case 6: regs.reg102_ref6_raster_uv_hor_virstride = value; break;\
75         case 7: regs.reg105_ref7_raster_uv_hor_virstride = value; break;\
79 #define SET_REF_VIRSTRIDE(regs, ref_index, value)\  argument
82         case 0: regs.reg85_ref0_virstride = value; break;\
83         case 1: regs.reg88_ref1_virstride = value; break;\
84         case 2: regs.reg91_ref2_virstride = value; break;\
85         case 3: regs.reg94_ref3_virstride = value; break;\
86         case 4: regs.reg97_ref4_virstride = value; break;\
87         case 5: regs.reg100_ref5_virstride = value; break;\
88         case 6: regs.reg103_ref6_virstride = value; break;\
89         case 7: regs.reg106_ref7_virstride = value; break;\
93 #define SET_REF_BASE(regs, ref_index, value)\  argument
96         case 0: regs.reg170_av1_last_base      = value; break; \
97         case 1: regs.reg171_av1golden_base     = value; break; \
98         case 2: regs.reg172_av1alfter_base     = value; break; \
99         case 3: regs.reg173_refer3_base        = value; break; \
100         case 4: regs.reg174_refer4_base        = value; break; \
101         case 5: regs.reg175_refer5_base        = value; break; \
102         case 6: regs.reg176_refer6_base        = value; break; \
103         case 7: regs.reg177_refer7_base        = value; break; \
107 #define SET_FBC_PAYLOAD_REF_BASE(regs, ref_index, value)\  argument
110         case 0: regs.reg195_payload_st_ref0_base    = value; break; \
111         case 1: regs.reg196_payload_st_ref1_base    = value; break; \
112         case 2: regs.reg197_payload_st_ref2_base    = value; break; \
113         case 3: regs.reg198_payload_st_ref3_base    = value; break; \
114         case 4: regs.reg199_payload_st_ref4_base    = value; break; \
115         case 5: regs.reg200_payload_st_ref5_base    = value; break; \
116         case 6: regs.reg201_payload_st_ref6_base    = value; break; \
117         case 7: regs.reg202_payload_st_ref7_base    = value; break; \
132     Vdpu383Av1dRegSet  *regs;  member
149     Vdpu383Av1dRegSet  *regs;  member
1314         reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu383Av1dRegSet, 1);  in hal_av1d_alloc_res()
1315         memset(reg_ctx->reg_buf[i].regs, 0, sizeof(Vdpu383Av1dRegSet));  in hal_av1d_alloc_res()
1320         reg_ctx->regs = reg_ctx->reg_buf[0].regs;  in hal_av1d_alloc_res()
1349         MPP_FREE(reg_ctx->reg_buf[i].regs);  in hal_av1d_release_res()
1957     Vdpu383Av1dRegSet *regs = reg_ctx->regs;  in vdpu383_av1d_rcb_reg_cfg()  local
1961     regs->common_addr.reg140_rcb_strmd_row_offset           = fd;  in vdpu383_av1d_rcb_reg_cfg()
1962     regs->common_addr.reg142_rcb_strmd_tile_row_offset      = fd;  in vdpu383_av1d_rcb_reg_cfg()
1963     regs->common_addr.reg144_rcb_inter_row_offset           = fd;  in vdpu383_av1d_rcb_reg_cfg()
1964     regs->common_addr.reg146_rcb_inter_tile_row_offset      = fd;  in vdpu383_av1d_rcb_reg_cfg()
1965     regs->common_addr.reg148_rcb_intra_row_offset           = fd;  in vdpu383_av1d_rcb_reg_cfg()
1966     regs->common_addr.reg150_rcb_intra_tile_row_offset      = fd;  in vdpu383_av1d_rcb_reg_cfg()
1967     regs->common_addr.reg152_rcb_filterd_row_offset         = fd;  in vdpu383_av1d_rcb_reg_cfg()
1968     regs->common_addr.reg154_rcb_filterd_protect_row_offset = fd;  in vdpu383_av1d_rcb_reg_cfg()
1969     regs->common_addr.reg156_rcb_filterd_tile_row_offset    = fd;  in vdpu383_av1d_rcb_reg_cfg()
1970     regs->common_addr.reg158_rcb_filterd_tile_col_offset    = fd;  in vdpu383_av1d_rcb_reg_cfg()
1971     regs->common_addr.reg160_rcb_filterd_av1_upscale_tile_col_offset = fd;  in vdpu383_av1d_rcb_reg_cfg()
1973 … regs->common_addr.reg141_rcb_strmd_row_len            = reg_ctx->rcb_buf_info[RCB_STRMD_ROW].size;  in vdpu383_av1d_rcb_reg_cfg()
1974 …regs->common_addr.reg143_rcb_strmd_tile_row_len       = reg_ctx->rcb_buf_info[RCB_STRMD_TILE_ROW].…  in vdpu383_av1d_rcb_reg_cfg()
1975 … regs->common_addr.reg145_rcb_inter_row_len            = reg_ctx->rcb_buf_info[RCB_INTER_ROW].size;  in vdpu383_av1d_rcb_reg_cfg()
1976 …regs->common_addr.reg147_rcb_inter_tile_row_len       = reg_ctx->rcb_buf_info[RCB_INTER_TILE_ROW].…  in vdpu383_av1d_rcb_reg_cfg()
1977 … regs->common_addr.reg149_rcb_intra_row_len            = reg_ctx->rcb_buf_info[RCB_INTRA_ROW].size;  in vdpu383_av1d_rcb_reg_cfg()
1978 …regs->common_addr.reg151_rcb_intra_tile_row_len       = reg_ctx->rcb_buf_info[RCB_INTRA_TILE_ROW].…  in vdpu383_av1d_rcb_reg_cfg()
1979 …regs->common_addr.reg153_rcb_filterd_row_len          = reg_ctx->rcb_buf_info[RCB_FILTERD_ROW].siz…  in vdpu383_av1d_rcb_reg_cfg()
1980 …regs->common_addr.reg155_rcb_filterd_protect_row_len  = reg_ctx->rcb_buf_info[RCB_FILTERD_PROTECT_…  in vdpu383_av1d_rcb_reg_cfg()
1981 …regs->common_addr.reg157_rcb_filterd_tile_row_len     = reg_ctx->rcb_buf_info[RCB_FILTERD_TILE_ROW…  in vdpu383_av1d_rcb_reg_cfg()
1982 …regs->common_addr.reg159_rcb_filterd_tile_col_len     = reg_ctx->rcb_buf_info[RCB_FILTERD_TILE_COL…  in vdpu383_av1d_rcb_reg_cfg()
1983 …regs->common_addr.reg161_rcb_filterd_av1_upscale_tile_col_len  = reg_ctx->rcb_buf_info[RCB_FILTERD…  in vdpu383_av1d_rcb_reg_cfg()
2074     Vdpu383Av1dRegSet *regs = reg_ctx->regs;  in vdpu383_av1d_set_cdf()  local
2099         regs->av1d_addrs.reg184_av1_noncoef_rd_base = mpp_buffer_get_fd(reg_ctx->cdf_rd_def_base);  in vdpu383_av1d_set_cdf()
2100         regs->av1d_addrs.reg178_av1_coef_rd_base = mpp_buffer_get_fd(reg_ctx->cdf_rd_def_base);  in vdpu383_av1d_set_cdf()
2123         regs->av1d_addrs.reg184_av1_noncoef_rd_base = mpp_buffer_get_fd(buf_tmp);  in vdpu383_av1d_set_cdf()
2124         regs->av1d_addrs.reg178_av1_coef_rd_base = mpp_buffer_get_fd(buf_tmp);  in vdpu383_av1d_set_cdf()
2125         regs->av1d_addrs.reg181_av1_rd_segid_base = mpp_buffer_get_fd(buf_tmp);  in vdpu383_av1d_set_cdf()
2137     regs->av1d_addrs.reg185_av1_noncoef_wr_base = mpp_buffer_get_fd(cdf_buf->buf[0]);  in vdpu383_av1d_set_cdf()
2138     regs->av1d_addrs.reg179_av1_coef_wr_base = mpp_buffer_get_fd(cdf_buf->buf[0]);  in vdpu383_av1d_set_cdf()
2139     regs->av1d_addrs.reg182_av1_wr_segid_base = mpp_buffer_get_fd(cdf_buf->buf[0]);  in vdpu383_av1d_set_cdf()
2180     Vdpu383Av1dRegSet *regs;  in vdpu383_av1d_gen_regs()  local
2207                 ctx->regs = ctx->reg_buf[i].regs;  in vdpu383_av1d_gen_regs()
2214     regs = ctx->regs;  in vdpu383_av1d_gen_regs()
2215     memset(regs, 0, sizeof(*regs));  in vdpu383_av1d_gen_regs()
2232         regs->ctrl_regs.reg8_dec_mode          = 4; // av1  in vdpu383_av1d_gen_regs()
2233         regs->ctrl_regs.reg9.fbc_e             = 0;  in vdpu383_av1d_gen_regs()
2234         regs->ctrl_regs.reg9.buf_empty_en      = 0;  in vdpu383_av1d_gen_regs()
2236         regs->ctrl_regs.reg10.strmd_auto_gating_e    = 1;  in vdpu383_av1d_gen_regs()
2237         regs->ctrl_regs.reg10.inter_auto_gating_e    = 1;  in vdpu383_av1d_gen_regs()
2238         regs->ctrl_regs.reg10.intra_auto_gating_e    = 1;  in vdpu383_av1d_gen_regs()
2239         regs->ctrl_regs.reg10.transd_auto_gating_e   = 1;  in vdpu383_av1d_gen_regs()
2240         regs->ctrl_regs.reg10.recon_auto_gating_e    = 1;  in vdpu383_av1d_gen_regs()
2241         regs->ctrl_regs.reg10.filterd_auto_gating_e  = 1;  in vdpu383_av1d_gen_regs()
2242         regs->ctrl_regs.reg10.bus_auto_gating_e      = 1;  in vdpu383_av1d_gen_regs()
2243         regs->ctrl_regs.reg10.ctrl_auto_gating_e     = 1;  in vdpu383_av1d_gen_regs()
2244         regs->ctrl_regs.reg10.rcb_auto_gating_e      = 1;  in vdpu383_av1d_gen_regs()
2245         regs->ctrl_regs.reg10.err_prc_auto_gating_e  = 1;  in vdpu383_av1d_gen_regs()
2249         regs->ctrl_regs.reg13_core_timeout_threshold  = 0x3fffff;  in vdpu383_av1d_gen_regs()
2251         regs->ctrl_regs.reg16.error_proc_disable     = 1;  in vdpu383_av1d_gen_regs()
2252         regs->ctrl_regs.reg16.error_spread_disable   = 0;  in vdpu383_av1d_gen_regs()
2253         regs->ctrl_regs.reg16.roi_error_ctu_cal_en   = 0;  in vdpu383_av1d_gen_regs()
2255         regs->ctrl_regs.reg20_cabac_error_en_lowbits  = 0xffffffdf;  in vdpu383_av1d_gen_regs()
2256         regs->ctrl_regs.reg21_cabac_error_en_highbits = 0x3fffffff;  in vdpu383_av1d_gen_regs()
2258         regs->ctrl_regs.reg28.axi_perf_work_e = 1;  in vdpu383_av1d_gen_regs()
2259         regs->ctrl_regs.reg28.axi_cnt_type    = 1;  in vdpu383_av1d_gen_regs()
2260         regs->ctrl_regs.reg28.rd_latency_id   = 11;  in vdpu383_av1d_gen_regs()
2262         regs->ctrl_regs.reg29.addr_align_type     = 1;  in vdpu383_av1d_gen_regs()
2263         regs->ctrl_regs.reg29.ar_cnt_id_type      = 0;  in vdpu383_av1d_gen_regs()
2264         regs->ctrl_regs.reg29.aw_cnt_id_type      = 1;  in vdpu383_av1d_gen_regs()
2265         regs->ctrl_regs.reg29.ar_count_id         = 17;  in vdpu383_av1d_gen_regs()
2266         regs->ctrl_regs.reg29.aw_count_id         = 0;  in vdpu383_av1d_gen_regs()
2267         regs->ctrl_regs.reg29.rd_band_width_mode  = 0;  in vdpu383_av1d_gen_regs()
2269         regs->ctrl_regs.reg30.axi_wr_qos = 0;  in vdpu383_av1d_gen_regs()
2270         regs->ctrl_regs.reg30.axi_rd_qos = 0;  in vdpu383_av1d_gen_regs()
2280         regs->av1d_paras.reg67_global_len = VDPU383_UNCMPS_HEADER_SIZE / 16; // 128 bit as unit  in vdpu383_av1d_gen_regs()
2281         regs->common_addr.reg131_gbl_base = ctx->bufs_fd;  in vdpu383_av1d_gen_regs()
2289                               8 * regs->av1d_paras.reg67_global_len * 16, 64, 0, 0);  in vdpu383_av1d_gen_regs()
2294         regs->av1d_paras.reg66_stream_len = MPP_ALIGN(p_hal->strm_len + 15, 128);  in vdpu383_av1d_gen_regs()
2296         regs->common_addr.reg128_strm_base = mpp_buffer_get_fd(mbuffer);  in vdpu383_av1d_gen_regs()
2297 …    regs->av1d_paras.reg65_strm_start_bit = (ctx->offset_uncomps & 0xf) * 8; // bit start to decode  in vdpu383_av1d_gen_regs()
2300         regs->av1d_addrs.reg169_error_ref_base = mpp_buffer_get_fd(mbuffer);  in vdpu383_av1d_gen_regs()
2344                 regs->ctrl_regs.reg9.fbc_e = 1;  in vdpu383_av1d_gen_regs()
2345                 regs->av1d_paras.reg68_hor_virstride = fbc_hdr_stride / 64;  in vdpu383_av1d_gen_regs()
2346                 fbd_offset = regs->av1d_paras.reg68_hor_virstride * h * 4;  in vdpu383_av1d_gen_regs()
2347                 regs->av1d_addrs.reg193_fbc_payload_offset = fbd_offset;  in vdpu383_av1d_gen_regs()
2349                 regs->ctrl_regs.reg9.tile_e = 1;  in vdpu383_av1d_gen_regs()
2350                 regs->av1d_paras.reg68_hor_virstride = MPP_ALIGN(hor_virstride * 6, 16) >> 4;  in vdpu383_av1d_gen_regs()
2351                 regs->av1d_paras.reg70_y_virstride = (y_virstride + uv_virstride) >> 4;  in vdpu383_av1d_gen_regs()
2353                 regs->ctrl_regs.reg9.fbc_e = 0;  in vdpu383_av1d_gen_regs()
2354                 regs->av1d_paras.reg68_hor_virstride = hor_virstride >> 4;  in vdpu383_av1d_gen_regs()
2355                 regs->av1d_paras.reg69_raster_uv_hor_virstride = hor_virstride >> 4;  in vdpu383_av1d_gen_regs()
2356                 regs->av1d_paras.reg70_y_virstride = y_virstride >> 4;  in vdpu383_av1d_gen_regs()
2359             regs->av1d_paras.reg80_error_ref_hor_virstride = regs->av1d_paras.reg68_hor_virstride;  in vdpu383_av1d_gen_regs()
2360 …regs->av1d_paras.reg81_error_ref_raster_uv_hor_virstride = regs->av1d_paras.reg69_raster_uv_hor_vi…  in vdpu383_av1d_gen_regs()
2361             regs->av1d_paras.reg82_error_ref_virstride = regs->av1d_paras.reg70_y_virstride;  in vdpu383_av1d_gen_regs()
2378                     SET_REF_HOR_VIRSTRIDE(regs->av1d_paras, mapped_idx, hor_virstride >> 4);  in vdpu383_av1d_gen_regs()
2379 …                 SET_REF_RASTER_UV_HOR_VIRSTRIDE(regs->av1d_paras, mapped_idx, hor_virstride >> 4);  in vdpu383_av1d_gen_regs()
2380                     SET_REF_VIRSTRIDE(regs->av1d_paras, mapped_idx, y_virstride >> 4);  in vdpu383_av1d_gen_regs()
2392         regs->av1d_addrs.reg168_decout_base = mpp_buffer_get_fd(mbuffer);  in vdpu383_av1d_gen_regs()
2393         regs->av1d_addrs.reg192_payload_st_cur_base = mpp_buffer_get_fd(mbuffer);  in vdpu383_av1d_gen_regs()
2405                     SET_REF_BASE(regs->av1d_addrs, mapped_idx, mpp_buffer_get_fd(mbuffer));  in vdpu383_av1d_gen_regs()
2406 …                SET_FBC_PAYLOAD_REF_BASE(regs->av1d_addrs, mapped_idx, mpp_buffer_get_fd(mbuffer));  in vdpu383_av1d_gen_regs()
2414         regs->av1d_addrs.reg216_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);  in vdpu383_av1d_gen_regs()
2421                 regs->av1d_addrs.reg217_232_colmv_ref_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);  in vdpu383_av1d_gen_regs()
2455             regs->common_addr.reg133_scale_down_base = fd;  in vdpu383_av1d_gen_regs()
2458             regs->av1d_addrs.reg168_decout_base = fd;  in vdpu383_av1d_gen_regs()
2459             regs->av1d_addrs.reg192_payload_st_cur_base = fd;  in vdpu383_av1d_gen_regs()
2460             regs->av1d_addrs.reg169_error_ref_base = fd;  in vdpu383_av1d_gen_regs()
2461             vdpu383_setup_down_scale(mframe, p_hal->dev, &regs->ctrl_regs,  in vdpu383_av1d_gen_regs()
2462                                      (void *)&regs->av1d_paras);  in vdpu383_av1d_gen_regs()
2465             regs->common_addr.reg133_scale_down_base = fd;  in vdpu383_av1d_gen_regs()
2466             vdpu383_setup_down_scale(mframe, p_hal->dev, &regs->ctrl_regs,  in vdpu383_av1d_gen_regs()
2467                                      (void *)&regs->av1d_paras);  in vdpu383_av1d_gen_regs()
2471             regs->ctrl_regs.reg9.scale_down_en = 0;  in vdpu383_av1d_gen_regs()
2491     Vdpu383Av1dRegSet *regs = p_hal->fast_mode ?  in vdpu383_av1d_start()  local
2492                               reg_ctx->reg_buf[task->dec.reg_index].regs :  in vdpu383_av1d_start()
2493                               reg_ctx->regs;  in vdpu383_av1d_start()
2499         wr_cfg.reg = &regs->ctrl_regs;  in vdpu383_av1d_start()
2500         wr_cfg.size = sizeof(regs->ctrl_regs);  in vdpu383_av1d_start()
2508         wr_cfg.reg = &regs->common_addr;  in vdpu383_av1d_start()
2509         wr_cfg.size = sizeof(regs->common_addr);  in vdpu383_av1d_start()
2517         wr_cfg.reg = &regs->av1d_paras;  in vdpu383_av1d_start()
2518         wr_cfg.size = sizeof(regs->av1d_paras);  in vdpu383_av1d_start()
2526         wr_cfg.reg = &regs->av1d_addrs;  in vdpu383_av1d_start()
2527         wr_cfg.size = sizeof(regs->av1d_addrs);  in vdpu383_av1d_start()
2535         rd_cfg.reg = &regs->ctrl_regs.reg15;  in vdpu383_av1d_start()
2536         rd_cfg.size = sizeof(regs->ctrl_regs.reg15);  in vdpu383_av1d_start()
2567                                 reg_ctx->reg_buf[task->dec.reg_index].regs :  in vdpu383_av1d_wait()
2568                                 reg_ctx->regs;  in vdpu383_av1d_wait()