1 /*
2 * Copyright 2015 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_vp8e_vepu1_v2"
18
19 #include <string.h>
20
21 #include "mpp_mem.h"
22 #include "mpp_rc.h"
23 #include "mpp_common.h"
24 #include "vp8e_syntax.h"
25
26 #include "hal_vp8e_base.h"
27 #include "hal_vp8e_vepu1_v2.h"
28 #include "hal_vp8e_vepu1_reg.h"
29 #include "hal_vp8e_debug.h"
30
31 #define SWREG_AMOUNT_VEPU1 (164)
32 #define HW_STATUS_MASK 0x58
33 #define HW_STATUS_BUFFER_FULL 0x20
34 #define HW_STATUS_FRAME_READY 0x04
35
vp8e_vpu_frame_start(void * hal)36 static MPP_RET vp8e_vpu_frame_start(void *hal)
37 {
38 RK_S32 i = 0;
39 HalVp8eCtx *ctx = (HalVp8eCtx *) hal;
40 Vp8eHwCfg *hw_cfg = &ctx->hw_cfg;
41 Vp8eVepu1Reg_t *regs = (Vp8eVepu1Reg_t *) ctx->regs;
42
43 memset(regs, 0, sizeof(Vp8eVepu1Reg_t));
44
45 regs->sw1.val = hw_cfg->irq_disable ? (regs->sw1.val | 0x02) :
46 (regs->sw1.val & 0xfffffffd);
47
48
49 if (hw_cfg->input_format < INPUT_RGB565)
50 regs->sw2.val = 0xd00f;
51
52 else if (hw_cfg->input_format < INPUT_RGB888)
53 regs->sw2.val = 0xd00f;
54 else
55 regs->sw2.val = 0x900e;
56
57 regs->sw5.base_stream = hw_cfg->output_strm_base;
58 mpp_dev_set_reg_offset(ctx->dev, 5, hw_cfg->output_strm_offset);
59
60 regs->sw6.base_control = hw_cfg->size_tbl_base;
61 regs->sw14.nal_size_write = (hw_cfg->size_tbl_base != 0);
62 regs->sw14.mv_write = (hw_cfg->mv_output_base != 0);
63
64 regs->sw7.base_ref_lum = hw_cfg->internal_img_lum_base_r[0];
65 regs->sw8.base_ref_chr = hw_cfg->internal_img_chr_base_r[0];
66 regs->sw9.base_rec_lum = hw_cfg->internal_img_lum_base_w;
67 regs->sw10.base_rec_chr = hw_cfg->internal_img_chr_base_w;
68
69 regs->sw11.base_in_lum = hw_cfg->input_lum_base;
70 if (hw_cfg->input_lum_offset)
71 mpp_dev_set_reg_offset(ctx->dev, 11, hw_cfg->input_lum_offset);
72
73 regs->sw12.base_in_cb = hw_cfg->input_cb_base;
74 if (hw_cfg->input_cb_offset)
75 mpp_dev_set_reg_offset(ctx->dev, 12, hw_cfg->input_cb_offset);
76
77 regs->sw13.base_in_cr = hw_cfg->input_cr_base;
78 if (hw_cfg->input_cr_offset)
79 mpp_dev_set_reg_offset(ctx->dev, 13, hw_cfg->input_cr_offset);
80
81 regs->sw14.int_timeout = 1;
82 regs->sw14.int_slice_ready = hw_cfg->int_slice_ready;
83 regs->sw14.rec_write_disable = hw_cfg->rec_write_disable;
84 regs->sw14.width = hw_cfg->mbs_in_row;
85 regs->sw14.height = hw_cfg->mbs_in_col;
86 regs->sw14.picture_type = hw_cfg->frame_coding_type;
87 regs->sw14.encoding_mode = hw_cfg->coding_type;
88
89 regs->sw15.chr_offset = hw_cfg->input_chroma_base_offset;
90 regs->sw15.lum_offset = hw_cfg->input_luma_base_offset;
91 regs->sw15.row_length = hw_cfg->pixels_on_row;
92 regs->sw15.x_fill = hw_cfg->x_fill;
93 regs->sw15.y_fill = hw_cfg->y_fill;
94 regs->sw15.input_format = hw_cfg->input_format;
95 regs->sw15.input_rot = hw_cfg->input_rotation;
96
97 regs->sw18.cabac_enable = hw_cfg->enable_cabac;
98 regs->sw18.ip_intra16_favor = hw_cfg->intra_16_favor;
99 regs->sw21.inter_favor = hw_cfg->inter_favor;
100 regs->sw18.disable_qp_mv = hw_cfg->disable_qp_mv;
101 regs->sw18.deblocking = hw_cfg->filter_disable;
102 regs->sw21.skip_penalty = hw_cfg->skip_penalty;
103 regs->sw19.split_mv = hw_cfg->split_mv_mode;
104 regs->sw20.split_penalty_16x8 = hw_cfg->split_penalty[0];
105 regs->sw20.split_penalty_8x8 = hw_cfg->split_penalty[1];
106 regs->sw20.split_penalty_8x4 = hw_cfg->split_penalty[2];
107 regs->sw62.split_penalty4x4 = hw_cfg->split_penalty[3];
108 regs->sw62.zero_mv_favor = hw_cfg->zero_mv_favor;
109
110 regs->sw22.strm_hdr_rem1 = hw_cfg->strm_start_msb;
111 regs->sw23.strm_hdr_rem2 = hw_cfg->strm_start_lsb;
112 regs->sw24.strm_buf_limit = hw_cfg->output_strm_size;
113
114 regs->sw16.base_ref_lum2 = hw_cfg->internal_img_lum_base_r[1];
115 regs->sw17.base_ref_chr2 = hw_cfg->internal_img_chr_base_r[1];
116
117 regs->sw27.y1_quant_dc = hw_cfg->y1_quant_dc[0];
118 regs->sw28.y1_quant_ac = hw_cfg->y1_quant_ac[0];
119 regs->sw29.y2_quant_dc = hw_cfg->y2_quant_dc[0];
120 regs->sw30.y2_quant_ac = hw_cfg->y2_quant_ac[0];
121 regs->sw31.ch_quant_dc = hw_cfg->ch_quant_dc[0];
122 regs->sw32.ch_quant_ac = hw_cfg->ch_quant_ac[0];
123
124 regs->sw27.y1_zbin_dc = hw_cfg->y1_zbin_dc[0];
125 regs->sw28.y1_zbin_ac = hw_cfg->y1_zbin_ac[0];
126 regs->sw29.y2_zbin_dc = hw_cfg->y2_zbin_dc[0];
127 regs->sw30.y2_zbin_ac = hw_cfg->y2_zbin_ac[0];
128 regs->sw31.ch_zbin_dc = hw_cfg->ch_zbin_dc[0];
129 regs->sw32.ch_zbin_ac = hw_cfg->ch_zbin_ac[0];
130
131 regs->sw27.y1_round_dc = hw_cfg->y1_round_dc[0];
132 regs->sw28.y1_round_ac = hw_cfg->y1_round_ac[0];
133 regs->sw29.y2_round_dc = hw_cfg->y2_round_dc[0];
134 regs->sw30.y2_round_ac = hw_cfg->y2_round_ac[0];
135 regs->sw31.ch_round_dc = hw_cfg->ch_round_dc[0];
136 regs->sw32.ch_round_ac = hw_cfg->ch_round_ac[0];
137
138 regs->sw33.y1_dequant_dc = hw_cfg->y1_dequant_dc[0];
139 regs->sw33.y1_dequant_ac = hw_cfg->y1_dequant_ac[0];
140 regs->sw33.y2_dequant_dc = hw_cfg->y2_dequant_dc[0];
141 regs->sw34.y2_dequant_ac = hw_cfg->y2_dequant_ac[0];
142 regs->sw34.ch_dequant_dc = hw_cfg->ch_dequant_dc[0];
143 regs->sw34.ch_dequant_ac = hw_cfg->ch_dequant_ac[0];
144
145 regs->sw33.mv_ref_idx = hw_cfg->mv_ref_idx[0];
146 regs->sw34.mv_ref_idx2 = hw_cfg->mv_ref_idx[1];
147 regs->sw34.ref2_enable = hw_cfg->ref2_enable;
148
149 regs->sw35.bool_enc_value = hw_cfg->bool_enc_value;
150 regs->sw36.bool_enc_value_bits = hw_cfg->bool_enc_value_bits;
151 regs->sw36.bool_enc_range = hw_cfg->bool_enc_range;
152
153 regs->sw36.filter_level = hw_cfg->filter_level[0];
154 regs->sw36.golden_penalty = hw_cfg->golden_penalty;
155 regs->sw36.filter_sharpness = hw_cfg->filter_sharpness;
156 regs->sw36.dct_partition_count = hw_cfg->dct_partitions;
157
158 regs->sw37.start_offset = hw_cfg->first_free_bit;
159
160 regs->sw39.base_next_lum = hw_cfg->vs_next_luma_base;
161 regs->sw40.stab_mode = hw_cfg->vs_mode;
162
163 regs->sw19.dmv_penalty4p = hw_cfg->diff_mv_penalty[0];
164 regs->sw19.dmv_penalty1p = hw_cfg->diff_mv_penalty[1];
165 regs->sw19.dmv_penaltyqp = hw_cfg->diff_mv_penalty[2];
166
167 regs->sw51.base_cabac_ctx = hw_cfg->cabac_tbl_base;
168 regs->sw52.base_mv_write = hw_cfg->mv_output_base;
169
170 regs->sw53.rgb_coeff_a = hw_cfg->rgb_coeff_a;
171 regs->sw53.rgb_coeff_b = hw_cfg->rgb_coeff_b;
172 regs->sw54.rgb_coeff_c = hw_cfg->rgb_coeff_c;
173 regs->sw54.rgb_coeff_e = hw_cfg->rgb_coeff_e;
174 regs->sw55.rgb_coeff_f = hw_cfg->rgb_coeff_f;
175
176 regs->sw55.r_mask_msb = hw_cfg->r_mask_msb;
177 regs->sw55.g_mask_msb = hw_cfg->g_mask_msb;
178 regs->sw55.b_mask_msb = hw_cfg->b_mask_msb;
179
180 regs->sw57.cir_start = hw_cfg->cir_start;
181 regs->sw57.cir_interval = hw_cfg->cir_interval;
182
183 regs->sw56.intra_area_left = hw_cfg->intra_area_left;
184 regs->sw56.intra_area_right = hw_cfg->intra_area_right;
185 regs->sw56.intra_area_top = hw_cfg->intra_area_top;
186 regs->sw56.intra_area_bottom = hw_cfg->intra_area_bottom;
187 regs->sw60.roi1_left = hw_cfg->roi1_left;
188 regs->sw60.roi1_right = hw_cfg->roi1_right;
189 regs->sw60.roi1_top = hw_cfg->roi1_top;
190 regs->sw60.roi1_bottom = hw_cfg->roi1_bottom;
191
192 regs->sw61.roi2_left = hw_cfg->roi2_left;
193 regs->sw61.roi2_right = hw_cfg->roi2_right;
194 regs->sw61.roi2_top = hw_cfg->roi2_top;
195 regs->sw61.roi2_bottom = hw_cfg->roi2_bottom;
196
197 regs->sw58.base_partition1 = hw_cfg->partition_Base[0];
198 mpp_dev_set_reg_offset(ctx->dev, 58, hw_cfg->partition_offset[0]);
199 regs->sw59.base_partition2 = hw_cfg->partition_Base[1];
200 mpp_dev_set_reg_offset(ctx->dev, 59, hw_cfg->partition_offset[1]);
201 regs->sw26.base_prob_count = hw_cfg->prob_count_base;
202
203 regs->sw64.mode0_penalty = hw_cfg->intra_mode_penalty[0];
204 regs->sw64.mode1_penalty = hw_cfg->intra_mode_penalty[1];
205 regs->sw65.mode2_penalty = hw_cfg->intra_mode_penalty[2];
206 regs->sw65.mode3_penalty = hw_cfg->intra_mode_penalty[3];
207
208 for (i = 0; i < 5; i++) {
209 regs->sw66_70[i].b_mode_0_penalty = hw_cfg->intra_b_mode_penalty[2 * i];
210 regs->sw66_70[i].b_mode_1_penalty = hw_cfg->intra_b_mode_penalty[2 * i + 1];
211 }
212
213 regs->sw34.segment_enable = hw_cfg->segment_enable;
214 regs->sw34.segment_map_update = hw_cfg->segment_map_update;
215 regs->sw71.base_segment_map = hw_cfg->segment_map_base;
216
217 for (i = 0; i < 3; i++) {
218 regs->sw72_95[0 + i * 8].num_0.y1_quant_dc = hw_cfg->y1_quant_dc[1 + i];
219 regs->sw72_95[0 + i * 8].num_0.y1_zbin_dc = hw_cfg->y1_zbin_dc[1 + i];
220 regs->sw72_95[0 + i * 8].num_0.y1_round_dc = hw_cfg->y1_round_dc[1 + i];
221
222 regs->sw72_95[1 + i * 8].num_1.y1_quant_ac = hw_cfg->y1_quant_ac[1 + i];
223 regs->sw72_95[1 + i * 8].num_1.y1_zbin_ac = hw_cfg->y1_zbin_ac[1 + i];
224 regs->sw72_95[1 + i * 8].num_1.y1_round_ac = hw_cfg->y1_round_ac[1 + i];
225
226 regs->sw72_95[2 + i * 8].num_2.y2_quant_dc = hw_cfg->y2_quant_dc[1 + i];
227 regs->sw72_95[2 + i * 8].num_2.y2_zbin_dc = hw_cfg->y2_zbin_dc[1 + i];
228 regs->sw72_95[2 + i * 8].num_2.y2_round_dc = hw_cfg->y2_round_dc[1 + i];
229
230 regs->sw72_95[3 + i * 8].num_3.y2_quant_ac = hw_cfg->y2_quant_ac[1 + i];
231 regs->sw72_95[3 + i * 8].num_3.y2_zbin_ac = hw_cfg->y2_zbin_ac[1 + i];
232 regs->sw72_95[3 + i * 8].num_3.y2_round_ac = hw_cfg->y2_round_ac[1 + i];
233
234 regs->sw72_95[4 + i * 8].num_4.ch_quant_dc = hw_cfg->ch_quant_dc[1 + i];
235 regs->sw72_95[4 + i * 8].num_4.ch_zbin_dc = hw_cfg->ch_zbin_dc[1 + i];
236 regs->sw72_95[4 + i * 8].num_4.ch_round_dc = hw_cfg->ch_round_dc[1 + i];
237
238 regs->sw72_95[5 + i * 8].num_5.ch_quant_ac = hw_cfg->ch_quant_ac[1 + i];
239 regs->sw72_95[5 + i * 8].num_5.ch_zbin_ac = hw_cfg->ch_zbin_ac[1 + i];
240 regs->sw72_95[5 + i * 8].num_5.ch_round_ac = hw_cfg->ch_round_ac[1 + i];
241
242 regs->sw72_95[6 + i * 8].num_6.y1_dequant_dc = hw_cfg->y1_dequant_dc[1 + i];
243 regs->sw72_95[6 + i * 8].num_6.y1_dequant_ac = hw_cfg->y1_dequant_ac[1 + i];
244 regs->sw72_95[6 + i * 8].num_6.y2_dequant_dc = hw_cfg->y2_dequant_dc[1 + i];
245
246 regs->sw72_95[7 + i * 8].num_7.y2_dequant_ac = hw_cfg->y2_dequant_ac[1 + i];
247 regs->sw72_95[7 + i * 8].num_7.ch_dequant_dc = hw_cfg->ch_dequant_dc[1 + i];
248 regs->sw72_95[7 + i * 8].num_7.ch_dequant_ac = hw_cfg->ch_dequant_ac[1 + i];
249 regs->sw72_95[7 + i * 8].num_7.filter_level = hw_cfg->filter_level[1 + i];
250
251 }
252
253 regs->sw162.lf_ref_delta0 = hw_cfg->lf_ref_delta[0] & mask_7b;
254 regs->sw162.lf_ref_delta1 = hw_cfg->lf_ref_delta[1] & mask_7b;
255 regs->sw162.lf_ref_delta2 = hw_cfg->lf_ref_delta[2] & mask_7b;
256 regs->sw162.lf_ref_delta3 = hw_cfg->lf_ref_delta[3] & mask_7b;
257 regs->sw163.lf_mode_delta0 = hw_cfg->lf_mode_delta[0] & mask_7b;
258 regs->sw163.lf_mode_delta1 = hw_cfg->lf_mode_delta[1] & mask_7b;
259 regs->sw163.lf_mode_delta2 = hw_cfg->lf_mode_delta[2] & mask_7b;
260 regs->sw163.lf_mode_delta3 = hw_cfg->lf_mode_delta[3] & mask_7b;
261
262 RK_S32 j = 0;
263
264 for (j = 0; j < 32; j++) {
265 regs->sw96_127[j].penalty_0 = hw_cfg->dmv_penalty[j * 4 + 3];
266 regs->sw96_127[j].penalty_1 = hw_cfg->dmv_penalty[j * 4 + 2];
267 regs->sw96_127[j].penalty_2 = hw_cfg->dmv_penalty[j * 4 + 1];
268 regs->sw96_127[j].penalty_3 = hw_cfg->dmv_penalty[j * 4];
269
270 regs->sw128_159[j].qpel_penalty_0 = hw_cfg->dmv_qpel_penalty[j * 4 + 3];
271 regs->sw128_159[j].qpel_penalty_1 = hw_cfg->dmv_qpel_penalty[j * 4 + 2];
272 regs->sw128_159[j].qpel_penalty_2 = hw_cfg->dmv_qpel_penalty[j * 4 + 1];
273 regs->sw128_159[j].qpel_penalty_3 = hw_cfg->dmv_qpel_penalty[j * 4];
274 }
275
276 regs->sw14.enable = 1;
277
278 return MPP_OK;
279 }
280
hal_vp8e_vepu1_init_v2(void * hal,MppEncHalCfg * cfg)281 static MPP_RET hal_vp8e_vepu1_init_v2(void *hal, MppEncHalCfg *cfg)
282 {
283 MPP_RET ret = MPP_OK;
284 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
285 Vp8eHwCfg *hw_cfg = &ctx->hw_cfg;
286
287 ctx->cfg = cfg->cfg;
288
289 /* update output to MppEnc */
290 cfg->type = VPU_CLIENT_VEPU1;
291 ret = mpp_dev_init(&cfg->dev, cfg->type);
292 if (ret) {
293 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
294 return ret;
295 }
296 ctx->dev = cfg->dev;
297
298 vp8e_hal_dbg(VP8E_DBG_HAL_FUNCTION, "mpp_dev_init success.\n");
299
300 ctx->buffers = mpp_calloc(Vp8eVpuBuf, 1);
301 if (ctx->buffers == NULL) {
302 mpp_err("failed to malloc buffers");
303 return MPP_ERR_NOMEM;
304 }
305 ctx->buffer_ready = 0;
306 ctx->frame_cnt = 0;
307 ctx->frame_type = VP8E_FRM_KEY;
308 ctx->prev_frame_lost = 0;
309 ctx->frame_size = 0;
310 ctx->ivf_hdr_rdy = 0;
311 ctx->reg_size = SWREG_AMOUNT_VEPU1;
312
313 hw_cfg->irq_disable = 0;
314
315 hw_cfg->rounding_ctrl = 0;
316 hw_cfg->cp_distance_mbs = 0;
317 hw_cfg->recon_img_id = 0;
318 hw_cfg->input_lum_base = 0;
319 hw_cfg->input_cb_base = 0;
320 hw_cfg->input_cr_base = 0;
321
322 hal_vp8e_init_qp_table(hal);
323
324 return ret;
325 }
326
hal_vp8e_vepu1_deinit_v2(void * hal)327 static MPP_RET hal_vp8e_vepu1_deinit_v2(void *hal)
328 {
329 MPP_RET ret = MPP_OK;
330 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
331
332 hal_vp8e_buf_free(ctx);
333
334 if (ctx->dev) {
335 mpp_dev_deinit(ctx->dev);
336 ctx->dev = NULL;
337 }
338
339 MPP_FREE(ctx->regs);
340 MPP_FREE(ctx->buffers);
341
342 vp8e_hal_dbg(VP8E_DBG_HAL_FUNCTION, "mpp_dev_deinit success.\n");
343
344 return ret;
345 }
346
hal_vp8e_vepu1_gen_regs_v2(void * hal,HalEncTask * task)347 static MPP_RET hal_vp8e_vepu1_gen_regs_v2(void *hal, HalEncTask *task)
348 {
349 MPP_RET ret = MPP_OK;
350 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
351
352 ctx->rc->qp_hdr = MPP_CLIP3(0, 127, task->rc_task->info.quality_target);
353
354 if (!ctx->buffer_ready) {
355 ret = hal_vp8e_setup(hal);
356 if (ret) {
357 mpp_err("failed to init hal vp8e\n");
358 return ret;
359 } else {
360 ctx->buffer_ready = 1;
361 }
362 }
363
364 memset(ctx->stream_size, 0, sizeof(ctx->stream_size));
365
366 hal_vp8e_enc_strm_code(ctx, task);
367 vp8e_vpu_frame_start(ctx);
368
369 return MPP_OK;
370 }
371
hal_vp8e_vepu1_start_v2(void * hal,HalEncTask * task)372 static MPP_RET hal_vp8e_vepu1_start_v2(void *hal, HalEncTask *task)
373 {
374 MPP_RET ret = MPP_OK;
375 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
376
377 if (VP8E_DBG_HAL_DUMP_REG & vp8e_hal_debug) {
378 RK_U32 i = 0;
379 RK_U32 *tmp = (RK_U32 *)ctx->regs;
380
381 for (; i < ctx->reg_size; i++)
382 mpp_log("reg[%d]:%x\n", i, tmp[i]);
383 }
384
385 do {
386 MppDevRegWrCfg wr_cfg;
387 MppDevRegRdCfg rd_cfg;
388 RK_U32 reg_size = ctx->reg_size * sizeof(RK_U32);
389
390 wr_cfg.reg = ctx->regs;
391 wr_cfg.size = reg_size;
392 wr_cfg.offset = 0;
393
394 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
395 if (ret) {
396 mpp_err_f("set register write failed %d\n", ret);
397 break;
398 }
399
400 rd_cfg.reg = ctx->regs;
401 rd_cfg.size = reg_size;
402 rd_cfg.offset = 0;
403
404 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
405 if (ret) {
406 mpp_err_f("set register read failed %d\n", ret);
407 break;
408 }
409
410 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
411 if (ret) {
412 mpp_err_f("send cmd failed %d\n", ret);
413 break;
414 }
415 } while (0);
416
417 (void)task;
418 return ret;
419 }
420
vp8e_update_hw_cfg(void * hal)421 static void vp8e_update_hw_cfg(void *hal)
422 {
423 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
424 Vp8eHwCfg *hw_cfg = &ctx->hw_cfg;
425 Vp8eVepu1Reg_t * regs = (Vp8eVepu1Reg_t *)ctx->regs;
426
427 hw_cfg->output_strm_base = regs->sw24.strm_buf_limit / 8;
428 hw_cfg->qp_sum = regs->sw25.qp_sum * 2;
429 hw_cfg->mad_count = regs->sw38.mad_count;
430 hw_cfg->rlc_count = regs->sw37.rlc_sum * 4;
431
432 hw_cfg->intra_16_favor = -1;
433 hw_cfg->inter_favor = -1;
434 hw_cfg->diff_mv_penalty[0] = -1;
435 hw_cfg->diff_mv_penalty[1] = -1;
436 hw_cfg->diff_mv_penalty[2] = -1;
437 hw_cfg->skip_penalty = -1;
438 hw_cfg->golden_penalty = -1;
439 hw_cfg->split_penalty[0] = 0;
440 hw_cfg->split_penalty[1] = 0;
441 hw_cfg->split_penalty[3] = 0;
442
443 }
444
hal_vp8e_vepu1_wait_v2(void * hal,HalEncTask * task)445 static MPP_RET hal_vp8e_vepu1_wait_v2(void *hal, HalEncTask *task)
446 {
447 MPP_RET ret;
448 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
449
450 Vp8eFeedback *fb = &ctx->feedback;
451 Vp8eVepu1Reg_t *regs = (Vp8eVepu1Reg_t *)ctx->regs;
452 RK_S32 sw_length = task->length;
453
454 if (NULL == ctx->dev) {
455 mpp_err_f("invalid dev ctx\n");
456 return MPP_NOK;
457 }
458
459 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
460 if (ret)
461 mpp_err_f("poll cmd failed %d\n", ret);
462
463 fb->hw_status = regs->sw1.val & HW_STATUS_MASK;
464 if (regs->sw1.val & HW_STATUS_FRAME_READY)
465 vp8e_update_hw_cfg(ctx);
466 else if (regs->sw1.val & HW_STATUS_BUFFER_FULL)
467 ctx->bitbuf[1].size = 0;
468
469 hal_vp8e_update_buffers(ctx, task);
470
471 ctx->last_frm_intra = task->rc_task->frm.is_intra;
472 ctx->frame_cnt++;
473
474 task->rc_task->info.bit_real = ctx->frame_size << 3;
475 task->hw_length = task->length - sw_length;
476
477 return ret;
478 }
479
hal_vp8e_vepu1_get_task_v2(void * hal,HalEncTask * task)480 static MPP_RET hal_vp8e_vepu1_get_task_v2(void *hal, HalEncTask *task)
481 {
482 HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
483 Vp8eSyntax* syntax = (Vp8eSyntax*)task->syntax.data;
484 //ctx->cfg = syntax->cfg;
485 RK_U32 i;
486
487 for (i = 0; i < task->syntax.number; i++) {
488 if (syntax[i].type == VP8E_SYN_CFG) {
489 ctx->cfg = (MppEncCfgSet*)syntax[i].data;
490 }
491 if (syntax[i].type == VP8E_SYN_RC) {
492 ctx->rc = (Vp8eRc*) syntax[i].data;
493 }
494 }
495
496 ctx->frame_type = task->rc_task->frm.is_intra ? VP8E_FRM_KEY : VP8E_FRM_P;
497
498 if (!ctx->cfg->vp8.disable_ivf && !ctx->ivf_hdr_rdy) {
499 RK_U8 *p_out = mpp_buffer_get_ptr(task->output);
500
501 write_ivf_header(hal, p_out);
502 task->length += IVF_HDR_BYTES;
503
504 ctx->ivf_hdr_rdy = 1;
505 }
506
507 return MPP_OK;
508 }
509
hal_vp8e_vepu1_ret_task_v2(void * hal,HalEncTask * task)510 static MPP_RET hal_vp8e_vepu1_ret_task_v2(void *hal, HalEncTask *task)
511 {
512 (void)hal;
513 (void)task;
514
515 return MPP_OK;
516 }
517
518 const MppEncHalApi hal_vp8e_vepu1 = {
519 .name = "hal_vp8e_vepu1",
520 .coding = MPP_VIDEO_CodingVP8,
521 .ctx_size = sizeof(HalVp8eCtx),
522 .flag = 0,
523 .init = hal_vp8e_vepu1_init_v2,
524 .deinit = hal_vp8e_vepu1_deinit_v2,
525 .prepare = NULL,
526 .get_task = hal_vp8e_vepu1_get_task_v2,
527 .gen_regs = hal_vp8e_vepu1_gen_regs_v2,
528 .start = hal_vp8e_vepu1_start_v2,
529 .wait = hal_vp8e_vepu1_wait_v2,
530 .part_start = NULL,
531 .part_wait = NULL,
532 .ret_task = hal_vp8e_vepu1_ret_task_v2,
533 };
534