Lines Matching refs:regs
41 Vp8eVepu1Reg_t *regs = (Vp8eVepu1Reg_t *) ctx->regs; in vp8e_vpu_frame_start() local
43 memset(regs, 0, sizeof(Vp8eVepu1Reg_t)); in vp8e_vpu_frame_start()
45 regs->sw1.val = hw_cfg->irq_disable ? (regs->sw1.val | 0x02) : in vp8e_vpu_frame_start()
46 (regs->sw1.val & 0xfffffffd); in vp8e_vpu_frame_start()
50 regs->sw2.val = 0xd00f; in vp8e_vpu_frame_start()
53 regs->sw2.val = 0xd00f; in vp8e_vpu_frame_start()
55 regs->sw2.val = 0x900e; in vp8e_vpu_frame_start()
57 regs->sw5.base_stream = hw_cfg->output_strm_base; in vp8e_vpu_frame_start()
60 regs->sw6.base_control = hw_cfg->size_tbl_base; in vp8e_vpu_frame_start()
61 regs->sw14.nal_size_write = (hw_cfg->size_tbl_base != 0); in vp8e_vpu_frame_start()
62 regs->sw14.mv_write = (hw_cfg->mv_output_base != 0); in vp8e_vpu_frame_start()
64 regs->sw7.base_ref_lum = hw_cfg->internal_img_lum_base_r[0]; in vp8e_vpu_frame_start()
65 regs->sw8.base_ref_chr = hw_cfg->internal_img_chr_base_r[0]; in vp8e_vpu_frame_start()
66 regs->sw9.base_rec_lum = hw_cfg->internal_img_lum_base_w; in vp8e_vpu_frame_start()
67 regs->sw10.base_rec_chr = hw_cfg->internal_img_chr_base_w; in vp8e_vpu_frame_start()
69 regs->sw11.base_in_lum = hw_cfg->input_lum_base; in vp8e_vpu_frame_start()
73 regs->sw12.base_in_cb = hw_cfg->input_cb_base; in vp8e_vpu_frame_start()
77 regs->sw13.base_in_cr = hw_cfg->input_cr_base; in vp8e_vpu_frame_start()
81 regs->sw14.int_timeout = 1; in vp8e_vpu_frame_start()
82 regs->sw14.int_slice_ready = hw_cfg->int_slice_ready; in vp8e_vpu_frame_start()
83 regs->sw14.rec_write_disable = hw_cfg->rec_write_disable; in vp8e_vpu_frame_start()
84 regs->sw14.width = hw_cfg->mbs_in_row; in vp8e_vpu_frame_start()
85 regs->sw14.height = hw_cfg->mbs_in_col; in vp8e_vpu_frame_start()
86 regs->sw14.picture_type = hw_cfg->frame_coding_type; in vp8e_vpu_frame_start()
87 regs->sw14.encoding_mode = hw_cfg->coding_type; in vp8e_vpu_frame_start()
89 regs->sw15.chr_offset = hw_cfg->input_chroma_base_offset; in vp8e_vpu_frame_start()
90 regs->sw15.lum_offset = hw_cfg->input_luma_base_offset; in vp8e_vpu_frame_start()
91 regs->sw15.row_length = hw_cfg->pixels_on_row; in vp8e_vpu_frame_start()
92 regs->sw15.x_fill = hw_cfg->x_fill; in vp8e_vpu_frame_start()
93 regs->sw15.y_fill = hw_cfg->y_fill; in vp8e_vpu_frame_start()
94 regs->sw15.input_format = hw_cfg->input_format; in vp8e_vpu_frame_start()
95 regs->sw15.input_rot = hw_cfg->input_rotation; in vp8e_vpu_frame_start()
97 regs->sw18.cabac_enable = hw_cfg->enable_cabac; in vp8e_vpu_frame_start()
98 regs->sw18.ip_intra16_favor = hw_cfg->intra_16_favor; in vp8e_vpu_frame_start()
99 regs->sw21.inter_favor = hw_cfg->inter_favor; in vp8e_vpu_frame_start()
100 regs->sw18.disable_qp_mv = hw_cfg->disable_qp_mv; in vp8e_vpu_frame_start()
101 regs->sw18.deblocking = hw_cfg->filter_disable; in vp8e_vpu_frame_start()
102 regs->sw21.skip_penalty = hw_cfg->skip_penalty; in vp8e_vpu_frame_start()
103 regs->sw19.split_mv = hw_cfg->split_mv_mode; in vp8e_vpu_frame_start()
104 regs->sw20.split_penalty_16x8 = hw_cfg->split_penalty[0]; in vp8e_vpu_frame_start()
105 regs->sw20.split_penalty_8x8 = hw_cfg->split_penalty[1]; in vp8e_vpu_frame_start()
106 regs->sw20.split_penalty_8x4 = hw_cfg->split_penalty[2]; in vp8e_vpu_frame_start()
107 regs->sw62.split_penalty4x4 = hw_cfg->split_penalty[3]; in vp8e_vpu_frame_start()
108 regs->sw62.zero_mv_favor = hw_cfg->zero_mv_favor; in vp8e_vpu_frame_start()
110 regs->sw22.strm_hdr_rem1 = hw_cfg->strm_start_msb; in vp8e_vpu_frame_start()
111 regs->sw23.strm_hdr_rem2 = hw_cfg->strm_start_lsb; in vp8e_vpu_frame_start()
112 regs->sw24.strm_buf_limit = hw_cfg->output_strm_size; in vp8e_vpu_frame_start()
114 regs->sw16.base_ref_lum2 = hw_cfg->internal_img_lum_base_r[1]; in vp8e_vpu_frame_start()
115 regs->sw17.base_ref_chr2 = hw_cfg->internal_img_chr_base_r[1]; in vp8e_vpu_frame_start()
117 regs->sw27.y1_quant_dc = hw_cfg->y1_quant_dc[0]; in vp8e_vpu_frame_start()
118 regs->sw28.y1_quant_ac = hw_cfg->y1_quant_ac[0]; in vp8e_vpu_frame_start()
119 regs->sw29.y2_quant_dc = hw_cfg->y2_quant_dc[0]; in vp8e_vpu_frame_start()
120 regs->sw30.y2_quant_ac = hw_cfg->y2_quant_ac[0]; in vp8e_vpu_frame_start()
121 regs->sw31.ch_quant_dc = hw_cfg->ch_quant_dc[0]; in vp8e_vpu_frame_start()
122 regs->sw32.ch_quant_ac = hw_cfg->ch_quant_ac[0]; in vp8e_vpu_frame_start()
124 regs->sw27.y1_zbin_dc = hw_cfg->y1_zbin_dc[0]; in vp8e_vpu_frame_start()
125 regs->sw28.y1_zbin_ac = hw_cfg->y1_zbin_ac[0]; in vp8e_vpu_frame_start()
126 regs->sw29.y2_zbin_dc = hw_cfg->y2_zbin_dc[0]; in vp8e_vpu_frame_start()
127 regs->sw30.y2_zbin_ac = hw_cfg->y2_zbin_ac[0]; in vp8e_vpu_frame_start()
128 regs->sw31.ch_zbin_dc = hw_cfg->ch_zbin_dc[0]; in vp8e_vpu_frame_start()
129 regs->sw32.ch_zbin_ac = hw_cfg->ch_zbin_ac[0]; in vp8e_vpu_frame_start()
131 regs->sw27.y1_round_dc = hw_cfg->y1_round_dc[0]; in vp8e_vpu_frame_start()
132 regs->sw28.y1_round_ac = hw_cfg->y1_round_ac[0]; in vp8e_vpu_frame_start()
133 regs->sw29.y2_round_dc = hw_cfg->y2_round_dc[0]; in vp8e_vpu_frame_start()
134 regs->sw30.y2_round_ac = hw_cfg->y2_round_ac[0]; in vp8e_vpu_frame_start()
135 regs->sw31.ch_round_dc = hw_cfg->ch_round_dc[0]; in vp8e_vpu_frame_start()
136 regs->sw32.ch_round_ac = hw_cfg->ch_round_ac[0]; in vp8e_vpu_frame_start()
138 regs->sw33.y1_dequant_dc = hw_cfg->y1_dequant_dc[0]; in vp8e_vpu_frame_start()
139 regs->sw33.y1_dequant_ac = hw_cfg->y1_dequant_ac[0]; in vp8e_vpu_frame_start()
140 regs->sw33.y2_dequant_dc = hw_cfg->y2_dequant_dc[0]; in vp8e_vpu_frame_start()
141 regs->sw34.y2_dequant_ac = hw_cfg->y2_dequant_ac[0]; in vp8e_vpu_frame_start()
142 regs->sw34.ch_dequant_dc = hw_cfg->ch_dequant_dc[0]; in vp8e_vpu_frame_start()
143 regs->sw34.ch_dequant_ac = hw_cfg->ch_dequant_ac[0]; in vp8e_vpu_frame_start()
145 regs->sw33.mv_ref_idx = hw_cfg->mv_ref_idx[0]; in vp8e_vpu_frame_start()
146 regs->sw34.mv_ref_idx2 = hw_cfg->mv_ref_idx[1]; in vp8e_vpu_frame_start()
147 regs->sw34.ref2_enable = hw_cfg->ref2_enable; in vp8e_vpu_frame_start()
149 regs->sw35.bool_enc_value = hw_cfg->bool_enc_value; in vp8e_vpu_frame_start()
150 regs->sw36.bool_enc_value_bits = hw_cfg->bool_enc_value_bits; in vp8e_vpu_frame_start()
151 regs->sw36.bool_enc_range = hw_cfg->bool_enc_range; in vp8e_vpu_frame_start()
153 regs->sw36.filter_level = hw_cfg->filter_level[0]; in vp8e_vpu_frame_start()
154 regs->sw36.golden_penalty = hw_cfg->golden_penalty; in vp8e_vpu_frame_start()
155 regs->sw36.filter_sharpness = hw_cfg->filter_sharpness; in vp8e_vpu_frame_start()
156 regs->sw36.dct_partition_count = hw_cfg->dct_partitions; in vp8e_vpu_frame_start()
158 regs->sw37.start_offset = hw_cfg->first_free_bit; in vp8e_vpu_frame_start()
160 regs->sw39.base_next_lum = hw_cfg->vs_next_luma_base; in vp8e_vpu_frame_start()
161 regs->sw40.stab_mode = hw_cfg->vs_mode; in vp8e_vpu_frame_start()
163 regs->sw19.dmv_penalty4p = hw_cfg->diff_mv_penalty[0]; in vp8e_vpu_frame_start()
164 regs->sw19.dmv_penalty1p = hw_cfg->diff_mv_penalty[1]; in vp8e_vpu_frame_start()
165 regs->sw19.dmv_penaltyqp = hw_cfg->diff_mv_penalty[2]; in vp8e_vpu_frame_start()
167 regs->sw51.base_cabac_ctx = hw_cfg->cabac_tbl_base; in vp8e_vpu_frame_start()
168 regs->sw52.base_mv_write = hw_cfg->mv_output_base; in vp8e_vpu_frame_start()
170 regs->sw53.rgb_coeff_a = hw_cfg->rgb_coeff_a; in vp8e_vpu_frame_start()
171 regs->sw53.rgb_coeff_b = hw_cfg->rgb_coeff_b; in vp8e_vpu_frame_start()
172 regs->sw54.rgb_coeff_c = hw_cfg->rgb_coeff_c; in vp8e_vpu_frame_start()
173 regs->sw54.rgb_coeff_e = hw_cfg->rgb_coeff_e; in vp8e_vpu_frame_start()
174 regs->sw55.rgb_coeff_f = hw_cfg->rgb_coeff_f; in vp8e_vpu_frame_start()
176 regs->sw55.r_mask_msb = hw_cfg->r_mask_msb; in vp8e_vpu_frame_start()
177 regs->sw55.g_mask_msb = hw_cfg->g_mask_msb; in vp8e_vpu_frame_start()
178 regs->sw55.b_mask_msb = hw_cfg->b_mask_msb; in vp8e_vpu_frame_start()
180 regs->sw57.cir_start = hw_cfg->cir_start; in vp8e_vpu_frame_start()
181 regs->sw57.cir_interval = hw_cfg->cir_interval; in vp8e_vpu_frame_start()
183 regs->sw56.intra_area_left = hw_cfg->intra_area_left; in vp8e_vpu_frame_start()
184 regs->sw56.intra_area_right = hw_cfg->intra_area_right; in vp8e_vpu_frame_start()
185 regs->sw56.intra_area_top = hw_cfg->intra_area_top; in vp8e_vpu_frame_start()
186 regs->sw56.intra_area_bottom = hw_cfg->intra_area_bottom; in vp8e_vpu_frame_start()
187 regs->sw60.roi1_left = hw_cfg->roi1_left; in vp8e_vpu_frame_start()
188 regs->sw60.roi1_right = hw_cfg->roi1_right; in vp8e_vpu_frame_start()
189 regs->sw60.roi1_top = hw_cfg->roi1_top; in vp8e_vpu_frame_start()
190 regs->sw60.roi1_bottom = hw_cfg->roi1_bottom; in vp8e_vpu_frame_start()
192 regs->sw61.roi2_left = hw_cfg->roi2_left; in vp8e_vpu_frame_start()
193 regs->sw61.roi2_right = hw_cfg->roi2_right; in vp8e_vpu_frame_start()
194 regs->sw61.roi2_top = hw_cfg->roi2_top; in vp8e_vpu_frame_start()
195 regs->sw61.roi2_bottom = hw_cfg->roi2_bottom; in vp8e_vpu_frame_start()
197 regs->sw58.base_partition1 = hw_cfg->partition_Base[0]; in vp8e_vpu_frame_start()
199 regs->sw59.base_partition2 = hw_cfg->partition_Base[1]; in vp8e_vpu_frame_start()
201 regs->sw26.base_prob_count = hw_cfg->prob_count_base; in vp8e_vpu_frame_start()
203 regs->sw64.mode0_penalty = hw_cfg->intra_mode_penalty[0]; in vp8e_vpu_frame_start()
204 regs->sw64.mode1_penalty = hw_cfg->intra_mode_penalty[1]; in vp8e_vpu_frame_start()
205 regs->sw65.mode2_penalty = hw_cfg->intra_mode_penalty[2]; in vp8e_vpu_frame_start()
206 regs->sw65.mode3_penalty = hw_cfg->intra_mode_penalty[3]; in vp8e_vpu_frame_start()
209 regs->sw66_70[i].b_mode_0_penalty = hw_cfg->intra_b_mode_penalty[2 * i]; in vp8e_vpu_frame_start()
210 regs->sw66_70[i].b_mode_1_penalty = hw_cfg->intra_b_mode_penalty[2 * i + 1]; in vp8e_vpu_frame_start()
213 regs->sw34.segment_enable = hw_cfg->segment_enable; in vp8e_vpu_frame_start()
214 regs->sw34.segment_map_update = hw_cfg->segment_map_update; in vp8e_vpu_frame_start()
215 regs->sw71.base_segment_map = hw_cfg->segment_map_base; in vp8e_vpu_frame_start()
218 regs->sw72_95[0 + i * 8].num_0.y1_quant_dc = hw_cfg->y1_quant_dc[1 + i]; in vp8e_vpu_frame_start()
219 regs->sw72_95[0 + i * 8].num_0.y1_zbin_dc = hw_cfg->y1_zbin_dc[1 + i]; in vp8e_vpu_frame_start()
220 regs->sw72_95[0 + i * 8].num_0.y1_round_dc = hw_cfg->y1_round_dc[1 + i]; in vp8e_vpu_frame_start()
222 regs->sw72_95[1 + i * 8].num_1.y1_quant_ac = hw_cfg->y1_quant_ac[1 + i]; in vp8e_vpu_frame_start()
223 regs->sw72_95[1 + i * 8].num_1.y1_zbin_ac = hw_cfg->y1_zbin_ac[1 + i]; in vp8e_vpu_frame_start()
224 regs->sw72_95[1 + i * 8].num_1.y1_round_ac = hw_cfg->y1_round_ac[1 + i]; in vp8e_vpu_frame_start()
226 regs->sw72_95[2 + i * 8].num_2.y2_quant_dc = hw_cfg->y2_quant_dc[1 + i]; in vp8e_vpu_frame_start()
227 regs->sw72_95[2 + i * 8].num_2.y2_zbin_dc = hw_cfg->y2_zbin_dc[1 + i]; in vp8e_vpu_frame_start()
228 regs->sw72_95[2 + i * 8].num_2.y2_round_dc = hw_cfg->y2_round_dc[1 + i]; in vp8e_vpu_frame_start()
230 regs->sw72_95[3 + i * 8].num_3.y2_quant_ac = hw_cfg->y2_quant_ac[1 + i]; in vp8e_vpu_frame_start()
231 regs->sw72_95[3 + i * 8].num_3.y2_zbin_ac = hw_cfg->y2_zbin_ac[1 + i]; in vp8e_vpu_frame_start()
232 regs->sw72_95[3 + i * 8].num_3.y2_round_ac = hw_cfg->y2_round_ac[1 + i]; in vp8e_vpu_frame_start()
234 regs->sw72_95[4 + i * 8].num_4.ch_quant_dc = hw_cfg->ch_quant_dc[1 + i]; in vp8e_vpu_frame_start()
235 regs->sw72_95[4 + i * 8].num_4.ch_zbin_dc = hw_cfg->ch_zbin_dc[1 + i]; in vp8e_vpu_frame_start()
236 regs->sw72_95[4 + i * 8].num_4.ch_round_dc = hw_cfg->ch_round_dc[1 + i]; in vp8e_vpu_frame_start()
238 regs->sw72_95[5 + i * 8].num_5.ch_quant_ac = hw_cfg->ch_quant_ac[1 + i]; in vp8e_vpu_frame_start()
239 regs->sw72_95[5 + i * 8].num_5.ch_zbin_ac = hw_cfg->ch_zbin_ac[1 + i]; in vp8e_vpu_frame_start()
240 regs->sw72_95[5 + i * 8].num_5.ch_round_ac = hw_cfg->ch_round_ac[1 + i]; in vp8e_vpu_frame_start()
242 regs->sw72_95[6 + i * 8].num_6.y1_dequant_dc = hw_cfg->y1_dequant_dc[1 + i]; in vp8e_vpu_frame_start()
243 regs->sw72_95[6 + i * 8].num_6.y1_dequant_ac = hw_cfg->y1_dequant_ac[1 + i]; in vp8e_vpu_frame_start()
244 regs->sw72_95[6 + i * 8].num_6.y2_dequant_dc = hw_cfg->y2_dequant_dc[1 + i]; in vp8e_vpu_frame_start()
246 regs->sw72_95[7 + i * 8].num_7.y2_dequant_ac = hw_cfg->y2_dequant_ac[1 + i]; in vp8e_vpu_frame_start()
247 regs->sw72_95[7 + i * 8].num_7.ch_dequant_dc = hw_cfg->ch_dequant_dc[1 + i]; in vp8e_vpu_frame_start()
248 regs->sw72_95[7 + i * 8].num_7.ch_dequant_ac = hw_cfg->ch_dequant_ac[1 + i]; in vp8e_vpu_frame_start()
249 regs->sw72_95[7 + i * 8].num_7.filter_level = hw_cfg->filter_level[1 + i]; in vp8e_vpu_frame_start()
253 regs->sw162.lf_ref_delta0 = hw_cfg->lf_ref_delta[0] & mask_7b; in vp8e_vpu_frame_start()
254 regs->sw162.lf_ref_delta1 = hw_cfg->lf_ref_delta[1] & mask_7b; in vp8e_vpu_frame_start()
255 regs->sw162.lf_ref_delta2 = hw_cfg->lf_ref_delta[2] & mask_7b; in vp8e_vpu_frame_start()
256 regs->sw162.lf_ref_delta3 = hw_cfg->lf_ref_delta[3] & mask_7b; in vp8e_vpu_frame_start()
257 regs->sw163.lf_mode_delta0 = hw_cfg->lf_mode_delta[0] & mask_7b; in vp8e_vpu_frame_start()
258 regs->sw163.lf_mode_delta1 = hw_cfg->lf_mode_delta[1] & mask_7b; in vp8e_vpu_frame_start()
259 regs->sw163.lf_mode_delta2 = hw_cfg->lf_mode_delta[2] & mask_7b; in vp8e_vpu_frame_start()
260 regs->sw163.lf_mode_delta3 = hw_cfg->lf_mode_delta[3] & mask_7b; in vp8e_vpu_frame_start()
265 regs->sw96_127[j].penalty_0 = hw_cfg->dmv_penalty[j * 4 + 3]; in vp8e_vpu_frame_start()
266 regs->sw96_127[j].penalty_1 = hw_cfg->dmv_penalty[j * 4 + 2]; in vp8e_vpu_frame_start()
267 regs->sw96_127[j].penalty_2 = hw_cfg->dmv_penalty[j * 4 + 1]; in vp8e_vpu_frame_start()
268 regs->sw96_127[j].penalty_3 = hw_cfg->dmv_penalty[j * 4]; in vp8e_vpu_frame_start()
270 regs->sw128_159[j].qpel_penalty_0 = hw_cfg->dmv_qpel_penalty[j * 4 + 3]; in vp8e_vpu_frame_start()
271 regs->sw128_159[j].qpel_penalty_1 = hw_cfg->dmv_qpel_penalty[j * 4 + 2]; in vp8e_vpu_frame_start()
272 regs->sw128_159[j].qpel_penalty_2 = hw_cfg->dmv_qpel_penalty[j * 4 + 1]; in vp8e_vpu_frame_start()
273 regs->sw128_159[j].qpel_penalty_3 = hw_cfg->dmv_qpel_penalty[j * 4]; in vp8e_vpu_frame_start()
276 regs->sw14.enable = 1; in vp8e_vpu_frame_start()
339 MPP_FREE(ctx->regs); in hal_vp8e_vepu1_deinit_v2()
379 RK_U32 *tmp = (RK_U32 *)ctx->regs; in hal_vp8e_vepu1_start_v2()
390 wr_cfg.reg = ctx->regs; in hal_vp8e_vepu1_start_v2()
400 rd_cfg.reg = ctx->regs; in hal_vp8e_vepu1_start_v2()
425 Vp8eVepu1Reg_t * regs = (Vp8eVepu1Reg_t *)ctx->regs; in vp8e_update_hw_cfg() local
427 hw_cfg->output_strm_base = regs->sw24.strm_buf_limit / 8; in vp8e_update_hw_cfg()
428 hw_cfg->qp_sum = regs->sw25.qp_sum * 2; in vp8e_update_hw_cfg()
429 hw_cfg->mad_count = regs->sw38.mad_count; in vp8e_update_hw_cfg()
430 hw_cfg->rlc_count = regs->sw37.rlc_sum * 4; in vp8e_update_hw_cfg()
451 Vp8eVepu1Reg_t *regs = (Vp8eVepu1Reg_t *)ctx->regs; in hal_vp8e_vepu1_wait_v2() local
463 fb->hw_status = regs->sw1.val & HW_STATUS_MASK; in hal_vp8e_vepu1_wait_v2()
464 if (regs->sw1.val & HW_STATUS_FRAME_READY) in hal_vp8e_vepu1_wait_v2()
466 else if (regs->sw1.val & HW_STATUS_BUFFER_FULL) in hal_vp8e_vepu1_wait_v2()