Lines Matching refs:regs
42 Vp8eVepu2Reg_t *regs = (Vp8eVepu2Reg_t *)ctx->regs; in vp8e_vpu_frame_start() local
44 memset(regs, 0, sizeof(Vp8eVepu2Reg_t)); in vp8e_vpu_frame_start()
46 regs->sw109.val = hw_cfg->irq_disable ? (regs->sw109.val | 0x0100) : in vp8e_vpu_frame_start()
47 (regs->sw109.val & 0xfeff); in vp8e_vpu_frame_start()
50 regs->sw54.val = 0x1000; in vp8e_vpu_frame_start()
53 regs->sw105.val = 0xfc000000; in vp8e_vpu_frame_start()
55 regs->sw105.val = 0xfc000000; in vp8e_vpu_frame_start()
57 regs->sw105.val = 0x3c000000; in vp8e_vpu_frame_start()
60 regs->sw77.base_stream = hw_cfg->output_strm_base; in vp8e_vpu_frame_start()
62 regs->sw78.base_control = hw_cfg->size_tbl_base; in vp8e_vpu_frame_start()
63 regs->sw74.nal_size_write = hw_cfg->size_tbl_base != 0; in vp8e_vpu_frame_start()
64 regs->sw109.mv_write = hw_cfg->mv_output_base != 0; in vp8e_vpu_frame_start()
66 regs->sw56.base_ref_lum = hw_cfg->internal_img_lum_base_r[0]; in vp8e_vpu_frame_start()
67 regs->sw57.base_ref_chr = hw_cfg->internal_img_chr_base_r[0]; in vp8e_vpu_frame_start()
68 regs->sw63.base_rec_lum = hw_cfg->internal_img_lum_base_w; in vp8e_vpu_frame_start()
69 regs->sw64.base_rec_chr = hw_cfg->internal_img_chr_base_w; in vp8e_vpu_frame_start()
71 regs->sw48.base_in_lum = hw_cfg->input_lum_base; in vp8e_vpu_frame_start()
75 regs->sw49.base_in_cb = hw_cfg->input_cb_base; in vp8e_vpu_frame_start()
79 regs->sw50.base_in_cr = hw_cfg->input_cr_base; in vp8e_vpu_frame_start()
84 regs->sw109.val |= 0x0400; in vp8e_vpu_frame_start()
85 regs->sw109.int_slice_ready = hw_cfg->int_slice_ready; in vp8e_vpu_frame_start()
86 regs->sw109.rec_write_disable = hw_cfg->rec_write_disable; in vp8e_vpu_frame_start()
87 regs->sw103.width = hw_cfg->mbs_in_row; in vp8e_vpu_frame_start()
88 regs->sw103.height = hw_cfg->mbs_in_col; in vp8e_vpu_frame_start()
89 regs->sw103.picture_type = hw_cfg->frame_coding_type; in vp8e_vpu_frame_start()
90 regs->sw103.encoding_mode = hw_cfg->coding_type; in vp8e_vpu_frame_start()
92 regs->sw61.chr_offset = hw_cfg->input_chroma_base_offset; in vp8e_vpu_frame_start()
93 regs->sw61.lum_offset = hw_cfg->input_luma_base_offset; in vp8e_vpu_frame_start()
94 regs->sw61.row_length = hw_cfg->pixels_on_row; in vp8e_vpu_frame_start()
95 regs->sw60.x_fill = hw_cfg->x_fill; in vp8e_vpu_frame_start()
96 regs->sw60.y_fill = hw_cfg->y_fill; in vp8e_vpu_frame_start()
97 regs->sw74.input_format = hw_cfg->input_format; in vp8e_vpu_frame_start()
98 regs->sw74.input_rot = hw_cfg->input_rotation; in vp8e_vpu_frame_start()
100 regs->sw59.cabac_enable = hw_cfg->enable_cabac; in vp8e_vpu_frame_start()
101 regs->sw75.ip_intra_16_favor = hw_cfg->intra_16_favor; in vp8e_vpu_frame_start()
102 regs->sw75.inter_favor = hw_cfg->inter_favor; in vp8e_vpu_frame_start()
103 regs->sw59.disable_qp_mv = hw_cfg->disable_qp_mv; in vp8e_vpu_frame_start()
104 regs->sw59.deblocking = hw_cfg->filter_disable; in vp8e_vpu_frame_start()
105 regs->sw60.skip_penalty = hw_cfg->skip_penalty; in vp8e_vpu_frame_start()
106 regs->sw99.split_mv = hw_cfg->split_mv_mode; in vp8e_vpu_frame_start()
107 regs->sw107.split_penalty_16x8 = hw_cfg->split_penalty[0]; in vp8e_vpu_frame_start()
108 regs->sw107.split_penalty_8x8 = hw_cfg->split_penalty[1]; in vp8e_vpu_frame_start()
109 regs->sw107.split_penalty_8x4 = hw_cfg->split_penalty[2]; in vp8e_vpu_frame_start()
110 regs->sw102.split_penalty_4x4 = hw_cfg->split_penalty[3]; in vp8e_vpu_frame_start()
111 regs->sw102.zero_mv_favor = hw_cfg->zero_mv_favor; in vp8e_vpu_frame_start()
113 regs->sw51.strm_hdr_rem1 = hw_cfg->strm_start_msb; in vp8e_vpu_frame_start()
114 regs->sw52.strm_hdr_rem2 = hw_cfg->strm_start_lsb; in vp8e_vpu_frame_start()
115 regs->sw53.strm_buf_limit = hw_cfg->output_strm_size; in vp8e_vpu_frame_start()
117 regs->sw76.base_ref_lum2 = hw_cfg->internal_img_lum_base_r[1]; in vp8e_vpu_frame_start()
118 regs->sw106.base_ref_chr2 = hw_cfg->internal_img_chr_base_r[1]; in vp8e_vpu_frame_start()
120 regs->sw100.y1_quant_dc = hw_cfg->y1_quant_dc[0]; in vp8e_vpu_frame_start()
121 regs->sw65.y1_quant_ac = hw_cfg->y1_quant_ac[0]; in vp8e_vpu_frame_start()
122 regs->sw66.y2_quant_dc = hw_cfg->y2_quant_dc[0]; in vp8e_vpu_frame_start()
123 regs->sw67.y2_quant_ac = hw_cfg->y2_quant_ac[0]; in vp8e_vpu_frame_start()
124 regs->sw68.ch_quant_dc = hw_cfg->ch_quant_dc[0]; in vp8e_vpu_frame_start()
125 regs->sw69.ch_quant_ac = hw_cfg->ch_quant_ac[0]; in vp8e_vpu_frame_start()
127 regs->sw100.y1_zbin_dc = hw_cfg->y1_zbin_dc[0]; in vp8e_vpu_frame_start()
128 regs->sw65.y1_zbin_ac = hw_cfg->y1_zbin_ac[0]; in vp8e_vpu_frame_start()
129 regs->sw66.y2_zbin_dc = hw_cfg->y2_zbin_dc[0]; in vp8e_vpu_frame_start()
130 regs->sw67.y2_zbin_ac = hw_cfg->y2_zbin_ac[0]; in vp8e_vpu_frame_start()
131 regs->sw68.ch_zbin_dc = hw_cfg->ch_zbin_dc[0]; in vp8e_vpu_frame_start()
132 regs->sw69.ch_zbin_ac = hw_cfg->ch_zbin_ac[0]; in vp8e_vpu_frame_start()
134 regs->sw100.y1_round_dc = hw_cfg->y1_round_dc[0]; in vp8e_vpu_frame_start()
135 regs->sw65.y1_round_ac = hw_cfg->y1_round_ac[0]; in vp8e_vpu_frame_start()
136 regs->sw66.y2_round_dc = hw_cfg->y2_round_dc[0]; in vp8e_vpu_frame_start()
137 regs->sw67.y2_round_ac = hw_cfg->y2_round_ac[0]; in vp8e_vpu_frame_start()
138 regs->sw68.ch_round_dc = hw_cfg->ch_round_dc[0]; in vp8e_vpu_frame_start()
139 regs->sw69.ch_round_ac = hw_cfg->ch_round_ac[0]; in vp8e_vpu_frame_start()
141 regs->sw70.y1_dequant_dc = hw_cfg->y1_dequant_dc[0]; in vp8e_vpu_frame_start()
142 regs->sw70.y1_dequant_ac = hw_cfg->y1_dequant_ac[0]; in vp8e_vpu_frame_start()
143 regs->sw70.y2_dequant_dc = hw_cfg->y2_dequant_dc[0]; in vp8e_vpu_frame_start()
144 regs->sw71.y2_dequant_ac = hw_cfg->y2_dequant_ac[0]; in vp8e_vpu_frame_start()
145 regs->sw71.ch_dequant_dc = hw_cfg->ch_dequant_dc[0]; in vp8e_vpu_frame_start()
146 regs->sw71.ch_dequant_ac = hw_cfg->ch_dequant_ac[0]; in vp8e_vpu_frame_start()
148 regs->sw70.mv_ref_idx = hw_cfg->mv_ref_idx[0]; in vp8e_vpu_frame_start()
149 regs->sw71.mv_ref_idx2 = hw_cfg->mv_ref_idx[1]; in vp8e_vpu_frame_start()
150 regs->sw71.ref2_enable = hw_cfg->ref2_enable; in vp8e_vpu_frame_start()
152 regs->sw72.bool_enc_value = hw_cfg->bool_enc_value; in vp8e_vpu_frame_start()
153 regs->sw73.bool_enc_value_bits = hw_cfg->bool_enc_value_bits; in vp8e_vpu_frame_start()
154 regs->sw73.bool_enc_range = hw_cfg->bool_enc_range; in vp8e_vpu_frame_start()
156 regs->sw73.filter_level = hw_cfg->filter_level[0]; in vp8e_vpu_frame_start()
157 regs->sw73.golden_penalty = hw_cfg->golden_penalty; in vp8e_vpu_frame_start()
158 regs->sw73.filter_sharpness = hw_cfg->filter_sharpness; in vp8e_vpu_frame_start()
159 regs->sw73.dct_partition_count = hw_cfg->dct_partitions; in vp8e_vpu_frame_start()
161 regs->sw60.start_offset = hw_cfg->first_free_bit; in vp8e_vpu_frame_start()
163 regs->sw79.base_next_lum = hw_cfg->vs_next_luma_base; in vp8e_vpu_frame_start()
164 regs->sw94.stab_mode = hw_cfg->vs_mode; in vp8e_vpu_frame_start()
166 regs->sw99.dmv_penalty_4p = hw_cfg->diff_mv_penalty[0]; in vp8e_vpu_frame_start()
167 regs->sw99.dmv_penalty_1p = hw_cfg->diff_mv_penalty[1]; in vp8e_vpu_frame_start()
168 regs->sw99.dmv_penalty_qp = hw_cfg->diff_mv_penalty[2]; in vp8e_vpu_frame_start()
170 regs->sw81.base_cabac_ctx = hw_cfg->cabac_tbl_base; in vp8e_vpu_frame_start()
171 regs->sw80.base_mv_write = hw_cfg->mv_output_base; in vp8e_vpu_frame_start()
173 regs->sw95.rgb_coeff_a = hw_cfg->rgb_coeff_a; in vp8e_vpu_frame_start()
174 regs->sw95.rgb_coeff_b = hw_cfg->rgb_coeff_b; in vp8e_vpu_frame_start()
175 regs->sw96.rgb_coeff_c = hw_cfg->rgb_coeff_c; in vp8e_vpu_frame_start()
176 regs->sw96.rgb_coeff_e = hw_cfg->rgb_coeff_e; in vp8e_vpu_frame_start()
177 regs->sw97.rgb_coeff_f = hw_cfg->rgb_coeff_f; in vp8e_vpu_frame_start()
179 regs->sw98.r_mask_msb = hw_cfg->r_mask_msb; in vp8e_vpu_frame_start()
180 regs->sw98.g_mask_msb = hw_cfg->g_mask_msb; in vp8e_vpu_frame_start()
181 regs->sw98.b_mask_msb = hw_cfg->b_mask_msb; in vp8e_vpu_frame_start()
183 regs->sw47.cir_start = hw_cfg->cir_start; in vp8e_vpu_frame_start()
184 regs->sw47.cir_interval = hw_cfg->cir_interval; in vp8e_vpu_frame_start()
186 regs->sw46.intra_area_left = hw_cfg->intra_area_left; in vp8e_vpu_frame_start()
187 regs->sw46.intra_area_right = hw_cfg->intra_area_right; in vp8e_vpu_frame_start()
188 regs->sw46.intra_area_top = hw_cfg->intra_area_top; in vp8e_vpu_frame_start()
189 regs->sw46.intra_area_bottom = hw_cfg->intra_area_bottom ; in vp8e_vpu_frame_start()
190 regs->sw82.roi1_left = hw_cfg->roi1_left; in vp8e_vpu_frame_start()
191 regs->sw82.roi1_right = hw_cfg->roi1_right; in vp8e_vpu_frame_start()
192 regs->sw82.roi1_top = hw_cfg->roi1_top; in vp8e_vpu_frame_start()
193 regs->sw82.roi1_bottom = hw_cfg->roi1_bottom; in vp8e_vpu_frame_start()
195 regs->sw83.roi2_left = hw_cfg->roi2_left; in vp8e_vpu_frame_start()
196 regs->sw83.roi2_right = hw_cfg->roi2_right; in vp8e_vpu_frame_start()
197 regs->sw83.roi2_top = hw_cfg->roi2_top; in vp8e_vpu_frame_start()
198 regs->sw83.roi2_bottom = hw_cfg->roi2_bottom; in vp8e_vpu_frame_start()
200 regs->sw44.base_partition1 = hw_cfg->partition_Base[0]; in vp8e_vpu_frame_start()
202 regs->sw45.base_partition2 = hw_cfg->partition_Base[1]; in vp8e_vpu_frame_start()
204 regs->sw108.base_prob_count = hw_cfg->prob_count_base; in vp8e_vpu_frame_start()
206 regs->sw33.mode0_penalty = hw_cfg->intra_mode_penalty[0]; in vp8e_vpu_frame_start()
207 regs->sw33.mode1_penalty = hw_cfg->intra_mode_penalty[1]; in vp8e_vpu_frame_start()
208 regs->sw34.mode2_penalty = hw_cfg->intra_mode_penalty[2]; in vp8e_vpu_frame_start()
209 regs->sw34.mode3_penalty = hw_cfg->intra_mode_penalty[3]; in vp8e_vpu_frame_start()
212 regs->sw28_32[i].b_mode_0_penalty = hw_cfg->intra_b_mode_penalty[2 * i]; in vp8e_vpu_frame_start()
213 regs->sw28_32[i].b_mode_1_penalty = hw_cfg->intra_b_mode_penalty[2 * i + 1]; in vp8e_vpu_frame_start()
216 regs->sw71.segment_enable = hw_cfg->segment_enable; in vp8e_vpu_frame_start()
217 regs->sw71.segment_map_update = hw_cfg->segment_map_update; in vp8e_vpu_frame_start()
218 regs->sw27.base_segment_map = hw_cfg->segment_map_base; in vp8e_vpu_frame_start()
221 regs->sw0_26[0 + i * 9].num_0.y1_quant_dc = hw_cfg->y1_quant_dc[1 + i]; in vp8e_vpu_frame_start()
222 regs->sw0_26[0 + i * 9].num_0.y2_quant_dc = hw_cfg->y2_quant_dc[1 + i]; in vp8e_vpu_frame_start()
224 regs->sw0_26[1 + i * 9].num_1.ch_quant_dc = hw_cfg->ch_quant_dc[1 + i]; in vp8e_vpu_frame_start()
225 regs->sw0_26[1 + i * 9].num_1.y1_quant_ac = hw_cfg->y1_quant_ac[1 + i]; in vp8e_vpu_frame_start()
227 regs->sw0_26[2 + i * 9].num_2.y2_quant_ac = hw_cfg->y2_quant_ac[1 + i]; in vp8e_vpu_frame_start()
228 regs->sw0_26[2 + i * 9].num_2.ch_quant_ac = hw_cfg->ch_quant_ac[1 + i]; in vp8e_vpu_frame_start()
230 regs->sw0_26[3 + i * 9].num_3.y1_zbin_dc = hw_cfg->y1_zbin_dc[1 + i]; in vp8e_vpu_frame_start()
231 regs->sw0_26[3 + i * 9].num_3.y2_zbin_dc = hw_cfg->y2_zbin_dc[1 + i]; in vp8e_vpu_frame_start()
232 regs->sw0_26[3 + i * 9].num_3.ch_zbin_dc = hw_cfg->ch_zbin_dc[1 + i]; in vp8e_vpu_frame_start()
234 regs->sw0_26[4 + i * 9].num_4.y1_zbin_ac = hw_cfg->y1_zbin_ac[1 + i]; in vp8e_vpu_frame_start()
235 regs->sw0_26[4 + i * 9].num_4.y2_zbin_ac = hw_cfg->y2_zbin_ac[1 + i]; in vp8e_vpu_frame_start()
236 regs->sw0_26[4 + i * 9].num_4.ch_zbin_ac = hw_cfg->ch_zbin_ac[1 + i]; in vp8e_vpu_frame_start()
238 regs->sw0_26[5 + i * 9].num_5.y1_round_dc = hw_cfg->y1_round_dc[1 + i]; in vp8e_vpu_frame_start()
239 regs->sw0_26[5 + i * 9].num_5.y2_round_dc = hw_cfg->y2_round_dc[1 + i]; in vp8e_vpu_frame_start()
240 regs->sw0_26[5 + i * 9].num_5.ch_round_dc = hw_cfg->ch_round_dc[1 + i]; in vp8e_vpu_frame_start()
242 regs->sw0_26[6 + i * 9].num_6.y1_round_ac = hw_cfg->y1_round_ac[1 + i]; in vp8e_vpu_frame_start()
243 regs->sw0_26[6 + i * 9].num_6.y2_round_ac = hw_cfg->y2_round_ac[1 + i]; in vp8e_vpu_frame_start()
244 regs->sw0_26[6 + i * 9].num_6.ch_round_ac = hw_cfg->ch_round_ac[1 + i]; in vp8e_vpu_frame_start()
246 regs->sw0_26[7 + i * 9].num_7.y1_dequant_dc = hw_cfg->y1_dequant_dc[1 + i]; in vp8e_vpu_frame_start()
247 regs->sw0_26[7 + i * 9].num_7.y2_dequant_dc = hw_cfg->y2_dequant_dc[1 + i]; in vp8e_vpu_frame_start()
248 regs->sw0_26[7 + i * 9].num_7.ch_dequant_dc = hw_cfg->ch_dequant_dc[1 + i]; in vp8e_vpu_frame_start()
249 regs->sw0_26[7 + i * 9].num_7.filter_level = hw_cfg->filter_level[1 + i]; in vp8e_vpu_frame_start()
251 regs->sw0_26[8 + i * 9].num_8.y1_dequant_ac = hw_cfg->y1_dequant_ac[1 + i]; in vp8e_vpu_frame_start()
252 regs->sw0_26[8 + i * 9].num_8.y2_dequant_ac = hw_cfg->y2_dequant_ac[1 + i]; in vp8e_vpu_frame_start()
253 regs->sw0_26[8 + i * 9].num_8.ch_dequant_ac = hw_cfg->ch_dequant_ac[1 + i]; in vp8e_vpu_frame_start()
256 regs->sw40.lf_ref_delta0 = hw_cfg->lf_ref_delta[0] & mask_7b; in vp8e_vpu_frame_start()
257 regs->sw42.lf_ref_delta1 = hw_cfg->lf_ref_delta[1] & mask_7b; in vp8e_vpu_frame_start()
258 regs->sw42.lf_ref_delta2 = hw_cfg->lf_ref_delta[2] & mask_7b; in vp8e_vpu_frame_start()
259 regs->sw42.lf_ref_delta3 = hw_cfg->lf_ref_delta[3] & mask_7b; in vp8e_vpu_frame_start()
260 regs->sw40.lf_mode_delta0 = hw_cfg->lf_mode_delta[0] & mask_7b; in vp8e_vpu_frame_start()
261 regs->sw43.lf_mode_delta1 = hw_cfg->lf_mode_delta[1] & mask_7b; in vp8e_vpu_frame_start()
262 regs->sw43.lf_mode_delta2 = hw_cfg->lf_mode_delta[2] & mask_7b; in vp8e_vpu_frame_start()
263 regs->sw43.lf_mode_delta3 = hw_cfg->lf_mode_delta[3] & mask_7b; in vp8e_vpu_frame_start()
267 regs->sw120_183[j].penalty_0 = hw_cfg->dmv_penalty[j * 4 + 3]; in vp8e_vpu_frame_start()
268 regs->sw120_183[j].penalty_1 = hw_cfg->dmv_penalty[j * 4 + 2]; in vp8e_vpu_frame_start()
269 regs->sw120_183[j].penalty_2 = hw_cfg->dmv_penalty[j * 4 + 1]; in vp8e_vpu_frame_start()
270 regs->sw120_183[j].penalty_3 = hw_cfg->dmv_penalty[j * 4]; in vp8e_vpu_frame_start()
272 regs->sw120_183[j + 32].penalty_0 = hw_cfg->dmv_qpel_penalty[j * 4 + 3]; in vp8e_vpu_frame_start()
273 regs->sw120_183[j + 32].penalty_1 = hw_cfg->dmv_qpel_penalty[j * 4 + 2]; in vp8e_vpu_frame_start()
274 regs->sw120_183[j + 32].penalty_2 = hw_cfg->dmv_qpel_penalty[j * 4 + 1]; in vp8e_vpu_frame_start()
275 regs->sw120_183[j + 32].penalty_3 = hw_cfg->dmv_qpel_penalty[j * 4]; in vp8e_vpu_frame_start()
278 regs->sw103.enable = 0x1; in vp8e_vpu_frame_start()
343 MPP_FREE(ctx->regs); in hal_vp8e_vepu2_deinit_v2()
383 RK_U32 *tmp = (RK_U32 *)ctx->regs; in hal_vp8e_vepu2_start_v2()
394 wr_cfg.reg = ctx->regs; in hal_vp8e_vepu2_start_v2()
404 rd_cfg.reg = ctx->regs; in hal_vp8e_vepu2_start_v2()
429 Vp8eVepu2Reg_t *regs = (Vp8eVepu2Reg_t *) ctx->regs; in vp8e_update_hw_cfg() local
431 hw_cfg->output_strm_base = regs->sw53.strm_buf_limit / 8; in vp8e_update_hw_cfg()
432 hw_cfg->qp_sum = regs->sw58.qp_sum * 2; in vp8e_update_hw_cfg()
433 hw_cfg->mad_count = regs->sw104.mad_count; in vp8e_update_hw_cfg()
434 hw_cfg->rlc_count = regs->sw62.rlc_sum * 3; in vp8e_update_hw_cfg()
454 Vp8eVepu2Reg_t *regs = (Vp8eVepu2Reg_t *) ctx->regs; in hal_vp8e_vepu2_wait_v2() local
466 fb->hw_status = regs->sw109.val & HW_STATUS_MASK; in hal_vp8e_vepu2_wait_v2()
467 if (regs->sw109.val & HW_STATUS_FRAME_READY) in hal_vp8e_vepu2_wait_v2()
469 else if (regs->sw109.val & HW_STATUS_BUFFER_FULL) in hal_vp8e_vepu2_wait_v2()