Lines Matching refs:regs
378 static void setup_vepu540c_normal(HalVepu540cRegSet *regs) in setup_vepu540c_normal() argument
384 regs->reg_ctl.enc_strt.lkt_num = 0; in setup_vepu540c_normal()
385 regs->reg_ctl.enc_strt.vepu_cmd = 1; in setup_vepu540c_normal()
387 regs->reg_ctl.func_en.cke = 1; in setup_vepu540c_normal()
388 regs->reg_ctl.func_en.resetn_hw_en = 1; in setup_vepu540c_normal()
389 regs->reg_ctl.func_en.enc_done_tmvp_en = 1; in setup_vepu540c_normal()
392 regs->reg_ctl.enc_clr.safe_clr = 0; in setup_vepu540c_normal()
393 regs->reg_ctl.enc_clr.force_clr = 0; in setup_vepu540c_normal()
399 regs->reg_ctl.int_en.enc_done_en = 1; in setup_vepu540c_normal()
400 regs->reg_ctl.int_en.lkt_node_done_en = 1; in setup_vepu540c_normal()
401 regs->reg_ctl.int_en.sclr_done_en = 1; in setup_vepu540c_normal()
402 regs->reg_ctl.int_en.vslc_done_en = 0; in setup_vepu540c_normal()
403 regs->reg_ctl.int_en.vbsf_oflw_en = 1; in setup_vepu540c_normal()
404 regs->reg_ctl.int_en.vbuf_lens_en = 1; in setup_vepu540c_normal()
405 regs->reg_ctl.int_en.enc_err_en = 1; in setup_vepu540c_normal()
406 regs->reg_ctl.int_en.dvbm_fcfg_en = 1; in setup_vepu540c_normal()
407 regs->reg_ctl.int_en.wdg_en = 1; in setup_vepu540c_normal()
408 regs->reg_ctl.int_en.lkt_err_int_en = 1; in setup_vepu540c_normal()
409 regs->reg_ctl.int_en.lkt_err_stop_en = 1; in setup_vepu540c_normal()
410 regs->reg_ctl.int_en.lkt_force_stop_en = 1; in setup_vepu540c_normal()
411 regs->reg_ctl.int_en.jslc_done_en = 1; in setup_vepu540c_normal()
412 regs->reg_ctl.int_en.jbsf_oflw_en = 1; in setup_vepu540c_normal()
413 regs->reg_ctl.int_en.jbuf_lens_en = 1; in setup_vepu540c_normal()
414 regs->reg_ctl.int_en.dvbm_dcnt_en = 1; in setup_vepu540c_normal()
417 regs->reg_ctl.int_msk.enc_done_msk = 0; in setup_vepu540c_normal()
418 regs->reg_ctl.int_msk.lkt_node_done_msk = 0; in setup_vepu540c_normal()
419 regs->reg_ctl.int_msk.sclr_done_msk = 0; in setup_vepu540c_normal()
420 regs->reg_ctl.int_msk.vslc_done_msk = 0; in setup_vepu540c_normal()
421 regs->reg_ctl.int_msk.vbsf_oflw_msk = 0; in setup_vepu540c_normal()
422 regs->reg_ctl.int_msk.vbuf_lens_msk = 0; in setup_vepu540c_normal()
423 regs->reg_ctl.int_msk.enc_err_msk = 0; in setup_vepu540c_normal()
424 regs->reg_ctl.int_msk.dvbm_fcfg_msk = 0; in setup_vepu540c_normal()
425 regs->reg_ctl.int_msk.wdg_msk = 0; in setup_vepu540c_normal()
426 regs->reg_ctl.int_msk.lkt_err_int_msk = 0; in setup_vepu540c_normal()
427 regs->reg_ctl.int_msk.lkt_err_stop_msk = 0; in setup_vepu540c_normal()
428 regs->reg_ctl.int_msk.lkt_force_stop_msk = 0; in setup_vepu540c_normal()
429 regs->reg_ctl.int_msk.jslc_done_msk = 0; in setup_vepu540c_normal()
430 regs->reg_ctl.int_msk.jbsf_oflw_msk = 0; in setup_vepu540c_normal()
431 regs->reg_ctl.int_msk.jbuf_lens_msk = 0; in setup_vepu540c_normal()
432 regs->reg_ctl.int_msk.dvbm_dcnt_msk = 0; in setup_vepu540c_normal()
437 regs->reg_ctl.enc_wdg.vs_load_thd = 0x5ffff; in setup_vepu540c_normal()
438 regs->reg_ctl.enc_wdg.rfp_load_thd = 0;//xff; in setup_vepu540c_normal()
441 regs->reg_ctl.dtrns_map.jpeg_bus_edin = 0; in setup_vepu540c_normal()
442 regs->reg_ctl.dtrns_map.src_bus_edin = 0; in setup_vepu540c_normal()
443 regs->reg_ctl.dtrns_map.meiw_bus_edin = 0; in setup_vepu540c_normal()
444 regs->reg_ctl.dtrns_map.bsw_bus_edin = 7; in setup_vepu540c_normal()
445 regs->reg_ctl.dtrns_map.lktr_bus_edin = 0; in setup_vepu540c_normal()
446 regs->reg_ctl.dtrns_map.roir_bus_edin = 0; in setup_vepu540c_normal()
447 regs->reg_ctl.dtrns_map.lktw_bus_edin = 0; in setup_vepu540c_normal()
448 regs->reg_ctl.dtrns_map.rec_nfbc_bus_edin = 0; in setup_vepu540c_normal()
450 regs->reg_ctl.dtrns_cfg.axi_brsp_cke = 0; in setup_vepu540c_normal()
454 static MPP_RET setup_vepu540c_prep(HalVepu540cRegSet *regs, MppEncPrepCfg *prep) in setup_vepu540c_prep() argument
469 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu540c_prep()
470 regs->reg_base.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu540c_prep()
471 regs->reg_base.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu540c_prep()
472 regs->reg_base.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu540c_prep()
474 regs->reg_ctl.dtrns_map.src_bus_edin = cfg.src_endian; in setup_vepu540c_prep()
476 regs->reg_base.src_fmt.src_cfmt = hw_fmt; in setup_vepu540c_prep()
477 regs->reg_base.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu540c_prep()
478 regs->reg_base.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu540c_prep()
479 regs->reg_base.src_fmt.out_fmt = (fmt == MPP_FMT_YUV400) ? 0 : 1; in setup_vepu540c_prep()
492 regs->reg_base.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu540c_prep()
493 regs->reg_base.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu540c_prep()
494 regs->reg_base.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu540c_prep()
496 regs->reg_base.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu540c_prep()
497 regs->reg_base.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu540c_prep()
498 regs->reg_base.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu540c_prep()
500 regs->reg_base.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in setup_vepu540c_prep()
501 regs->reg_base.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu540c_prep()
502 regs->reg_base.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu540c_prep()
504 regs->reg_base.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu540c_prep()
505 regs->reg_base.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu540c_prep()
506 regs->reg_base.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; in setup_vepu540c_prep()
510 regs->reg_base.src_udfy.csc_wgt_b2y = cfg.weight[0]; in setup_vepu540c_prep()
511 regs->reg_base.src_udfy.csc_wgt_g2y = cfg.weight[1]; in setup_vepu540c_prep()
512 regs->reg_base.src_udfy.csc_wgt_r2y = cfg.weight[2]; in setup_vepu540c_prep()
514 regs->reg_base.src_udfu.csc_wgt_b2u = cfg.weight[3]; in setup_vepu540c_prep()
515 regs->reg_base.src_udfu.csc_wgt_g2u = cfg.weight[4]; in setup_vepu540c_prep()
516 regs->reg_base.src_udfu.csc_wgt_r2u = cfg.weight[5]; in setup_vepu540c_prep()
518 regs->reg_base.src_udfv.csc_wgt_b2v = cfg.weight[6]; in setup_vepu540c_prep()
519 regs->reg_base.src_udfv.csc_wgt_g2v = cfg.weight[7]; in setup_vepu540c_prep()
520 regs->reg_base.src_udfv.csc_wgt_r2v = cfg.weight[8]; in setup_vepu540c_prep()
522 regs->reg_base.src_udfo.csc_ofst_y = cfg.offset[0]; in setup_vepu540c_prep()
523 regs->reg_base.src_udfo.csc_ofst_u = cfg.offset[1]; in setup_vepu540c_prep()
524 regs->reg_base.src_udfo.csc_ofst_v = cfg.offset[2]; in setup_vepu540c_prep()
527 regs->reg_base.src_strd0.src_strd0 = y_stride; in setup_vepu540c_prep()
528 regs->reg_base.src_strd1.src_strd1 = c_stride; in setup_vepu540c_prep()
530 regs->reg_base.src_proc.src_mirr = prep->mirroring > 0; in setup_vepu540c_prep()
531 regs->reg_base.src_proc.src_rot = prep->rotation; in setup_vepu540c_prep()
534 regs->reg_base.sli_cfg.mv_v_lmt_thd = 0; in setup_vepu540c_prep()
535 regs->reg_base.sli_cfg.mv_v_lmt_en = 0; in setup_vepu540c_prep()
537 regs->reg_base.pic_ofst.pic_ofst_y = 0; in setup_vepu540c_prep()
538 regs->reg_base.pic_ofst.pic_ofst_x = 0; in setup_vepu540c_prep()
545 static void setup_vepu540c_codec(HalVepu540cRegSet *regs, H264eSps *sps, in setup_vepu540c_codec() argument
550 regs->reg_base.enc_pic.enc_stnd = 0; in setup_vepu540c_codec()
551 regs->reg_base.enc_pic.cur_frm_ref = slice->nal_reference_idc > 0; in setup_vepu540c_codec()
552 regs->reg_base.enc_pic.bs_scp = 1; in setup_vepu540c_codec()
554 regs->reg_base.synt_nal.nal_ref_idc = slice->nal_reference_idc; in setup_vepu540c_codec()
555 regs->reg_base.synt_nal.nal_unit_type = slice->nalu_type; in setup_vepu540c_codec()
557 regs->reg_base.synt_sps.max_fnum = sps->log2_max_frame_num_minus4; in setup_vepu540c_codec()
558 regs->reg_base.synt_sps.drct_8x8 = sps->direct8x8_inference; in setup_vepu540c_codec()
559 regs->reg_base.synt_sps.mpoc_lm4 = sps->log2_max_poc_lsb_minus4; in setup_vepu540c_codec()
561 regs->reg_base.synt_pps.etpy_mode = pps->entropy_coding_mode; in setup_vepu540c_codec()
562 regs->reg_base.synt_pps.trns_8x8 = pps->transform_8x8_mode; in setup_vepu540c_codec()
563 regs->reg_base.synt_pps.csip_flag = pps->constrained_intra_pred; in setup_vepu540c_codec()
564 regs->reg_base.synt_pps.num_ref0_idx = pps->num_ref_idx_l0_default_active - 1; in setup_vepu540c_codec()
565 regs->reg_base.synt_pps.num_ref1_idx = pps->num_ref_idx_l1_default_active - 1; in setup_vepu540c_codec()
566 regs->reg_base.synt_pps.pic_init_qp = pps->pic_init_qp; in setup_vepu540c_codec()
567 regs->reg_base.synt_pps.cb_ofst = pps->chroma_qp_index_offset; in setup_vepu540c_codec()
568 regs->reg_base.synt_pps.cr_ofst = pps->second_chroma_qp_index_offset; in setup_vepu540c_codec()
569 regs->reg_base.synt_pps.dbf_cp_flg = pps->deblocking_filter_control; in setup_vepu540c_codec()
571 regs->reg_base.synt_sli0.sli_type = (slice->slice_type == H264_I_SLICE) ? (2) : (0); in setup_vepu540c_codec()
572 regs->reg_base.synt_sli0.pps_id = slice->pic_parameter_set_id; in setup_vepu540c_codec()
573 regs->reg_base.synt_sli0.drct_smvp = 0; in setup_vepu540c_codec()
574 regs->reg_base.synt_sli0.num_ref_ovrd = slice->num_ref_idx_override; in setup_vepu540c_codec()
575 regs->reg_base.synt_sli0.cbc_init_idc = slice->cabac_init_idc; in setup_vepu540c_codec()
576 regs->reg_base.synt_sli0.frm_num = slice->frame_num; in setup_vepu540c_codec()
578 …regs->reg_base.synt_sli1.idr_pid = (slice->slice_type == H264_I_SLICE) ? slice->idr_pic_id … in setup_vepu540c_codec()
579 regs->reg_base.synt_sli1.poc_lsb = slice->pic_order_cnt_lsb; in setup_vepu540c_codec()
582 regs->reg_base.synt_sli2.dis_dblk_idc = slice->disable_deblocking_filter_idc; in setup_vepu540c_codec()
583 regs->reg_base.synt_sli2.sli_alph_ofst = slice->slice_alpha_c0_offset_div2; in setup_vepu540c_codec()
591 regs->reg_base.synt_sli2.ref_list0_rodr = 1; in setup_vepu540c_codec()
592 regs->reg_base.synt_sli2.rodr_pic_idx = rplmo.modification_of_pic_nums_idc; in setup_vepu540c_codec()
597 regs->reg_base.synt_sli2.rodr_pic_num = rplmo.abs_diff_pic_num_minus1; in setup_vepu540c_codec()
600 regs->reg_base.synt_sli2.rodr_pic_num = rplmo.long_term_pic_idx; in setup_vepu540c_codec()
609 regs->reg_base.synt_sli2.ref_list0_rodr = 0; in setup_vepu540c_codec()
610 regs->reg_base.synt_sli2.rodr_pic_idx = 0; in setup_vepu540c_codec()
611 regs->reg_base.synt_sli2.rodr_pic_num = 0; in setup_vepu540c_codec()
616 regs->reg_base.synt_refm0.nopp_flg = 0; in setup_vepu540c_codec()
617 regs->reg_base.synt_refm0.ltrf_flg = 0; in setup_vepu540c_codec()
618 regs->reg_base.synt_refm0.arpm_flg = 0; in setup_vepu540c_codec()
619 regs->reg_base.synt_refm0.mmco4_pre = 0; in setup_vepu540c_codec()
620 regs->reg_base.synt_refm0.mmco_type0 = 0; in setup_vepu540c_codec()
621 regs->reg_base.synt_refm0.mmco_parm0 = 0; in setup_vepu540c_codec()
622 regs->reg_base.synt_refm0.mmco_type1 = 0; in setup_vepu540c_codec()
623 regs->reg_base.synt_refm1.mmco_parm1 = 0; in setup_vepu540c_codec()
624 regs->reg_base.synt_refm0.mmco_type2 = 0; in setup_vepu540c_codec()
625 regs->reg_base.synt_refm1.mmco_parm2 = 0; in setup_vepu540c_codec()
626 regs->reg_base.synt_refm2.long_term_frame_idx0 = 0; in setup_vepu540c_codec()
627 regs->reg_base.synt_refm2.long_term_frame_idx1 = 0; in setup_vepu540c_codec()
628 regs->reg_base.synt_refm2.long_term_frame_idx2 = 0; in setup_vepu540c_codec()
634 regs->reg_base.synt_refm0.nopp_flg = slice->no_output_of_prior_pics; in setup_vepu540c_codec()
635 regs->reg_base.synt_refm0.ltrf_flg = slice->long_term_reference_flag; in setup_vepu540c_codec()
640 regs->reg_base.synt_refm0.arpm_flg = 1; in setup_vepu540c_codec()
675 regs->reg_base.synt_refm0.mmco_type0 = type; in setup_vepu540c_codec()
676 regs->reg_base.synt_refm0.mmco_parm0 = param_0; in setup_vepu540c_codec()
677 regs->reg_base.synt_refm2.long_term_frame_idx0 = param_1; in setup_vepu540c_codec()
711 regs->reg_base.synt_refm0.mmco_type1 = type; in setup_vepu540c_codec()
712 regs->reg_base.synt_refm1.mmco_parm1 = param_0; in setup_vepu540c_codec()
713 regs->reg_base.synt_refm2.long_term_frame_idx1 = param_1; in setup_vepu540c_codec()
747 regs->reg_base.synt_refm0.mmco_type2 = type; in setup_vepu540c_codec()
748 regs->reg_base.synt_refm1.mmco_parm2 = param_0; in setup_vepu540c_codec()
749 regs->reg_base.synt_refm2.long_term_frame_idx2 = param_1; in setup_vepu540c_codec()
757 static void setup_vepu540c_rdo_pred(HalVepu540cRegSet *regs, H264eSps *sps, in setup_vepu540c_rdo_pred() argument
763 regs->reg_rc_roi.klut_ofst.chrm_klut_ofst = 6; in setup_vepu540c_rdo_pred()
765 regs->reg_rc_roi.klut_ofst.chrm_klut_ofst = 9; in setup_vepu540c_rdo_pred()
768 regs->reg_base.rdo_cfg.rect_size = (sps->profile_idc == H264_PROFILE_BASELINE && in setup_vepu540c_rdo_pred()
770 regs->reg_base.rdo_cfg.vlc_lmt = (sps->profile_idc < H264_PROFILE_MAIN) && in setup_vepu540c_rdo_pred()
772 regs->reg_base.rdo_cfg.chrm_spcl = 1; in setup_vepu540c_rdo_pred()
773 regs->reg_base.rdo_cfg.ccwa_e = 1; in setup_vepu540c_rdo_pred()
774 regs->reg_base.rdo_cfg.scl_lst_sel = pps->pic_scaling_matrix_present; in setup_vepu540c_rdo_pred()
775 regs->reg_base.rdo_cfg.atf_e = 1; in setup_vepu540c_rdo_pred()
776 regs->reg_base.rdo_cfg.atr_e = 1; in setup_vepu540c_rdo_pred()
777 regs->reg_base.rdo_cfg.intra_cost_e = 1; in setup_vepu540c_rdo_pred()
778 regs->reg_base.iprd_csts.rdo_mark_mode = 0x100; in setup_vepu540c_rdo_pred()
886 static void setup_vepu540c_rc_base(HalVepu540cRegSet *regs, HalH264eVepu540cCtx *ctx, EncRcTask *rc… in setup_vepu540c_rc_base() argument
910 regs->reg_rc_roi.roi_qthd0.qpmin_area0 = qp_min; in setup_vepu540c_rc_base()
911 regs->reg_rc_roi.roi_qthd0.qpmax_area0 = qp_max; in setup_vepu540c_rc_base()
912 regs->reg_rc_roi.roi_qthd0.qpmin_area1 = qp_min; in setup_vepu540c_rc_base()
913 regs->reg_rc_roi.roi_qthd0.qpmax_area1 = qp_max; in setup_vepu540c_rc_base()
914 regs->reg_rc_roi.roi_qthd0.qpmin_area2 = qp_min; in setup_vepu540c_rc_base()
916 regs->reg_rc_roi.roi_qthd1.qpmax_area2 = qp_max; in setup_vepu540c_rc_base()
917 regs->reg_rc_roi.roi_qthd1.qpmin_area3 = qp_min; in setup_vepu540c_rc_base()
918 regs->reg_rc_roi.roi_qthd1.qpmax_area3 = qp_max; in setup_vepu540c_rc_base()
919 regs->reg_rc_roi.roi_qthd1.qpmin_area4 = qp_min; in setup_vepu540c_rc_base()
920 regs->reg_rc_roi.roi_qthd1.qpmax_area4 = qp_max; in setup_vepu540c_rc_base()
922 regs->reg_rc_roi.roi_qthd2.qpmin_area5 = qp_min; in setup_vepu540c_rc_base()
923 regs->reg_rc_roi.roi_qthd2.qpmax_area5 = qp_max; in setup_vepu540c_rc_base()
924 regs->reg_rc_roi.roi_qthd2.qpmin_area6 = qp_min; in setup_vepu540c_rc_base()
925 regs->reg_rc_roi.roi_qthd2.qpmax_area6 = qp_max; in setup_vepu540c_rc_base()
926 regs->reg_rc_roi.roi_qthd2.qpmin_area7 = qp_min; in setup_vepu540c_rc_base()
928 regs->reg_rc_roi.roi_qthd3.qpmax_area7 = qp_max; in setup_vepu540c_rc_base()
929 regs->reg_rc_roi.roi_qthd3.qpmap_mode = qpmap_mode; in setup_vepu540c_rc_base()
932 regs->reg_base.enc_pic.pic_qp = rc_info->quality_target; in setup_vepu540c_rc_base()
933 regs->reg_base.rc_qp.rc_max_qp = rc_info->quality_target; in setup_vepu540c_rc_base()
934 regs->reg_base.rc_qp.rc_min_qp = rc_info->quality_target; in setup_vepu540c_rc_base()
946 regs->reg_base.enc_pic.pic_qp = qp_target; in setup_vepu540c_rc_base()
948 regs->reg_base.rc_cfg.rc_en = 1; in setup_vepu540c_rc_base()
949 regs->reg_base.rc_cfg.aq_en = 1; in setup_vepu540c_rc_base()
950 regs->reg_base.rc_cfg.aq_mode = 0; in setup_vepu540c_rc_base()
951 regs->reg_base.rc_cfg.rc_ctu_num = mb_w; in setup_vepu540c_rc_base()
953 regs->reg_base.rc_qp.rc_qp_range = (slice->slice_type == H264_I_SLICE) ? in setup_vepu540c_rc_base()
955 regs->reg_base.rc_qp.rc_max_qp = qp_max; in setup_vepu540c_rc_base()
956 regs->reg_base.rc_qp.rc_min_qp = qp_min; in setup_vepu540c_rc_base()
958 regs->reg_base.rc_tgt.ctu_ebit = mb_target_bits_mul_16; in setup_vepu540c_rc_base()
960 regs->reg_rc_roi.rc_adj0.qp_adj0 = -2; in setup_vepu540c_rc_base()
961 regs->reg_rc_roi.rc_adj0.qp_adj1 = -1; in setup_vepu540c_rc_base()
962 regs->reg_rc_roi.rc_adj0.qp_adj2 = 0; in setup_vepu540c_rc_base()
963 regs->reg_rc_roi.rc_adj0.qp_adj3 = 1; in setup_vepu540c_rc_base()
964 regs->reg_rc_roi.rc_adj0.qp_adj4 = 2; in setup_vepu540c_rc_base()
965 regs->reg_rc_roi.rc_adj1.qp_adj5 = 0; in setup_vepu540c_rc_base()
966 regs->reg_rc_roi.rc_adj1.qp_adj6 = 0; in setup_vepu540c_rc_base()
967 regs->reg_rc_roi.rc_adj1.qp_adj7 = 0; in setup_vepu540c_rc_base()
968 regs->reg_rc_roi.rc_adj1.qp_adj8 = 0; in setup_vepu540c_rc_base()
970 regs->reg_rc_roi.rc_dthd_0_8[0] = 4 * negative_bits_thd; in setup_vepu540c_rc_base()
971 regs->reg_rc_roi.rc_dthd_0_8[1] = negative_bits_thd; in setup_vepu540c_rc_base()
972 regs->reg_rc_roi.rc_dthd_0_8[2] = positive_bits_thd; in setup_vepu540c_rc_base()
973 regs->reg_rc_roi.rc_dthd_0_8[3] = 4 * positive_bits_thd; in setup_vepu540c_rc_base()
974 regs->reg_rc_roi.rc_dthd_0_8[4] = 0x7FFFFFFF; in setup_vepu540c_rc_base()
975 regs->reg_rc_roi.rc_dthd_0_8[5] = 0x7FFFFFFF; in setup_vepu540c_rc_base()
976 regs->reg_rc_roi.rc_dthd_0_8[6] = 0x7FFFFFFF; in setup_vepu540c_rc_base()
977 regs->reg_rc_roi.rc_dthd_0_8[7] = 0x7FFFFFFF; in setup_vepu540c_rc_base()
978 regs->reg_rc_roi.rc_dthd_0_8[8] = 0x7FFFFFFF; in setup_vepu540c_rc_base()
983 static void setup_vepu540c_io_buf(HalVepu540cRegSet *regs, MppDev dev, in setup_vepu540c_io_buf() argument
1001 regs->reg_base.adr_src0 = fd_in; in setup_vepu540c_io_buf()
1002 regs->reg_base.adr_src1 = fd_in; in setup_vepu540c_io_buf()
1003 regs->reg_base.adr_src2 = fd_in; in setup_vepu540c_io_buf()
1005 regs->reg_base.bsbt_addr = fd_out; in setup_vepu540c_io_buf()
1006 regs->reg_base.bsbb_addr = fd_out; in setup_vepu540c_io_buf()
1007 regs->reg_base.adr_bsbs = fd_out; in setup_vepu540c_io_buf()
1008 regs->reg_base.bsbr_addr = fd_out; in setup_vepu540c_io_buf()
1012 regs->reg_base.rfpt_h_addr = 0xffffffff; in setup_vepu540c_io_buf()
1013 regs->reg_base.rfpb_h_addr = 0; in setup_vepu540c_io_buf()
1014 regs->reg_base.rfpt_b_addr = 0xffffffff; in setup_vepu540c_io_buf()
1015 regs->reg_base.adr_rfpb_b = 0; in setup_vepu540c_io_buf()
1062 static void setup_vepu540c_recn_refr(HalH264eVepu540cCtx *ctx, HalVepu540cRegSet *regs) in setup_vepu540c_recn_refr() argument
1083 regs->reg_base.rfpw_h_addr = fd; in setup_vepu540c_recn_refr()
1084 regs->reg_base.rfpw_b_addr = fd; in setup_vepu540c_recn_refr()
1085 regs->reg_base.dspw_addr = mpp_buffer_get_fd(buf_thumb); in setup_vepu540c_recn_refr()
1097 regs->reg_base.rfpr_h_addr = fd; in setup_vepu540c_recn_refr()
1098 regs->reg_base.rfpr_b_addr = fd; in setup_vepu540c_recn_refr()
1099 regs->reg_base.dspr_addr = mpp_buffer_get_fd(buf_thumb); in setup_vepu540c_recn_refr()
1105 static void setup_vepu540c_split(HalVepu540cRegSet *regs, MppEncCfgSet *cfg) in setup_vepu540c_split() argument
1111 regs->reg_base.sli_splt.sli_splt = 0; in setup_vepu540c_split()
1112 regs->reg_base.sli_splt.sli_splt_mode = 0; in setup_vepu540c_split()
1113 regs->reg_base.sli_splt.sli_splt_cpst = 0; in setup_vepu540c_split()
1114 regs->reg_base.sli_splt.sli_max_num_m1 = 0; in setup_vepu540c_split()
1115 regs->reg_base.sli_splt.sli_flsh = 0; in setup_vepu540c_split()
1116 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = 0; in setup_vepu540c_split()
1118 regs->reg_base.sli_byte.sli_splt_byte = 0; in setup_vepu540c_split()
1119 regs->reg_base.enc_pic.slen_fifo = 0; in setup_vepu540c_split()
1122 regs->reg_base.sli_splt.sli_splt = 1; in setup_vepu540c_split()
1123 regs->reg_base.sli_splt.sli_splt_mode = 0; in setup_vepu540c_split()
1124 regs->reg_base.sli_splt.sli_splt_cpst = 0; in setup_vepu540c_split()
1125 regs->reg_base.sli_splt.sli_max_num_m1 = 500; in setup_vepu540c_split()
1126 regs->reg_base.sli_splt.sli_flsh = 1; in setup_vepu540c_split()
1127 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = 0; in setup_vepu540c_split()
1129 regs->reg_base.sli_byte.sli_splt_byte = cfg->split.split_arg; in setup_vepu540c_split()
1130 regs->reg_base.enc_pic.slen_fifo = 0; in setup_vepu540c_split()
1131 regs->reg_base.enc_pic.slen_fifo = cfg->split.split_out ? 1 : 0; in setup_vepu540c_split()
1132 regs->reg_ctl.int_en.vslc_done_en = regs->reg_base.enc_pic.slen_fifo; in setup_vepu540c_split()
1139 regs->reg_base.sli_splt.sli_splt = 1; in setup_vepu540c_split()
1140 regs->reg_base.sli_splt.sli_splt_mode = 1; in setup_vepu540c_split()
1141 regs->reg_base.sli_splt.sli_splt_cpst = 0; in setup_vepu540c_split()
1142 regs->reg_base.sli_splt.sli_max_num_m1 = 500; in setup_vepu540c_split()
1143 regs->reg_base.sli_splt.sli_flsh = 1; in setup_vepu540c_split()
1144 regs->reg_base.sli_cnum.sli_splt_cnum_m1 = cfg->split.split_arg - 1; in setup_vepu540c_split()
1146 regs->reg_base.sli_byte.sli_splt_byte = 0; in setup_vepu540c_split()
1147 regs->reg_base.enc_pic.slen_fifo = cfg->split.split_out ? 1 : 0; in setup_vepu540c_split()
1149 (regs->reg_base.enc_pic.slen_fifo && (slice_num > VEPU540C_SLICE_FIFO_LEN))) in setup_vepu540c_split()
1150 regs->reg_ctl.int_en.vslc_done_en = 1; in setup_vepu540c_split()
1160 static void calc_cime_parameter(HalVepu540cRegSet *regs) in calc_cime_parameter() argument
1162 Vepu540cBaseCfg *base_regs = ®s->reg_base; in calc_cime_parameter()
1245 static void setup_vepu540c_me(HalVepu540cRegSet *regs, H264eSps *sps, in setup_vepu540c_me() argument
1250 regs->reg_base.me_rnge.cime_srch_dwnh = 15; in setup_vepu540c_me()
1251 regs->reg_base.me_rnge.cime_srch_uph = 14; in setup_vepu540c_me()
1252 regs->reg_base.me_rnge.cime_srch_rgtw = 12; in setup_vepu540c_me()
1253 regs->reg_base.me_rnge.cime_srch_lftw = 12; in setup_vepu540c_me()
1254 regs->reg_base.me_cfg.rme_srch_h = 3; in setup_vepu540c_me()
1255 regs->reg_base.me_cfg.rme_srch_v = 3; in setup_vepu540c_me()
1257 regs->reg_base.me_cfg.srgn_max_num = 72; in setup_vepu540c_me()
1258 regs->reg_base.me_cfg.cime_dist_thre = 1024; in setup_vepu540c_me()
1259 regs->reg_base.me_cfg.rme_dis = 0; in setup_vepu540c_me()
1260 regs->reg_base.me_cfg.fme_dis = 0; in setup_vepu540c_me()
1261 regs->reg_base.me_rnge.dlt_frm_num = 0x0; in setup_vepu540c_me()
1262 calc_cime_parameter(regs); in setup_vepu540c_me()
1286 static void setup_vepu540c_l2(HalVepu540cRegSet *regs, H264eSlice *slice, MppEncHwCfg *hw) in setup_vepu540c_l2() argument
1292 memcpy(regs->reg_s3.rdo_wgta_qp_grpa_0_51, &h264e_lambda_default[6], H264E_LAMBDA_TAB_SIZE); in setup_vepu540c_l2()
1295 regs->reg_s3.RDO_QUANT.quant_f_bias_I = hw->qbias_i; in setup_vepu540c_l2()
1296 regs->reg_s3.RDO_QUANT.quant_f_bias_P = hw->qbias_p; in setup_vepu540c_l2()
1298 regs->reg_s3.RDO_QUANT.quant_f_bias_I = 683; in setup_vepu540c_l2()
1299 regs->reg_s3.RDO_QUANT.quant_f_bias_P = 341; in setup_vepu540c_l2()
1301 regs->reg_s3.iprd_tthdy4_0.iprd_tthdy4_0 = 1; in setup_vepu540c_l2()
1302 regs->reg_s3.iprd_tthdy4_0.iprd_tthdy4_1 = 3; in setup_vepu540c_l2()
1303 regs->reg_s3.iprd_tthdy4_1.iprd_tthdy4_2 = 6; in setup_vepu540c_l2()
1304 regs->reg_s3.iprd_tthdy4_1.iprd_tthdy4_3 = 8; in setup_vepu540c_l2()
1305 regs->reg_s3.iprd_tthdc8_0.iprd_tthdc8_0 = 1; in setup_vepu540c_l2()
1306 regs->reg_s3.iprd_tthdc8_0.iprd_tthdc8_1 = 3; in setup_vepu540c_l2()
1307 regs->reg_s3.iprd_tthdc8_1.iprd_tthdc8_2 = 6; in setup_vepu540c_l2()
1308 regs->reg_s3.iprd_tthdc8_1.iprd_tthdc8_3 = 8; in setup_vepu540c_l2()
1309 regs->reg_s3.iprd_tthdy8_0.iprd_tthdy8_0 = 1; in setup_vepu540c_l2()
1310 regs->reg_s3.iprd_tthdy8_0.iprd_tthdy8_1 = 3; in setup_vepu540c_l2()
1311 regs->reg_s3.iprd_tthdy8_1.iprd_tthdy8_2 = 6; in setup_vepu540c_l2()
1312 regs->reg_s3.iprd_tthdy8_1.iprd_tthdy8_3 = 8; in setup_vepu540c_l2()
1313 regs->reg_s3.iprd_tthd_ul.iprd_tthd_ul = 4; in setup_vepu540c_l2()
1314 regs->reg_s3.iprd_wgty8.iprd_wgty8_0 = 22; in setup_vepu540c_l2()
1315 regs->reg_s3.iprd_wgty8.iprd_wgty8_1 = 23; in setup_vepu540c_l2()
1316 regs->reg_s3.iprd_wgty8.iprd_wgty8_2 = 20; in setup_vepu540c_l2()
1317 regs->reg_s3.iprd_wgty8.iprd_wgty8_3 = 22; in setup_vepu540c_l2()
1318 regs->reg_s3.iprd_wgty4.iprd_wgty4_0 = 22; in setup_vepu540c_l2()
1319 regs->reg_s3.iprd_wgty4.iprd_wgty4_1 = 26; in setup_vepu540c_l2()
1320 regs->reg_s3.iprd_wgty4.iprd_wgty4_2 = 20; in setup_vepu540c_l2()
1321 regs->reg_s3.iprd_wgty4.iprd_wgty4_3 = 22; in setup_vepu540c_l2()
1322 regs->reg_s3.iprd_wgty16.iprd_wgty16_0 = 22; in setup_vepu540c_l2()
1323 regs->reg_s3.iprd_wgty16.iprd_wgty16_1 = 26; in setup_vepu540c_l2()
1324 regs->reg_s3.iprd_wgty16.iprd_wgty16_2 = 20; in setup_vepu540c_l2()
1325 regs->reg_s3.iprd_wgty16.iprd_wgty16_3 = 22; in setup_vepu540c_l2()
1326 regs->reg_s3.iprd_wgtc8.iprd_wgtc8_0 = 18; in setup_vepu540c_l2()
1327 regs->reg_s3.iprd_wgtc8.iprd_wgtc8_1 = 21; in setup_vepu540c_l2()
1328 regs->reg_s3.iprd_wgtc8.iprd_wgtc8_2 = 20; in setup_vepu540c_l2()
1329 regs->reg_s3.iprd_wgtc8.iprd_wgtc8_3 = 19; in setup_vepu540c_l2()
1333 regs->reg_s3.ATR_THD0.atr_thd0 = 1; in setup_vepu540c_l2()
1334 regs->reg_s3.ATR_THD0.atr_thd1 = 2; in setup_vepu540c_l2()
1335 regs->reg_s3.ATR_THD1.atr_thd2 = 6; in setup_vepu540c_l2()
1337 regs->reg_s3.ATR_THD0.atr_thd0 = 2; in setup_vepu540c_l2()
1338 regs->reg_s3.ATR_THD0.atr_thd1 = 4; in setup_vepu540c_l2()
1339 regs->reg_s3.ATR_THD1.atr_thd2 = 9; in setup_vepu540c_l2()
1341 regs->reg_s3.ATR_THD1.atr_thdqp = 32; in setup_vepu540c_l2()
1344 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt0 = 16; in setup_vepu540c_l2()
1345 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt1 = 16; in setup_vepu540c_l2()
1346 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt2 = 16; in setup_vepu540c_l2()
1348 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt0 = 22; in setup_vepu540c_l2()
1349 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt1 = 21; in setup_vepu540c_l2()
1350 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt2 = 20; in setup_vepu540c_l2()
1352 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt0 = 20; in setup_vepu540c_l2()
1353 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt1 = 18; in setup_vepu540c_l2()
1354 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt2 = 16; in setup_vepu540c_l2()
1356 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt0 = 25; in setup_vepu540c_l2()
1357 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt1 = 20; in setup_vepu540c_l2()
1358 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt2 = 16; in setup_vepu540c_l2()
1360 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt0 = 25; in setup_vepu540c_l2()
1361 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt1 = 20; in setup_vepu540c_l2()
1362 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt2 = 18; in setup_vepu540c_l2()
1364 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt0 = 25; in setup_vepu540c_l2()
1365 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt1 = 20; in setup_vepu540c_l2()
1366 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt2 = 16; in setup_vepu540c_l2()
1371 regs->reg_s3.cime_sqi_cfg.cime_pmv_num = 1; in setup_vepu540c_l2()
1372 regs->reg_s3.cime_sqi_cfg.cime_fuse = 1; in setup_vepu540c_l2()
1373 regs->reg_s3.cime_sqi_cfg.itp_mode = 0; in setup_vepu540c_l2()
1374 regs->reg_s3.cime_sqi_cfg.move_lambda = 0; in setup_vepu540c_l2()
1375 regs->reg_s3.cime_sqi_cfg.rime_lvl_mrg = 0; in setup_vepu540c_l2()
1376 regs->reg_s3.cime_sqi_cfg.rime_prelvl_en = 0; in setup_vepu540c_l2()
1377 regs->reg_s3.cime_sqi_cfg.rime_prersu_en = 0; in setup_vepu540c_l2()
1380 regs->reg_s3.cime_mvd_th.cime_mvd_th0 = 16; in setup_vepu540c_l2()
1381 regs->reg_s3.cime_mvd_th.cime_mvd_th1 = 48; in setup_vepu540c_l2()
1382 regs->reg_s3.cime_mvd_th.cime_mvd_th2 = 80; in setup_vepu540c_l2()
1385 regs->reg_s3.cime_madp_th.cime_madp_th = 16; in setup_vepu540c_l2()
1388 regs->reg_s3.cime_multi.cime_multi0 = 8; in setup_vepu540c_l2()
1389 regs->reg_s3.cime_multi.cime_multi1 = 12; in setup_vepu540c_l2()
1390 regs->reg_s3.cime_multi.cime_multi2 = 16; in setup_vepu540c_l2()
1391 regs->reg_s3.cime_multi.cime_multi3 = 20; in setup_vepu540c_l2()
1397 regs->reg_s3.rime_mvd_th.rime_mvd_th0 = 1; in setup_vepu540c_l2()
1398 regs->reg_s3.rime_mvd_th.rime_mvd_th1 = 2; in setup_vepu540c_l2()
1399 regs->reg_s3.rime_mvd_th.fme_madp_th = 0; in setup_vepu540c_l2()
1402 regs->reg_s3.rime_madp_th.rime_madp_th0 = 8; in setup_vepu540c_l2()
1403 regs->reg_s3.rime_madp_th.rime_madp_th1 = 16; in setup_vepu540c_l2()
1406 regs->reg_s3.rime_multi.rime_multi0 = 4; in setup_vepu540c_l2()
1407 regs->reg_s3.rime_multi.rime_multi1 = 8; in setup_vepu540c_l2()
1408 regs->reg_s3.rime_multi.rime_multi2 = 12; in setup_vepu540c_l2()
1411 regs->reg_s3.cmv_st_th.cmv_th0 = 64; in setup_vepu540c_l2()
1412 regs->reg_s3.cmv_st_th.cmv_th1 = 96; in setup_vepu540c_l2()
1413 regs->reg_s3.cmv_st_th.cmv_th2 = 128; in setup_vepu540c_l2()
1418 regs->reg_rc_roi.madi_st_thd.madi_th0 = 5; in setup_vepu540c_l2()
1419 regs->reg_rc_roi.madi_st_thd.madi_th1 = 12; in setup_vepu540c_l2()
1420 regs->reg_rc_roi.madi_st_thd.madi_th2 = 20; in setup_vepu540c_l2()
1422 regs->reg_rc_roi.madp_st_thd0.madp_th0 = 4 << 4; in setup_vepu540c_l2()
1423 regs->reg_rc_roi.madp_st_thd0.madp_th1 = 9 << 4; in setup_vepu540c_l2()
1425 regs->reg_rc_roi.madp_st_thd1.madp_th2 = 15 << 4; in setup_vepu540c_l2()
1430 regs->reg_rc_roi.aq_tthd[i] = hw->aq_thrd_i[i]; in setup_vepu540c_l2()
1431 regs->reg_rc_roi.aq_step[i] = hw->aq_step_i[i] & 0x3f; in setup_vepu540c_l2()
1435 regs->reg_rc_roi.aq_tthd[i] = hw->aq_thrd_p[i]; in setup_vepu540c_l2()
1436 regs->reg_rc_roi.aq_step[i] = hw->aq_step_p[i] & 0x3f; in setup_vepu540c_l2()
1443 static void setup_vepu540c_ext_line_buf(HalVepu540cRegSet *regs, HalH264eVepu540cCtx *ctx) in setup_vepu540c_ext_line_buf() argument
1448 regs->reg_base.ebuft_addr = fd; in setup_vepu540c_ext_line_buf()
1449 regs->reg_base.ebufb_addr = fd; in setup_vepu540c_ext_line_buf()
1453 regs->reg_base.ebuft_addr = 0; in setup_vepu540c_ext_line_buf()
1454 regs->reg_base.ebufb_addr = 0; in setup_vepu540c_ext_line_buf()
1461 HalVepu540cRegSet *regs = ctx->regs_set; in hal_h264e_vepu540c_gen_regs() local
1472 memset(regs, 0, sizeof(*regs)); in hal_h264e_vepu540c_gen_regs()
1474 setup_vepu540c_normal(regs); in hal_h264e_vepu540c_gen_regs()
1475 ret = setup_vepu540c_prep(regs, &ctx->cfg->prep); in hal_h264e_vepu540c_gen_regs()
1479 setup_vepu540c_codec(regs, sps, pps, slice); in hal_h264e_vepu540c_gen_regs()
1480 setup_vepu540c_rdo_pred(regs, sps, pps, slice); in hal_h264e_vepu540c_gen_regs()
1481 setup_vepu540c_rdo_cfg(®s->reg_rdo); in hal_h264e_vepu540c_gen_regs()
1484 …memcpy(®s->reg_scl.q_intra_y8, vepu580_540_h264_flat_scl_tab, sizeof(vepu580_540_h264_flat_scl_… in hal_h264e_vepu540c_gen_regs()
1486 setup_vepu540c_rc_base(regs, ctx, task->rc_task); in hal_h264e_vepu540c_gen_regs()
1487 setup_vepu540c_io_buf(regs, ctx->dev, task); in hal_h264e_vepu540c_gen_regs()
1488 setup_vepu540c_recn_refr(ctx, regs); in hal_h264e_vepu540c_gen_regs()
1490 regs->reg_base.meiw_addr = task->md_info ? mpp_buffer_get_fd(task->md_info) : 0; in hal_h264e_vepu540c_gen_regs()
1492 regs->reg_base.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); in hal_h264e_vepu540c_gen_regs()
1493 regs->reg_base.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); in hal_h264e_vepu540c_gen_regs()
1495 setup_vepu540c_split(regs, cfg); in hal_h264e_vepu540c_gen_regs()
1496 setup_vepu540c_me(regs, sps, slice); in hal_h264e_vepu540c_gen_regs()
1499 setup_vepu540c_ext_line_buf(regs, ctx); in hal_h264e_vepu540c_gen_regs()