34     Vpu1H263dRegSet_t *regs = (Vpu1H263dRegSet_t*)ctx->regs;  in vpu1_h263d_setup_regs_by_syntax()  local
61     regs->SwReg04.sw_pic_mb_width = (pp->vop_width  + 15) >> 4;  in vpu1_h263d_setup_regs_by_syntax()
62     regs->SwReg04.sw_pic_mb_hight_p = (pp->vop_height + 15) >> 4;  in vpu1_h263d_setup_regs_by_syntax()
63     regs->SwReg04.sw_mb_width_off = pp->vop_width & 0xf;  in vpu1_h263d_setup_regs_by_syntax()
64     regs->SwReg04.sw_mb_height_off = pp->vop_height & 0xf;  in vpu1_h263d_setup_regs_by_syntax()
66     regs->SwReg03.sw_dec_mode = 2;  in vpu1_h263d_setup_regs_by_syntax()
67     regs->SwReg03.sw_filtering_dis = 1;  in vpu1_h263d_setup_regs_by_syntax()
68     regs->SwReg18.sw_h263_vc1_rc = 0;  in vpu1_h263d_setup_regs_by_syntax()
69     regs->SwReg06.sw_init_qp = pp->vop_quant;  in vpu1_h263d_setup_regs_by_syntax()
70     regs->SwReg05.sw_sync_markers_e = 1;  in vpu1_h263d_setup_regs_by_syntax()
79         RK_U32 val = regs->SwReg12.sw_rlc_vlc_base;  in vpu1_h263d_setup_regs_by_syntax()
87         regs->SwReg12.sw_rlc_vlc_base = val;  in vpu1_h263d_setup_regs_by_syntax()
88         regs->SwReg05.sw_strm_start_bit = start_bit_offset;  in vpu1_h263d_setup_regs_by_syntax()
89         regs->SwReg06.sw_stream_len = left_bytes;  in vpu1_h263d_setup_regs_by_syntax()
92     regs->SwReg05.sw_vop_time_incr = pp->vop_time_increment_resolution;  in vpu1_h263d_setup_regs_by_syntax()
96         regs->SwReg03.sw_pic_inter_e = 1;  in vpu1_h263d_setup_regs_by_syntax()
99             regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_ref0;  in vpu1_h263d_setup_regs_by_syntax()
100             regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_ref0;  in vpu1_h263d_setup_regs_by_syntax()
102             regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr;  in vpu1_h263d_setup_regs_by_syntax()
103             regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_curr;  in vpu1_h263d_setup_regs_by_syntax()
107         regs->SwReg03.sw_pic_inter_e = 0;  in vpu1_h263d_setup_regs_by_syntax()
109         regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr;  in vpu1_h263d_setup_regs_by_syntax()
110         regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_curr;  in vpu1_h263d_setup_regs_by_syntax()
117     regs->SwReg18.sw_fcode_fwd_hor = 1;  in vpu1_h263d_setup_regs_by_syntax()
118     regs->SwReg18.sw_fcode_fwd_ver = 1;  in vpu1_h263d_setup_regs_by_syntax()
119     regs->SwReg18.sw_prev_anc_type = (pp->prev_coding_type == H263_P_VOP);  in vpu1_h263d_setup_regs_by_syntax()
125     Vpu1H263dRegSet_t *regs = NULL;  in hal_vpu1_h263d_init()  local
130     regs = mpp_calloc(Vpu1H263dRegSet_t, 1);  in hal_vpu1_h263d_init()
131     if (NULL == regs) {  in hal_vpu1_h263d_init()
147     ctx->regs       = (void*)regs;  in hal_vpu1_h263d_init()
151     if (regs) {  in hal_vpu1_h263d_init()
152         mpp_free(regs);  in hal_vpu1_h263d_init()
153         regs = NULL;  in hal_vpu1_h263d_init()
166     if (ctx->regs) {  in hal_vpu1_h263d_deinit()
167         mpp_free(ctx->regs);  in hal_vpu1_h263d_deinit()
168         ctx->regs = NULL;  in hal_vpu1_h263d_deinit()
187     Vpu1H263dRegSet_t *regs = (Vpu1H263dRegSet_t*)ctx->regs;  in hal_vpu1_h263d_gen_regs()  local
193     memset(regs, 0, sizeof(Vpu1H263dRegSet_t));  in hal_vpu1_h263d_gen_regs()
198     regs->SwReg02.sw_dec_out_endian = 1;  in hal_vpu1_h263d_gen_regs()
199     regs->SwReg02.sw_dec_in_endian = 1;  in hal_vpu1_h263d_gen_regs()
200     regs->SwReg02.sw_dec_inswap32_e = 1;  in hal_vpu1_h263d_gen_regs()
201     regs->SwReg02.sw_dec_outswap32_e = 1;  in hal_vpu1_h263d_gen_regs()
202     regs->SwReg02.sw_dec_strswap32_e = 1;  in hal_vpu1_h263d_gen_regs()
203     regs->SwReg02.sw_dec_strendian_e = 1;  in hal_vpu1_h263d_gen_regs()
204     regs->SwReg02.sw_dec_max_burst = 16;  in hal_vpu1_h263d_gen_regs()
205     regs->SwReg55.sw_apf_threshold = 1;  in hal_vpu1_h263d_gen_regs()
206     regs->SwReg02.sw_dec_timeout_e = 1;  in hal_vpu1_h263d_gen_regs()
207     regs->SwReg02.sw_dec_clk_gate_e = 1;  in hal_vpu1_h263d_gen_regs()
208     regs->SwReg01.sw_dec_en = 1;  in hal_vpu1_h263d_gen_regs()
209     regs->SwReg49.sw_pred_bc_tap_0_0 = -1;  in hal_vpu1_h263d_gen_regs()
210     regs->SwReg49.sw_pred_bc_tap_0_1 = 3;  in hal_vpu1_h263d_gen_regs()
211     regs->SwReg49.sw_pred_bc_tap_0_2 = -6;  in hal_vpu1_h263d_gen_regs()
212     regs->SwReg34.sw_pred_bc_tap_0_3 = 20;  in hal_vpu1_h263d_gen_regs()
223     regs->SwReg13.dec_out_st_adr = (RK_U32)ctx->fd_curr;  in hal_vpu1_h263d_gen_regs()
224     regs->SwReg12.sw_rlc_vlc_base = mpp_buffer_get_fd(buf_pkt);  in hal_vpu1_h263d_gen_regs()
236     RK_U32 *regs = (RK_U32 *)ctx->regs;  in hal_vpu1_h263d_start()  local
243             mpp_log("reg[%03d]: %08x\n", i, regs[i]);  in hal_vpu1_h263d_start()
250         wr_cfg.reg = regs;  in hal_vpu1_h263d_start()
260         rd_cfg.reg = regs;  in hal_vpu1_h263d_start()
291         RK_U32 *regs = (RK_U32 *)ctx->regs;  in hal_vpu1_h263d_wait()  local
296             mpp_log("reg[%03d]: %08x\n", i, regs[i]);  in hal_vpu1_h263d_wait()