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Searched refs:cpll (Results 1 – 25 of 25) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/m68k/cpu/mcf52x2/
H A Dspeed.c29 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
47 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
48 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
/OK3568_Linux_fs/kernel/drivers/clk/pxa/
H A Dclk-pxa.c214 rate = freqs[i].cpll; in pxa2xx_determine_rate()
232 rate = freqs[closest_below].cpll; in pxa2xx_determine_rate()
234 rate = freqs[closest_above].cpll; in pxa2xx_determine_rate()
H A Dclk-pxa.h135 unsigned long cpll; member
H A Dclk-pxa25x.c265 if (pxa25x_freqs[i].cpll == rate) in clk_pxa25x_cpll_set_rate()
H A Dclk-pxa27x.c257 if (pxa27x_freqs[i].cpll == rate) in clk_pxa27x_cpll_set_rate()
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-exynos5410.c61 apll, cpll, epll, mpll, enumerator
242 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
H A Dclk-exynos5250.c105 apll, mpll, cpll, epll, vpll, gpll, bpll, enumerator
741 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
H A Dclk-exynos5420.c150 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator
1464 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-rk3188.c21 apll, cpll, dpll, gpll, enumerator
221 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
232 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
H A Dclk-rk3128.c21 apll, dpll, cpll, gpll, enumerator
165 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
H A Dclk-rk3228.c21 apll, dpll, cpll, gpll, enumerator
174 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
H A Dclk-rk3328.c23 apll, dpll, cpll, gpll, npll, enumerator
223 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
H A Dclk-rv1126.c29 apll, dpll, cpll, hpll, enumerator
239 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
246 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
H A Dclk-rk3368.c19 apllb, aplll, dpll, cpll, gpll, npll, enumerator
155 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
H A Dclk-rk3399.c19 lpll, bpll, dpll, cpll, gpll, npll, vpll, enumerator
301 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
304 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
H A Dclk-rk3288.c27 apll, dpll, cpll, gpll, npll, enumerator
240 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
H A Dclk-px30.c21 apll, dpll, cpll, npll, apll_b_h, apll_b_l, enumerator
196 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
H A Dclk-rk3528.c20 apll, cpll, gpll, ppll, dpll, enumerator
178 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
H A Dclk-rk3562.c20 apll, gpll, vpll, hpll, cpll, dpll, enumerator
136 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
H A Dclk-rk1808.c24 apll, dpll, cpll, gpll, npll, ppll, enumerator
191 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p,
H A Dclk-rv1106.c62 apll, dpll, cpll, gpll, enumerator
256 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
H A Dclk-rk3568.c31 apll, dpll, gpll, cpll, npll, vpll, enumerator
335 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
H A Dclk-rk3588.c22 b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, enumerator
662 [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p,
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c1268 u32 apllb, aplll, dpll, cpll, gpll; in rkclk_init() local
1284 cpll = rkclk_pll_get_rate(cru, CPLL); in rkclk_init()
1288 __func__, apllb, aplll, dpll, cpll, gpll); in rkclk_init()
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3328.dtsi780 * We need set cpll child clk div first,
781 * and then set the cpll frequency.