1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 i2c0 = &i2c0; 31 i2c1 = &i2c1; 32 i2c2 = &i2c2; 33 i2c3 = &i2c3; 34 ethernet0 = &gmac2io; 35 ethernet1 = &gmac2phy; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53"; 45 reg = <0x0 0x0>; 46 clocks = <&cru ARMCLK>; 47 #cooling-cells = <2>; 48 cpu-idle-states = <&CPU_SLEEP>; 49 dynamic-power-coefficient = <120>; 50 enable-method = "psci"; 51 next-level-cache = <&l2>; 52 operating-points-v2 = <&cpu0_opp_table>; 53 }; 54 55 cpu1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 reg = <0x0 0x1>; 59 clocks = <&cru ARMCLK>; 60 #cooling-cells = <2>; 61 cpu-idle-states = <&CPU_SLEEP>; 62 dynamic-power-coefficient = <120>; 63 enable-method = "psci"; 64 next-level-cache = <&l2>; 65 operating-points-v2 = <&cpu0_opp_table>; 66 }; 67 68 cpu2: cpu@2 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x2>; 72 clocks = <&cru ARMCLK>; 73 #cooling-cells = <2>; 74 cpu-idle-states = <&CPU_SLEEP>; 75 dynamic-power-coefficient = <120>; 76 enable-method = "psci"; 77 next-level-cache = <&l2>; 78 operating-points-v2 = <&cpu0_opp_table>; 79 }; 80 81 cpu3: cpu@3 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x3>; 85 clocks = <&cru ARMCLK>; 86 #cooling-cells = <2>; 87 cpu-idle-states = <&CPU_SLEEP>; 88 dynamic-power-coefficient = <120>; 89 enable-method = "psci"; 90 next-level-cache = <&l2>; 91 operating-points-v2 = <&cpu0_opp_table>; 92 }; 93 94 idle-states { 95 entry-method = "psci"; 96 97 CPU_SLEEP: cpu-sleep { 98 compatible = "arm,idle-state"; 99 local-timer-stop; 100 arm,psci-suspend-param = <0x0010000>; 101 entry-latency-us = <120>; 102 exit-latency-us = <250>; 103 min-residency-us = <900>; 104 }; 105 }; 106 107 l2: l2-cache0 { 108 compatible = "cache"; 109 }; 110 }; 111 112 cpu0_opp_table: opp_table0 { 113 compatible = "operating-points-v2"; 114 opp-shared; 115 116 opp-408000000 { 117 opp-hz = /bits/ 64 <408000000>; 118 opp-microvolt = <950000>; 119 clock-latency-ns = <40000>; 120 opp-suspend; 121 }; 122 opp-600000000 { 123 opp-hz = /bits/ 64 <600000000>; 124 opp-microvolt = <950000>; 125 clock-latency-ns = <40000>; 126 }; 127 opp-816000000 { 128 opp-hz = /bits/ 64 <816000000>; 129 opp-microvolt = <1000000>; 130 clock-latency-ns = <40000>; 131 }; 132 opp-1008000000 { 133 opp-hz = /bits/ 64 <1008000000>; 134 opp-microvolt = <1100000>; 135 clock-latency-ns = <40000>; 136 }; 137 opp-1200000000 { 138 opp-hz = /bits/ 64 <1200000000>; 139 opp-microvolt = <1225000>; 140 clock-latency-ns = <40000>; 141 }; 142 opp-1296000000 { 143 opp-hz = /bits/ 64 <1296000000>; 144 opp-microvolt = <1300000>; 145 clock-latency-ns = <40000>; 146 }; 147 }; 148 149 amba: bus { 150 compatible = "simple-bus"; 151 #address-cells = <2>; 152 #size-cells = <2>; 153 ranges; 154 155 dmac: dmac@ff1f0000 { 156 compatible = "arm,pl330", "arm,primecell"; 157 reg = <0x0 0xff1f0000 0x0 0x4000>; 158 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 160 arm,pl330-periph-burst; 161 clocks = <&cru ACLK_DMAC>; 162 clock-names = "apb_pclk"; 163 #dma-cells = <1>; 164 }; 165 }; 166 167 analog_sound: analog-sound { 168 compatible = "simple-audio-card"; 169 simple-audio-card,format = "i2s"; 170 simple-audio-card,mclk-fs = <256>; 171 simple-audio-card,name = "Analog"; 172 status = "disabled"; 173 174 simple-audio-card,cpu { 175 sound-dai = <&i2s1>; 176 }; 177 178 simple-audio-card,codec { 179 sound-dai = <&codec>; 180 }; 181 }; 182 183 arm-pmu { 184 compatible = "arm,cortex-a53-pmu"; 185 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 189 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 190 }; 191 192 display_subsystem: display-subsystem { 193 compatible = "rockchip,display-subsystem"; 194 ports = <&vop_out>; 195 }; 196 197 hdmi_sound: hdmi-sound { 198 compatible = "simple-audio-card"; 199 simple-audio-card,format = "i2s"; 200 simple-audio-card,mclk-fs = <128>; 201 simple-audio-card,name = "HDMI"; 202 status = "disabled"; 203 204 simple-audio-card,cpu { 205 sound-dai = <&i2s0>; 206 }; 207 208 simple-audio-card,codec { 209 sound-dai = <&hdmi>; 210 }; 211 }; 212 213 psci { 214 compatible = "arm,psci-1.0", "arm,psci-0.2"; 215 method = "smc"; 216 }; 217 218 timer { 219 compatible = "arm,armv8-timer"; 220 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 221 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 222 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 223 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 224 }; 225 226 xin24m: xin24m { 227 compatible = "fixed-clock"; 228 #clock-cells = <0>; 229 clock-frequency = <24000000>; 230 clock-output-names = "xin24m"; 231 }; 232 233 i2s0: i2s@ff000000 { 234 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 235 reg = <0x0 0xff000000 0x0 0x1000>; 236 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 238 clock-names = "i2s_clk", "i2s_hclk"; 239 dmas = <&dmac 11>, <&dmac 12>; 240 dma-names = "tx", "rx"; 241 #sound-dai-cells = <0>; 242 status = "disabled"; 243 }; 244 245 i2s1: i2s@ff010000 { 246 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 247 reg = <0x0 0xff010000 0x0 0x1000>; 248 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 250 clock-names = "i2s_clk", "i2s_hclk"; 251 dmas = <&dmac 14>, <&dmac 15>; 252 dma-names = "tx", "rx"; 253 #sound-dai-cells = <0>; 254 status = "disabled"; 255 }; 256 257 i2s2: i2s@ff020000 { 258 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 259 reg = <0x0 0xff020000 0x0 0x1000>; 260 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 262 clock-names = "i2s_clk", "i2s_hclk"; 263 dmas = <&dmac 0>, <&dmac 1>; 264 dma-names = "tx", "rx"; 265 #sound-dai-cells = <0>; 266 status = "disabled"; 267 }; 268 269 spdif: spdif@ff030000 { 270 compatible = "rockchip,rk3328-spdif"; 271 reg = <0x0 0xff030000 0x0 0x1000>; 272 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 274 clock-names = "mclk", "hclk"; 275 dmas = <&dmac 10>; 276 dma-names = "tx"; 277 pinctrl-names = "default"; 278 pinctrl-0 = <&spdifm2_tx>; 279 #sound-dai-cells = <0>; 280 status = "disabled"; 281 }; 282 283 pdm: pdm@ff040000 { 284 compatible = "rockchip,pdm"; 285 reg = <0x0 0xff040000 0x0 0x1000>; 286 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 287 clock-names = "pdm_clk", "pdm_hclk"; 288 dmas = <&dmac 16>; 289 dma-names = "rx"; 290 pinctrl-names = "default", "sleep"; 291 pinctrl-0 = <&pdmm0_clk 292 &pdmm0_sdi0 293 &pdmm0_sdi1 294 &pdmm0_sdi2 295 &pdmm0_sdi3>; 296 pinctrl-1 = <&pdmm0_clk_sleep 297 &pdmm0_sdi0_sleep 298 &pdmm0_sdi1_sleep 299 &pdmm0_sdi2_sleep 300 &pdmm0_sdi3_sleep>; 301 status = "disabled"; 302 }; 303 304 grf: syscon@ff100000 { 305 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 306 reg = <0x0 0xff100000 0x0 0x1000>; 307 308 io_domains: io-domains { 309 compatible = "rockchip,rk3328-io-voltage-domain"; 310 status = "disabled"; 311 }; 312 313 grf_gpio: grf-gpio { 314 compatible = "rockchip,rk3328-grf-gpio"; 315 gpio-controller; 316 #gpio-cells = <2>; 317 }; 318 319 power: power-controller { 320 compatible = "rockchip,rk3328-power-controller"; 321 #power-domain-cells = <1>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 325 power-domain@RK3328_PD_HEVC { 326 reg = <RK3328_PD_HEVC>; 327 }; 328 power-domain@RK3328_PD_VIDEO { 329 reg = <RK3328_PD_VIDEO>; 330 }; 331 power-domain@RK3328_PD_VPU { 332 reg = <RK3328_PD_VPU>; 333 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 334 }; 335 }; 336 337 reboot-mode { 338 compatible = "syscon-reboot-mode"; 339 offset = <0x5c8>; 340 mode-normal = <BOOT_NORMAL>; 341 mode-recovery = <BOOT_RECOVERY>; 342 mode-bootloader = <BOOT_FASTBOOT>; 343 mode-loader = <BOOT_BL_DOWNLOAD>; 344 }; 345 }; 346 347 uart0: serial@ff110000 { 348 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 349 reg = <0x0 0xff110000 0x0 0x100>; 350 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 352 clock-names = "baudclk", "apb_pclk"; 353 dmas = <&dmac 2>, <&dmac 3>; 354 dma-names = "tx", "rx"; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 357 reg-io-width = <4>; 358 reg-shift = <2>; 359 status = "disabled"; 360 }; 361 362 uart1: serial@ff120000 { 363 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 364 reg = <0x0 0xff120000 0x0 0x100>; 365 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 367 clock-names = "baudclk", "apb_pclk"; 368 dmas = <&dmac 4>, <&dmac 5>; 369 dma-names = "tx", "rx"; 370 pinctrl-names = "default"; 371 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 372 reg-io-width = <4>; 373 reg-shift = <2>; 374 status = "disabled"; 375 }; 376 377 uart2: serial@ff130000 { 378 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 379 reg = <0x0 0xff130000 0x0 0x100>; 380 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 382 clock-names = "baudclk", "apb_pclk"; 383 dmas = <&dmac 6>, <&dmac 7>; 384 dma-names = "tx", "rx"; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&uart2m1_xfer>; 387 reg-io-width = <4>; 388 reg-shift = <2>; 389 status = "disabled"; 390 }; 391 392 i2c0: i2c@ff150000 { 393 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 394 reg = <0x0 0xff150000 0x0 0x1000>; 395 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 399 clock-names = "i2c", "pclk"; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&i2c0_xfer>; 402 status = "disabled"; 403 }; 404 405 i2c1: i2c@ff160000 { 406 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 407 reg = <0x0 0xff160000 0x0 0x1000>; 408 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 412 clock-names = "i2c", "pclk"; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&i2c1_xfer>; 415 status = "disabled"; 416 }; 417 418 i2c2: i2c@ff170000 { 419 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 420 reg = <0x0 0xff170000 0x0 0x1000>; 421 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 425 clock-names = "i2c", "pclk"; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&i2c2_xfer>; 428 status = "disabled"; 429 }; 430 431 i2c3: i2c@ff180000 { 432 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 433 reg = <0x0 0xff180000 0x0 0x1000>; 434 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 438 clock-names = "i2c", "pclk"; 439 pinctrl-names = "default"; 440 pinctrl-0 = <&i2c3_xfer>; 441 status = "disabled"; 442 }; 443 444 spi0: spi@ff190000 { 445 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 446 reg = <0x0 0xff190000 0x0 0x1000>; 447 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 451 clock-names = "spiclk", "apb_pclk"; 452 dmas = <&dmac 8>, <&dmac 9>; 453 dma-names = "tx", "rx"; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 456 status = "disabled"; 457 }; 458 459 wdt: watchdog@ff1a0000 { 460 compatible = "snps,dw-wdt"; 461 reg = <0x0 0xff1a0000 0x0 0x100>; 462 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&cru PCLK_BUS_PRE>; 464 }; 465 466 pwm0: pwm@ff1b0000 { 467 compatible = "rockchip,rk3328-pwm"; 468 reg = <0x0 0xff1b0000 0x0 0x10>; 469 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 470 clock-names = "pwm", "pclk"; 471 pinctrl-names = "active"; 472 pinctrl-0 = <&pwm0_pin>; 473 #pwm-cells = <3>; 474 status = "disabled"; 475 }; 476 477 pwm1: pwm@ff1b0010 { 478 compatible = "rockchip,rk3328-pwm"; 479 reg = <0x0 0xff1b0010 0x0 0x10>; 480 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 481 clock-names = "pwm", "pclk"; 482 pinctrl-names = "active"; 483 pinctrl-0 = <&pwm1_pin>; 484 #pwm-cells = <3>; 485 status = "disabled"; 486 }; 487 488 pwm2: pwm@ff1b0020 { 489 compatible = "rockchip,rk3328-pwm"; 490 reg = <0x0 0xff1b0020 0x0 0x10>; 491 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 492 clock-names = "pwm", "pclk"; 493 pinctrl-names = "active"; 494 pinctrl-0 = <&pwm2_pin>; 495 #pwm-cells = <3>; 496 status = "disabled"; 497 }; 498 499 pwm3: pwm@ff1b0030 { 500 compatible = "rockchip,rk3328-pwm"; 501 reg = <0x0 0xff1b0030 0x0 0x10>; 502 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 504 clock-names = "pwm", "pclk"; 505 pinctrl-names = "active"; 506 pinctrl-0 = <&pwmir_pin>; 507 #pwm-cells = <3>; 508 status = "disabled"; 509 }; 510 511 thermal-zones { 512 soc_thermal: soc-thermal { 513 polling-delay-passive = <20>; 514 polling-delay = <1000>; 515 sustainable-power = <1000>; 516 517 thermal-sensors = <&tsadc 0>; 518 519 trips { 520 threshold: trip-point0 { 521 temperature = <70000>; 522 hysteresis = <2000>; 523 type = "passive"; 524 }; 525 target: trip-point1 { 526 temperature = <85000>; 527 hysteresis = <2000>; 528 type = "passive"; 529 }; 530 soc_crit: soc-crit { 531 temperature = <95000>; 532 hysteresis = <2000>; 533 type = "critical"; 534 }; 535 }; 536 537 cooling-maps { 538 map0 { 539 trip = <&target>; 540 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 541 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 542 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 543 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 544 contribution = <4096>; 545 }; 546 }; 547 }; 548 549 }; 550 551 tsadc: tsadc@ff250000 { 552 compatible = "rockchip,rk3328-tsadc"; 553 reg = <0x0 0xff250000 0x0 0x100>; 554 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 555 assigned-clocks = <&cru SCLK_TSADC>; 556 assigned-clock-rates = <50000>; 557 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 558 clock-names = "tsadc", "apb_pclk"; 559 pinctrl-names = "gpio", "otpout"; 560 pinctrl-0 = <&otp_pin>; 561 pinctrl-1 = <&otp_out>; 562 resets = <&cru SRST_TSADC>; 563 reset-names = "tsadc-apb"; 564 rockchip,grf = <&grf>; 565 rockchip,hw-tshut-temp = <100000>; 566 #thermal-sensor-cells = <1>; 567 status = "disabled"; 568 }; 569 570 efuse: efuse@ff260000 { 571 compatible = "rockchip,rk3328-efuse"; 572 reg = <0x0 0xff260000 0x0 0x50>; 573 #address-cells = <1>; 574 #size-cells = <1>; 575 clocks = <&cru SCLK_EFUSE>; 576 clock-names = "pclk_efuse"; 577 rockchip,efuse-size = <0x20>; 578 579 /* Data cells */ 580 efuse_id: id@7 { 581 reg = <0x07 0x10>; 582 }; 583 cpu_leakage: cpu-leakage@17 { 584 reg = <0x17 0x1>; 585 }; 586 logic_leakage: logic-leakage@19 { 587 reg = <0x19 0x1>; 588 }; 589 efuse_cpu_version: cpu-version@1a { 590 reg = <0x1a 0x1>; 591 bits = <3 3>; 592 }; 593 }; 594 595 saradc: adc@ff280000 { 596 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 597 reg = <0x0 0xff280000 0x0 0x100>; 598 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 599 #io-channel-cells = <1>; 600 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 601 clock-names = "saradc", "apb_pclk"; 602 resets = <&cru SRST_SARADC_P>; 603 reset-names = "saradc-apb"; 604 status = "disabled"; 605 }; 606 607 gpu: gpu@ff300000 { 608 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 609 reg = <0x0 0xff300000 0x0 0x30000>; 610 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 617 interrupt-names = "gp", 618 "gpmmu", 619 "pp", 620 "pp0", 621 "ppmmu0", 622 "pp1", 623 "ppmmu1"; 624 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 625 clock-names = "bus", "core"; 626 resets = <&cru SRST_GPU_A>; 627 }; 628 629 h265e_mmu: iommu@ff330200 { 630 compatible = "rockchip,iommu"; 631 reg = <0x0 0xff330200 0 0x100>; 632 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 633 interrupt-names = "h265e_mmu"; 634 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 635 clock-names = "aclk", "iface"; 636 #iommu-cells = <0>; 637 status = "disabled"; 638 }; 639 640 vepu_mmu: iommu@ff340800 { 641 compatible = "rockchip,iommu"; 642 reg = <0x0 0xff340800 0x0 0x40>; 643 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 644 interrupt-names = "vepu_mmu"; 645 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 646 clock-names = "aclk", "iface"; 647 #iommu-cells = <0>; 648 status = "disabled"; 649 }; 650 651 vpu: video-codec@ff350000 { 652 compatible = "rockchip,rk3328-vpu"; 653 reg = <0x0 0xff350000 0x0 0x800>; 654 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 655 interrupt-names = "vdpu"; 656 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 657 clock-names = "aclk", "hclk"; 658 iommus = <&vpu_mmu>; 659 power-domains = <&power RK3328_PD_VPU>; 660 }; 661 662 vpu_mmu: iommu@ff350800 { 663 compatible = "rockchip,iommu"; 664 reg = <0x0 0xff350800 0x0 0x40>; 665 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 666 interrupt-names = "vpu_mmu"; 667 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 668 clock-names = "aclk", "iface"; 669 #iommu-cells = <0>; 670 power-domains = <&power RK3328_PD_VPU>; 671 }; 672 673 rkvdec_mmu: iommu@ff360480 { 674 compatible = "rockchip,iommu"; 675 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 676 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 677 interrupt-names = "rkvdec_mmu"; 678 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 679 clock-names = "aclk", "iface"; 680 #iommu-cells = <0>; 681 status = "disabled"; 682 }; 683 684 vop: vop@ff370000 { 685 compatible = "rockchip,rk3328-vop"; 686 reg = <0x0 0xff370000 0x0 0x3efc>; 687 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 689 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 690 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 691 reset-names = "axi", "ahb", "dclk"; 692 iommus = <&vop_mmu>; 693 status = "disabled"; 694 695 vop_out: port { 696 #address-cells = <1>; 697 #size-cells = <0>; 698 699 vop_out_hdmi: endpoint@0 { 700 reg = <0>; 701 remote-endpoint = <&hdmi_in_vop>; 702 }; 703 }; 704 }; 705 706 vop_mmu: iommu@ff373f00 { 707 compatible = "rockchip,iommu"; 708 reg = <0x0 0xff373f00 0x0 0x100>; 709 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 710 interrupt-names = "vop_mmu"; 711 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 712 clock-names = "aclk", "iface"; 713 #iommu-cells = <0>; 714 status = "disabled"; 715 }; 716 717 hdmi: hdmi@ff3c0000 { 718 compatible = "rockchip,rk3328-dw-hdmi"; 719 reg = <0x0 0xff3c0000 0x0 0x20000>; 720 reg-io-width = <4>; 721 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&cru PCLK_HDMI>, 724 <&cru SCLK_HDMI_SFC>, 725 <&cru SCLK_RTC32K>; 726 clock-names = "iahb", 727 "isfr", 728 "cec"; 729 phys = <&hdmiphy>; 730 phy-names = "hdmi"; 731 pinctrl-names = "default"; 732 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 733 rockchip,grf = <&grf>; 734 #sound-dai-cells = <0>; 735 status = "disabled"; 736 737 ports { 738 hdmi_in: port { 739 hdmi_in_vop: endpoint { 740 remote-endpoint = <&vop_out_hdmi>; 741 }; 742 }; 743 }; 744 }; 745 746 codec: codec@ff410000 { 747 compatible = "rockchip,rk3328-codec"; 748 reg = <0x0 0xff410000 0x0 0x1000>; 749 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 750 clock-names = "pclk", "mclk"; 751 rockchip,grf = <&grf>; 752 #sound-dai-cells = <0>; 753 status = "disabled"; 754 }; 755 756 hdmiphy: phy@ff430000 { 757 compatible = "rockchip,rk3328-hdmi-phy"; 758 reg = <0x0 0xff430000 0x0 0x10000>; 759 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 761 clock-names = "sysclk", "refoclk", "refpclk"; 762 clock-output-names = "hdmi_phy"; 763 #clock-cells = <0>; 764 nvmem-cells = <&efuse_cpu_version>; 765 nvmem-cell-names = "cpu-version"; 766 #phy-cells = <0>; 767 status = "disabled"; 768 }; 769 770 cru: clock-controller@ff440000 { 771 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 772 reg = <0x0 0xff440000 0x0 0x1000>; 773 rockchip,grf = <&grf>; 774 #clock-cells = <1>; 775 #reset-cells = <1>; 776 assigned-clocks = 777 /* 778 * CPLL should run at 1200, but that is to high for 779 * the initial dividers of most of its children. 780 * We need set cpll child clk div first, 781 * and then set the cpll frequency. 782 */ 783 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 784 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 785 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 786 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 787 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 788 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 789 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 790 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 791 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 792 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 793 <&cru SCLK_WIFI>, <&cru ARMCLK>, 794 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 795 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 796 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 797 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 798 <&cru SCLK_RTC32K>; 799 assigned-clock-parents = 800 <&cru HDMIPHY>, <&cru PLL_APLL>, 801 <&cru PLL_GPLL>, <&xin24m>, 802 <&xin24m>, <&xin24m>; 803 assigned-clock-rates = 804 <0>, <61440000>, 805 <0>, <24000000>, 806 <24000000>, <24000000>, 807 <15000000>, <15000000>, 808 <100000000>, <100000000>, 809 <100000000>, <100000000>, 810 <50000000>, <100000000>, 811 <100000000>, <100000000>, 812 <50000000>, <50000000>, 813 <50000000>, <50000000>, 814 <24000000>, <600000000>, 815 <491520000>, <1200000000>, 816 <150000000>, <75000000>, 817 <75000000>, <150000000>, 818 <75000000>, <75000000>, 819 <32768>; 820 }; 821 822 usb2phy_grf: syscon@ff450000 { 823 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 824 "simple-mfd"; 825 reg = <0x0 0xff450000 0x0 0x10000>; 826 #address-cells = <1>; 827 #size-cells = <1>; 828 829 u2phy: usb2-phy@100 { 830 compatible = "rockchip,rk3328-usb2phy"; 831 reg = <0x100 0x10>; 832 clocks = <&xin24m>; 833 clock-names = "phyclk"; 834 clock-output-names = "usb480m_phy"; 835 #clock-cells = <0>; 836 assigned-clocks = <&cru USB480M>; 837 assigned-clock-parents = <&u2phy>; 838 status = "disabled"; 839 840 u2phy_otg: otg-port { 841 #phy-cells = <0>; 842 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 845 interrupt-names = "otg-bvalid", "otg-id", 846 "linestate"; 847 status = "disabled"; 848 }; 849 850 u2phy_host: host-port { 851 #phy-cells = <0>; 852 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 853 interrupt-names = "linestate"; 854 status = "disabled"; 855 }; 856 }; 857 }; 858 859 sdmmc: mmc@ff500000 { 860 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 861 reg = <0x0 0xff500000 0x0 0x4000>; 862 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 864 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 865 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 866 fifo-depth = <0x100>; 867 max-frequency = <150000000>; 868 status = "disabled"; 869 }; 870 871 sdio: mmc@ff510000 { 872 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 873 reg = <0x0 0xff510000 0x0 0x4000>; 874 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 876 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 877 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 878 fifo-depth = <0x100>; 879 max-frequency = <150000000>; 880 status = "disabled"; 881 }; 882 883 emmc: mmc@ff520000 { 884 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 885 reg = <0x0 0xff520000 0x0 0x4000>; 886 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 888 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 889 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 890 fifo-depth = <0x100>; 891 max-frequency = <150000000>; 892 status = "disabled"; 893 }; 894 895 gmac2io: ethernet@ff540000 { 896 compatible = "rockchip,rk3328-gmac"; 897 reg = <0x0 0xff540000 0x0 0x10000>; 898 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 899 interrupt-names = "macirq"; 900 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 901 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 902 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 903 <&cru PCLK_MAC2IO>; 904 clock-names = "stmmaceth", "mac_clk_rx", 905 "mac_clk_tx", "clk_mac_ref", 906 "clk_mac_refout", "aclk_mac", 907 "pclk_mac"; 908 resets = <&cru SRST_GMAC2IO_A>; 909 reset-names = "stmmaceth"; 910 rockchip,grf = <&grf>; 911 snps,txpbl = <0x4>; 912 status = "disabled"; 913 }; 914 915 gmac2phy: ethernet@ff550000 { 916 compatible = "rockchip,rk3328-gmac"; 917 reg = <0x0 0xff550000 0x0 0x10000>; 918 rockchip,grf = <&grf>; 919 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 920 interrupt-names = "macirq"; 921 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 922 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 923 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 924 <&cru SCLK_MAC2PHY_OUT>; 925 clock-names = "stmmaceth", "mac_clk_rx", 926 "mac_clk_tx", "clk_mac_ref", 927 "aclk_mac", "pclk_mac", 928 "clk_macphy"; 929 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; 930 reset-names = "stmmaceth", "mac-phy"; 931 phy-mode = "rmii"; 932 phy-handle = <&phy>; 933 snps,txpbl = <0x4>; 934 clock_in_out = "output"; 935 status = "disabled"; 936 937 mdio { 938 compatible = "snps,dwmac-mdio"; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 942 phy: ethernet-phy@0 { 943 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 944 reg = <0>; 945 clocks = <&cru SCLK_MAC2PHY_OUT>; 946 resets = <&cru SRST_MACPHY>; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 949 phy-is-integrated; 950 }; 951 }; 952 }; 953 954 usb20_otg: usb@ff580000 { 955 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 956 "snps,dwc2"; 957 reg = <0x0 0xff580000 0x0 0x40000>; 958 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&cru HCLK_OTG>; 960 clock-names = "otg"; 961 dr_mode = "otg"; 962 g-np-tx-fifo-size = <16>; 963 g-rx-fifo-size = <280>; 964 g-tx-fifo-size = <256 128 128 64 32 16>; 965 phys = <&u2phy_otg>; 966 phy-names = "usb2-phy"; 967 status = "disabled"; 968 }; 969 970 usb_host0_ehci: usb@ff5c0000 { 971 compatible = "generic-ehci"; 972 reg = <0x0 0xff5c0000 0x0 0x10000>; 973 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&cru HCLK_HOST0>, <&u2phy>; 975 phys = <&u2phy_host>; 976 phy-names = "usb"; 977 status = "disabled"; 978 }; 979 980 usb_host0_ohci: usb@ff5d0000 { 981 compatible = "generic-ohci"; 982 reg = <0x0 0xff5d0000 0x0 0x10000>; 983 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&cru HCLK_HOST0>, <&u2phy>; 985 phys = <&u2phy_host>; 986 phy-names = "usb"; 987 status = "disabled"; 988 }; 989 990 usbdrd3: usb@ff600000 { 991 compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; 992 reg = <0x0 0xff600000 0x0 0x100000>; 993 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 995 <&cru ACLK_USB3OTG>; 996 clock-names = "ref_clk", "suspend_clk", 997 "bus_clk"; 998 dr_mode = "otg"; 999 phy_type = "utmi_wide"; 1000 snps,dis-del-phy-power-chg-quirk; 1001 snps,dis_enblslpm_quirk; 1002 snps,dis-tx-ipgap-linecheck-quirk; 1003 snps,dis-u2-freeclk-exists-quirk; 1004 snps,dis_u2_susphy_quirk; 1005 snps,dis_u3_susphy_quirk; 1006 snps,parkmode-disable-ss-quirk; 1007 status = "disabled"; 1008 }; 1009 1010 gic: interrupt-controller@ff811000 { 1011 compatible = "arm,gic-400"; 1012 #interrupt-cells = <3>; 1013 #address-cells = <0>; 1014 interrupt-controller; 1015 reg = <0x0 0xff811000 0 0x1000>, 1016 <0x0 0xff812000 0 0x2000>, 1017 <0x0 0xff814000 0 0x2000>, 1018 <0x0 0xff816000 0 0x2000>; 1019 interrupts = <GIC_PPI 9 1020 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1021 }; 1022 1023 pinctrl: pinctrl { 1024 compatible = "rockchip,rk3328-pinctrl"; 1025 rockchip,grf = <&grf>; 1026 #address-cells = <2>; 1027 #size-cells = <2>; 1028 ranges; 1029 1030 gpio0: gpio0@ff210000 { 1031 compatible = "rockchip,gpio-bank"; 1032 reg = <0x0 0xff210000 0x0 0x100>; 1033 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&cru PCLK_GPIO0>; 1035 1036 gpio-controller; 1037 #gpio-cells = <2>; 1038 1039 interrupt-controller; 1040 #interrupt-cells = <2>; 1041 }; 1042 1043 gpio1: gpio1@ff220000 { 1044 compatible = "rockchip,gpio-bank"; 1045 reg = <0x0 0xff220000 0x0 0x100>; 1046 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&cru PCLK_GPIO1>; 1048 1049 gpio-controller; 1050 #gpio-cells = <2>; 1051 1052 interrupt-controller; 1053 #interrupt-cells = <2>; 1054 }; 1055 1056 gpio2: gpio2@ff230000 { 1057 compatible = "rockchip,gpio-bank"; 1058 reg = <0x0 0xff230000 0x0 0x100>; 1059 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&cru PCLK_GPIO2>; 1061 1062 gpio-controller; 1063 #gpio-cells = <2>; 1064 1065 interrupt-controller; 1066 #interrupt-cells = <2>; 1067 }; 1068 1069 gpio3: gpio3@ff240000 { 1070 compatible = "rockchip,gpio-bank"; 1071 reg = <0x0 0xff240000 0x0 0x100>; 1072 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1073 clocks = <&cru PCLK_GPIO3>; 1074 1075 gpio-controller; 1076 #gpio-cells = <2>; 1077 1078 interrupt-controller; 1079 #interrupt-cells = <2>; 1080 }; 1081 1082 pcfg_pull_up: pcfg-pull-up { 1083 bias-pull-up; 1084 }; 1085 1086 pcfg_pull_down: pcfg-pull-down { 1087 bias-pull-down; 1088 }; 1089 1090 pcfg_pull_none: pcfg-pull-none { 1091 bias-disable; 1092 }; 1093 1094 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1095 bias-disable; 1096 drive-strength = <2>; 1097 }; 1098 1099 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1100 bias-pull-up; 1101 drive-strength = <2>; 1102 }; 1103 1104 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1105 bias-pull-up; 1106 drive-strength = <4>; 1107 }; 1108 1109 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1110 bias-disable; 1111 drive-strength = <4>; 1112 }; 1113 1114 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1115 bias-pull-down; 1116 drive-strength = <4>; 1117 }; 1118 1119 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1120 bias-disable; 1121 drive-strength = <8>; 1122 }; 1123 1124 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1125 bias-pull-up; 1126 drive-strength = <8>; 1127 }; 1128 1129 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1130 bias-disable; 1131 drive-strength = <12>; 1132 }; 1133 1134 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1135 bias-pull-up; 1136 drive-strength = <12>; 1137 }; 1138 1139 pcfg_output_high: pcfg-output-high { 1140 output-high; 1141 }; 1142 1143 pcfg_output_low: pcfg-output-low { 1144 output-low; 1145 }; 1146 1147 pcfg_input_high: pcfg-input-high { 1148 bias-pull-up; 1149 input-enable; 1150 }; 1151 1152 pcfg_input: pcfg-input { 1153 input-enable; 1154 }; 1155 1156 i2c0 { 1157 i2c0_xfer: i2c0-xfer { 1158 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1159 <2 RK_PD1 1 &pcfg_pull_none>; 1160 }; 1161 }; 1162 1163 i2c1 { 1164 i2c1_xfer: i2c1-xfer { 1165 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1166 <2 RK_PA5 2 &pcfg_pull_none>; 1167 }; 1168 }; 1169 1170 i2c2 { 1171 i2c2_xfer: i2c2-xfer { 1172 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1173 <2 RK_PB6 1 &pcfg_pull_none>; 1174 }; 1175 }; 1176 1177 i2c3 { 1178 i2c3_xfer: i2c3-xfer { 1179 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1180 <0 RK_PA6 2 &pcfg_pull_none>; 1181 }; 1182 i2c3_pins: i2c3-pins { 1183 rockchip,pins = 1184 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1185 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1186 }; 1187 }; 1188 1189 hdmi_i2c { 1190 hdmii2c_xfer: hdmii2c-xfer { 1191 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1192 <0 RK_PA6 1 &pcfg_pull_none>; 1193 }; 1194 }; 1195 1196 pdm-0 { 1197 pdmm0_clk: pdmm0-clk { 1198 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1199 }; 1200 1201 pdmm0_fsync: pdmm0-fsync { 1202 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1203 }; 1204 1205 pdmm0_sdi0: pdmm0-sdi0 { 1206 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1207 }; 1208 1209 pdmm0_sdi1: pdmm0-sdi1 { 1210 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1211 }; 1212 1213 pdmm0_sdi2: pdmm0-sdi2 { 1214 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1215 }; 1216 1217 pdmm0_sdi3: pdmm0-sdi3 { 1218 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1219 }; 1220 1221 pdmm0_clk_sleep: pdmm0-clk-sleep { 1222 rockchip,pins = 1223 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1224 }; 1225 1226 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1227 rockchip,pins = 1228 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1229 }; 1230 1231 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1232 rockchip,pins = 1233 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1234 }; 1235 1236 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1237 rockchip,pins = 1238 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1239 }; 1240 1241 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1242 rockchip,pins = 1243 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1244 }; 1245 1246 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1247 rockchip,pins = 1248 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1249 }; 1250 }; 1251 1252 tsadc { 1253 otp_pin: otp-pin { 1254 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1255 }; 1256 1257 otp_out: otp-out { 1258 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1259 }; 1260 }; 1261 1262 uart0 { 1263 uart0_xfer: uart0-xfer { 1264 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1265 <1 RK_PB0 1 &pcfg_pull_up>; 1266 }; 1267 1268 uart0_cts: uart0-cts { 1269 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1270 }; 1271 1272 uart0_rts: uart0-rts { 1273 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1274 }; 1275 1276 uart0_rts_pin: uart0-rts-pin { 1277 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1278 }; 1279 }; 1280 1281 uart1 { 1282 uart1_xfer: uart1-xfer { 1283 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, 1284 <3 RK_PA6 4 &pcfg_pull_up>; 1285 }; 1286 1287 uart1_cts: uart1-cts { 1288 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1289 }; 1290 1291 uart1_rts: uart1-rts { 1292 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1293 }; 1294 1295 uart1_rts_pin: uart1-rts-pin { 1296 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1297 }; 1298 }; 1299 1300 uart2-0 { 1301 uart2m0_xfer: uart2m0-xfer { 1302 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, 1303 <1 RK_PA1 2 &pcfg_pull_up>; 1304 }; 1305 }; 1306 1307 uart2-1 { 1308 uart2m1_xfer: uart2m1-xfer { 1309 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 1310 <2 RK_PA1 1 &pcfg_pull_up>; 1311 }; 1312 }; 1313 1314 spi0-0 { 1315 spi0m0_clk: spi0m0-clk { 1316 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1317 }; 1318 1319 spi0m0_cs0: spi0m0-cs0 { 1320 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1321 }; 1322 1323 spi0m0_tx: spi0m0-tx { 1324 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1325 }; 1326 1327 spi0m0_rx: spi0m0-rx { 1328 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1329 }; 1330 1331 spi0m0_cs1: spi0m0-cs1 { 1332 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1333 }; 1334 }; 1335 1336 spi0-1 { 1337 spi0m1_clk: spi0m1-clk { 1338 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1339 }; 1340 1341 spi0m1_cs0: spi0m1-cs0 { 1342 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1343 }; 1344 1345 spi0m1_tx: spi0m1-tx { 1346 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1347 }; 1348 1349 spi0m1_rx: spi0m1-rx { 1350 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1351 }; 1352 1353 spi0m1_cs1: spi0m1-cs1 { 1354 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1355 }; 1356 }; 1357 1358 spi0-2 { 1359 spi0m2_clk: spi0m2-clk { 1360 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1361 }; 1362 1363 spi0m2_cs0: spi0m2-cs0 { 1364 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1365 }; 1366 1367 spi0m2_tx: spi0m2-tx { 1368 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1369 }; 1370 1371 spi0m2_rx: spi0m2-rx { 1372 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1373 }; 1374 }; 1375 1376 i2s1 { 1377 i2s1_mclk: i2s1-mclk { 1378 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1379 }; 1380 1381 i2s1_sclk: i2s1-sclk { 1382 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1383 }; 1384 1385 i2s1_lrckrx: i2s1-lrckrx { 1386 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1387 }; 1388 1389 i2s1_lrcktx: i2s1-lrcktx { 1390 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1391 }; 1392 1393 i2s1_sdi: i2s1-sdi { 1394 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1395 }; 1396 1397 i2s1_sdo: i2s1-sdo { 1398 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1399 }; 1400 1401 i2s1_sdio1: i2s1-sdio1 { 1402 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1403 }; 1404 1405 i2s1_sdio2: i2s1-sdio2 { 1406 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1407 }; 1408 1409 i2s1_sdio3: i2s1-sdio3 { 1410 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1411 }; 1412 1413 i2s1_sleep: i2s1-sleep { 1414 rockchip,pins = 1415 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1416 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1417 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1418 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1419 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1420 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1421 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1422 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1423 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1424 }; 1425 }; 1426 1427 i2s2-0 { 1428 i2s2m0_mclk: i2s2m0-mclk { 1429 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1430 }; 1431 1432 i2s2m0_sclk: i2s2m0-sclk { 1433 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1434 }; 1435 1436 i2s2m0_lrckrx: i2s2m0-lrckrx { 1437 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1438 }; 1439 1440 i2s2m0_lrcktx: i2s2m0-lrcktx { 1441 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1442 }; 1443 1444 i2s2m0_sdi: i2s2m0-sdi { 1445 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1446 }; 1447 1448 i2s2m0_sdo: i2s2m0-sdo { 1449 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1450 }; 1451 1452 i2s2m0_sleep: i2s2m0-sleep { 1453 rockchip,pins = 1454 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1455 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1456 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1457 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1458 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1459 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1460 }; 1461 }; 1462 1463 i2s2-1 { 1464 i2s2m1_mclk: i2s2m1-mclk { 1465 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1466 }; 1467 1468 i2s2m1_sclk: i2s2m1-sclk { 1469 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1470 }; 1471 1472 i2s2m1_lrckrx: i2sm1-lrckrx { 1473 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1474 }; 1475 1476 i2s2m1_lrcktx: i2s2m1-lrcktx { 1477 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1478 }; 1479 1480 i2s2m1_sdi: i2s2m1-sdi { 1481 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1482 }; 1483 1484 i2s2m1_sdo: i2s2m1-sdo { 1485 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1486 }; 1487 1488 i2s2m1_sleep: i2s2m1-sleep { 1489 rockchip,pins = 1490 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1491 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1492 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1493 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1494 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1495 }; 1496 }; 1497 1498 spdif-0 { 1499 spdifm0_tx: spdifm0-tx { 1500 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1501 }; 1502 }; 1503 1504 spdif-1 { 1505 spdifm1_tx: spdifm1-tx { 1506 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1507 }; 1508 }; 1509 1510 spdif-2 { 1511 spdifm2_tx: spdifm2-tx { 1512 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1513 }; 1514 }; 1515 1516 sdmmc0-0 { 1517 sdmmc0m0_pwren: sdmmc0m0-pwren { 1518 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1519 }; 1520 1521 sdmmc0m0_pin: sdmmc0m0-pin { 1522 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1523 }; 1524 }; 1525 1526 sdmmc0-1 { 1527 sdmmc0m1_pwren: sdmmc0m1-pwren { 1528 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1529 }; 1530 1531 sdmmc0m1_pin: sdmmc0m1-pin { 1532 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1533 }; 1534 }; 1535 1536 sdmmc0 { 1537 sdmmc0_clk: sdmmc0-clk { 1538 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1539 }; 1540 1541 sdmmc0_cmd: sdmmc0-cmd { 1542 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1543 }; 1544 1545 sdmmc0_dectn: sdmmc0-dectn { 1546 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1547 }; 1548 1549 sdmmc0_wrprt: sdmmc0-wrprt { 1550 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1551 }; 1552 1553 sdmmc0_bus1: sdmmc0-bus1 { 1554 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1555 }; 1556 1557 sdmmc0_bus4: sdmmc0-bus4 { 1558 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1559 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1560 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1561 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1562 }; 1563 1564 sdmmc0_pins: sdmmc0-pins { 1565 rockchip,pins = 1566 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1567 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1568 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1569 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1570 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1571 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1572 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1573 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1574 }; 1575 }; 1576 1577 sdmmc0ext { 1578 sdmmc0ext_clk: sdmmc0ext-clk { 1579 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1580 }; 1581 1582 sdmmc0ext_cmd: sdmmc0ext-cmd { 1583 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1584 }; 1585 1586 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1587 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1588 }; 1589 1590 sdmmc0ext_dectn: sdmmc0ext-dectn { 1591 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1592 }; 1593 1594 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1595 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1596 }; 1597 1598 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1599 rockchip,pins = 1600 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1601 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1602 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1603 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1604 }; 1605 1606 sdmmc0ext_pins: sdmmc0ext-pins { 1607 rockchip,pins = 1608 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1609 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1610 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1611 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1612 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1613 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1614 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1615 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1616 }; 1617 }; 1618 1619 sdmmc1 { 1620 sdmmc1_clk: sdmmc1-clk { 1621 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1622 }; 1623 1624 sdmmc1_cmd: sdmmc1-cmd { 1625 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1626 }; 1627 1628 sdmmc1_pwren: sdmmc1-pwren { 1629 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1630 }; 1631 1632 sdmmc1_wrprt: sdmmc1-wrprt { 1633 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1634 }; 1635 1636 sdmmc1_dectn: sdmmc1-dectn { 1637 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1638 }; 1639 1640 sdmmc1_bus1: sdmmc1-bus1 { 1641 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1642 }; 1643 1644 sdmmc1_bus4: sdmmc1-bus4 { 1645 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1646 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1647 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1648 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1649 }; 1650 1651 sdmmc1_pins: sdmmc1-pins { 1652 rockchip,pins = 1653 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1654 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1655 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1656 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1657 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1658 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1659 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1660 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1661 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1662 }; 1663 }; 1664 1665 emmc { 1666 emmc_clk: emmc-clk { 1667 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1668 }; 1669 1670 emmc_cmd: emmc-cmd { 1671 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1672 }; 1673 1674 emmc_pwren: emmc-pwren { 1675 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1676 }; 1677 1678 emmc_rstnout: emmc-rstnout { 1679 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1680 }; 1681 1682 emmc_bus1: emmc-bus1 { 1683 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1684 }; 1685 1686 emmc_bus4: emmc-bus4 { 1687 rockchip,pins = 1688 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1689 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1690 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1691 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1692 }; 1693 1694 emmc_bus8: emmc-bus8 { 1695 rockchip,pins = 1696 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1697 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1698 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1699 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1700 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1701 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1702 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1703 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1704 }; 1705 }; 1706 1707 pwm0 { 1708 pwm0_pin: pwm0-pin { 1709 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1710 }; 1711 }; 1712 1713 pwm1 { 1714 pwm1_pin: pwm1-pin { 1715 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1716 }; 1717 }; 1718 1719 pwm2 { 1720 pwm2_pin: pwm2-pin { 1721 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1722 }; 1723 }; 1724 1725 pwmir { 1726 pwmir_pin: pwmir-pin { 1727 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1728 }; 1729 }; 1730 1731 gmac-1 { 1732 rgmiim1_pins: rgmiim1-pins { 1733 rockchip,pins = 1734 /* mac_txclk */ 1735 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1736 /* mac_rxclk */ 1737 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1738 /* mac_mdio */ 1739 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1740 /* mac_txen */ 1741 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1742 /* mac_clk */ 1743 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1744 /* mac_rxdv */ 1745 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1746 /* mac_mdc */ 1747 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1748 /* mac_rxd1 */ 1749 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1750 /* mac_rxd0 */ 1751 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1752 /* mac_txd1 */ 1753 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1754 /* mac_txd0 */ 1755 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1756 /* mac_rxd3 */ 1757 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1758 /* mac_rxd2 */ 1759 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1760 /* mac_txd3 */ 1761 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1762 /* mac_txd2 */ 1763 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1764 1765 /* mac_txclk */ 1766 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1767 /* mac_txen */ 1768 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1769 /* mac_clk */ 1770 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1771 /* mac_txd1 */ 1772 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1773 /* mac_txd0 */ 1774 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1775 /* mac_txd3 */ 1776 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1777 /* mac_txd2 */ 1778 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1779 }; 1780 1781 rmiim1_pins: rmiim1-pins { 1782 rockchip,pins = 1783 /* mac_mdio */ 1784 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1785 /* mac_txen */ 1786 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1787 /* mac_clk */ 1788 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1789 /* mac_rxer */ 1790 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1791 /* mac_rxdv */ 1792 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1793 /* mac_mdc */ 1794 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1795 /* mac_rxd1 */ 1796 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1797 /* mac_rxd0 */ 1798 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1799 /* mac_txd1 */ 1800 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1801 /* mac_txd0 */ 1802 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1803 1804 /* mac_mdio */ 1805 <0 RK_PB3 1 &pcfg_pull_none>, 1806 /* mac_txen */ 1807 <0 RK_PB4 1 &pcfg_pull_none>, 1808 /* mac_clk */ 1809 <0 RK_PD0 1 &pcfg_pull_none>, 1810 /* mac_mdc */ 1811 <0 RK_PC3 1 &pcfg_pull_none>, 1812 /* mac_txd1 */ 1813 <0 RK_PC0 1 &pcfg_pull_none>, 1814 /* mac_txd0 */ 1815 <0 RK_PC1 1 &pcfg_pull_none>; 1816 }; 1817 }; 1818 1819 gmac2phy { 1820 fephyled_speed10: fephyled-speed10 { 1821 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1822 }; 1823 1824 fephyled_duplex: fephyled-duplex { 1825 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1826 }; 1827 1828 fephyled_rxm1: fephyled-rxm1 { 1829 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1830 }; 1831 1832 fephyled_txm1: fephyled-txm1 { 1833 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1834 }; 1835 1836 fephyled_linkm1: fephyled-linkm1 { 1837 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1838 }; 1839 }; 1840 1841 tsadc_pin { 1842 tsadc_int: tsadc-int { 1843 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1844 }; 1845 tsadc_pin: tsadc-pin { 1846 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1847 }; 1848 }; 1849 1850 hdmi_pin { 1851 hdmi_cec: hdmi-cec { 1852 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1853 }; 1854 1855 hdmi_hpd: hdmi-hpd { 1856 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1857 }; 1858 }; 1859 1860 cif-0 { 1861 dvp_d2d9_m0:dvp-d2d9-m0 { 1862 rockchip,pins = 1863 /* cif_d0 */ 1864 <3 RK_PA4 2 &pcfg_pull_none>, 1865 /* cif_d1 */ 1866 <3 RK_PA5 2 &pcfg_pull_none>, 1867 /* cif_d2 */ 1868 <3 RK_PA6 2 &pcfg_pull_none>, 1869 /* cif_d3 */ 1870 <3 RK_PA7 2 &pcfg_pull_none>, 1871 /* cif_d4 */ 1872 <3 RK_PB0 2 &pcfg_pull_none>, 1873 /* cif_d5m0 */ 1874 <3 RK_PB1 2 &pcfg_pull_none>, 1875 /* cif_d6m0 */ 1876 <3 RK_PB2 2 &pcfg_pull_none>, 1877 /* cif_d7m0 */ 1878 <3 RK_PB3 2 &pcfg_pull_none>, 1879 /* cif_href */ 1880 <3 RK_PA1 2 &pcfg_pull_none>, 1881 /* cif_vsync */ 1882 <3 RK_PA0 2 &pcfg_pull_none>, 1883 /* cif_clkoutm0 */ 1884 <3 RK_PA3 2 &pcfg_pull_none>, 1885 /* cif_clkin */ 1886 <3 RK_PA2 2 &pcfg_pull_none>; 1887 }; 1888 }; 1889 1890 cif-1 { 1891 dvp_d2d9_m1:dvp-d2d9-m1 { 1892 rockchip,pins = 1893 /* cif_d0 */ 1894 <3 RK_PA4 2 &pcfg_pull_none>, 1895 /* cif_d1 */ 1896 <3 RK_PA5 2 &pcfg_pull_none>, 1897 /* cif_d2 */ 1898 <3 RK_PA6 2 &pcfg_pull_none>, 1899 /* cif_d3 */ 1900 <3 RK_PA7 2 &pcfg_pull_none>, 1901 /* cif_d4 */ 1902 <3 RK_PB0 2 &pcfg_pull_none>, 1903 /* cif_d5m1 */ 1904 <2 RK_PC0 4 &pcfg_pull_none>, 1905 /* cif_d6m1 */ 1906 <2 RK_PC1 4 &pcfg_pull_none>, 1907 /* cif_d7m1 */ 1908 <2 RK_PC2 4 &pcfg_pull_none>, 1909 /* cif_href */ 1910 <3 RK_PA1 2 &pcfg_pull_none>, 1911 /* cif_vsync */ 1912 <3 RK_PA0 2 &pcfg_pull_none>, 1913 /* cif_clkoutm1 */ 1914 <2 RK_PB7 4 &pcfg_pull_none>, 1915 /* cif_clkin */ 1916 <3 RK_PA2 2 &pcfg_pull_none>; 1917 }; 1918 }; 1919 }; 1920}; 1921